From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/p1020-post.dtsi | 2 ++ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24 ++++++++++++++++++++- include/configs/P1022DS.h | 4 +++- include/configs/p1_p2_rdb_pc.h | 9 +++++++- 4 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1c77702f01..1dce8e86e9 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,6 +44,8 @@ clock-frequency = <0>; };

+ /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" };

/* PCIe controller base address 0x9000 */ diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 71fca8ca1e..f668d7efb1 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -227,6 +228,7 @@ int checkboard(void) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, io_config, val; + int bus_num = CONFIG_SYS_SPD_BUS_NUM;

printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7 +236,26 @@ int checkboard(void) in_8(&cpld_data->pcba_rev) & 0x0F);

/* Initialize i2c early for rom_loc and flash bank information */ - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); + #if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + + if (dm_i2c_read(dev, 0, &in, 1) < 0 || + dm_i2c_read(dev, 1, &out, 1) < 0 || + dm_i2c_read(dev, 3, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + #else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num);

if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || @@ -242,6 +263,7 @@ int checkboard(void) printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } + #endif

val = (in & io_config) | (out & (~io_config));

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5cc2e06979..f8b035fb79 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -359,8 +359,8 @@ #endif

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -368,6 +368,8 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#endif +#define CONFIG_SYS_I2C_FSL

/* * I2C2 EEPROM diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce..d59fd033bd 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -537,8 +538,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -546,6 +547,12 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */

From: Biwen Li biwen.li@nxp.com

This adds i2c node for board P2020RDB

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/p2020-post.dtsi | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 5bbd5c5468..4ed093dad4 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -37,6 +37,9 @@ /* Filled in by U-Boot */ clock-frequency = <0>; }; + + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" };

/* PCIe controller base address 0x8000 */

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for board P2041RDB

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/p2041.dtsi | 5 ++++- include/configs/P2041RDB.h | 9 ++++++++- 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 0f5e7dbdc8..95931e299d 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -3,7 +3,7 @@ * P2041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -86,6 +86,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe200000 { diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f6472b9e11..f1eb6d7100 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -267,14 +268,20 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL +

/* * RapidIO

From: Biwen Li biwen.li@nxp.com

This adds i2c node for SoC P3041

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/p3041.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 6736d00035..3152683b84 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -3,7 +3,7 @@ * P3041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2010 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -86,6 +86,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe200000 {

From: Biwen Li biwen.li@nxp.com

This adds i2c node for SoC P4080

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/p4080.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 02f39fbfcb..4a80561e18 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -3,7 +3,7 @@ * P4080/P4040 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -97,6 +97,8 @@ reg = <0x211000 0x1000>; phy_type = "ulpi"; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe200000 {

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC T1023/T1024

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/t102x.dtsi | 4 +- board/freescale/t102xqds/t102xqds.c | 94 ++++++++++++++++++++++++++++- board/freescale/t102xqds/t102xqds.h | 3 +- board/freescale/t102xrdb/t102xrdb.c | 70 +++++++++++++++++++-- include/configs/T102xQDS.h | 10 ++- include/configs/T102xRDB.h | 8 ++- 6 files changed, 179 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index a6b821a76a..521825d85a 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -3,7 +3,7 @@ * T102X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -75,6 +75,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe240000 { diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index e42337e47a..0bff011ff8 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -75,11 +76,23 @@ int checkboard(void) return 0; }

-int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + }

+ ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -191,6 +204,82 @@ void board_retimer_ds125df111_init(void) { u8 reg;

+#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret, bus_num = 0; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) + goto failed; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + dm_i2c_write(dev, 0, &reg, 1); + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) + goto failed; + + reg = I2C_MUX_CH5; + dm_i2c_write(dev, 0, &reg, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) + goto failed; + reg = 0x0; + dm_i2c_write(dev, 0xff, &reg, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, &reg, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, &reg, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, &reg, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, &reg, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, &reg, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, &reg, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, &reg, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, &reg, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + dm_i2c_read(dev, 0x1e, &reg, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, &reg, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, &reg, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, &reg, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, &reg, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, &reg, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, &reg, 1); + return; + +failed: + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; +#else /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ reg = I2C_MUX_CH7; i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1); @@ -241,6 +330,7 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); +#endif }

int board_early_init_f(void) @@ -281,7 +371,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_mux_lane_to_slot(); board_retimer_ds125df111_init();

diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h index 15de132598..d327b5edb9 100644 --- a/board/freescale/t102xqds/t102xqds.h +++ b/board/freescale/t102xqds/t102xqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#ifndef __T102x_QDS_H__ @@ -8,6 +9,6 @@

void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_num);

#endif diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index eee09a5701..71ca9a5361 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -250,8 +251,68 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) { ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 val, orig_bus = i2c_get_bus_num(); + u32 val; u8 tmp; + int bus_num = I2C_PCA6408_BUS_NUM; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + dm_i2c_read(dev, 0, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + return tmp; + case I2C_SET_BANK0: + tmp = 0x0; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + tmp = 0x1; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#else + u32 orig_bus; + orig_bus = i2c_get_bus_num();

switch (ctrl_type) { case GPIO1_SD_SEL: @@ -275,14 +336,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) val = 0; return val; case I2C_GET_BANK: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); tmp &= 0x7; tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); i2c_set_bus_num(orig_bus); return tmp; case I2C_SET_BANK0: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x0; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -291,7 +352,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) out_be32(&gur->rstcr, 0x2); break; case I2C_SET_BANK4: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x1; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -301,6 +362,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) default: break; } +#endif return 0; }

diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 8ac260c2bc..2b61fa56e5 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -437,14 +438,20 @@ unsigned long get_board_ddr_clk(void); #endif

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */

#define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -460,6 +467,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0

/* * RTC configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 43897a711a..b9dbc01f08 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -434,15 +435,20 @@ unsigned long get_board_ddr_clk(void); #endif

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif

+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC P1010

Signed-off-by: Biwen Li biwen.li@nxp.com --- board/freescale/p1010rdb/p1010rdb.c | 159 +++++++++++++++++++++++++++- include/configs/P1010RDB.h | 8 +- 2 files changed, 164 insertions(+), 3 deletions(-)

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index a086692683..f49e679d01 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp;

+#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; +#if defined(CONFIG_TARGET_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR1, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x01; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x05; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_TARGET_P1010RDB_PB) + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_TDM: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x82); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x82); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CAN: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + default: + break; + } +#endif +#else #if defined(CONFIG_TARGET_P1010RDB_PA) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);

@@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type) break; } i2c_set_bus_num(orig_bus); +#endif #endif return 0; } @@ -250,9 +371,24 @@ int config_board_mux(int ctrl_type) int i2c_pca9557_read(int type) { u8 val; - - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + int bus_num = I2C_PCA9557_BUS_NUM; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + dm_i2c_read(dev, 0, &val, 1); +#else + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); +#endif

switch (type) { case I2C_READ_BANK: @@ -280,11 +416,26 @@ int checkboard(void) printf("Board: %sRDB-PA, ", cpu->name); #elif defined(CONFIG_TARGET_P1010RDB_PB) printf("Board: %sRDB-PB, ", cpu->name); +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + val = 0x0; /* no polarity inversion */ + dm_i2c_write(dev, 2, &val, 1); +#else i2c_set_bus_num(I2C_PCA9557_BUS_NUM); i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); val = 0x0; /* no polarity inversion */ i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); #endif +#endif

#ifdef CONFIG_SDCARD /* switch to IFC to read info from CPLD */ @@ -308,7 +459,11 @@ int checkboard(void) case 0xe: puts("SDHC\n"); val = 0x60; /* set pca9557 pin input/output */ +#ifdef CONFIG_DM_I2C + dm_i2c_write(dev, 3, &val, 1); +#else i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); +#endif break; case 0x5: config_board_mux(MUX_TYPE_IFC); diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 60e8904d42..41dbbedecc 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -522,17 +523,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define I2C_PCA9557_ADDR1 0x18 #define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0 +#define CONFIG_SYS_I2C_FSL

/* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB)

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for board MPC8548CDS

Signed-off-by: Biwen Li biwen.li@nxp.com --- board/freescale/common/sys_eeprom.c | 3 ++- include/configs/MPC8548CDS.h | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6f151b0f71..c52af7060e 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -589,6 +589,7 @@ unsigned int get_cpu_board_revision(void) u8 major; /* 0x04 Board revision, major */ u8 minor; /* 0x05 Board revision, minor */ } be; + int ret;

#ifndef CONFIG_DM_I2C i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, @@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void) #else ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev) + &dev); #endif if (!ret) dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a68d190f6a..b7796236fd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. + * Copyright 2020 NXP */

/* @@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL

/* EEPROM */ #define CONFIG_ID_EEPROM

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC T4240

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/t4240.dtsi | 5 +- board/freescale/common/vsc3316_3308.c | 255 +++++++++++++++++++++++++- board/freescale/t4qds/t4240qds.c | 43 ++++- include/configs/T4240QDS.h | 13 ++ include/configs/T4240RDB.h | 9 +- 5 files changed, 315 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 43f98cd9e1..9b5902fe9e 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -3,7 +3,7 @@ * T4240 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -125,6 +125,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe240000 { diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 033fae020f..3fb702aba1 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include "vsc3316_3308.h" @@ -32,7 +33,22 @@ int vsc_if_enable(unsigned int vsc_addr)

/* enable 2-wire Serial InterFace (I2C) */ data = 0x02; +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); +#else return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); +#endif }

int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], @@ -45,6 +61,65 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], debug("VSC:Initializing VSC3316 at I2C address 0x%2x" " for Tx\n", vsc_addr);

+#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Configuring the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0x80); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); + +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -90,6 +165,7 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],

/* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); +#endif

vsc_wp_config(vsc_addr);

@@ -107,6 +183,104 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", vsc_addr);

+#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Configure Global Input ISE */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); + + /* Configure Tx/Rx Global Output PE1 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); + + /* Configure Tx/Rx Global Output PE2 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); + + /* Configure Tx/Rx Global Input GAIN */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); + + /* Setting Global output termination */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); + + /* Configure Tx/Rx Global Output level */ + if (vsc_addr == VSC3308_TX_ADDRESS) + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); + else + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning off all the required input of the switch */ + for (i = 0; i < num_con; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 2, 0); + dm_i2c_reg_write(dev, 3, 0); + } else { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn off the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } else { + dm_i2c_reg_write(dev, 3, 0); + dm_i2c_reg_write(dev, 4, 0); + } + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -192,7 +366,7 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],

/* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr);

return 0; @@ -208,7 +382,68 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],

debug("VSC:Initializing VSC3308 at I2C address 0x%x" " for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);

+ /*Configure Global Input ISE and gain */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning ON the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -258,7 +493,7 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],

/* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr);

return 0; @@ -270,6 +505,22 @@ void vsc_wp_config(unsigned int vsc_addr)

/* For new crosspoint configuration to occur, WP bit of * CORE_CONFIG_REG should be set 1 and then reset to 0 */ +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); +#else i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); +#endif } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 5608774afd..5656e9c048 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -91,11 +92,25 @@ int checkboard(void) return 0; }

-int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret;

+#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -115,10 +130,26 @@ static inline int read_voltage(void) { int i, ret, voltage_read = 0; u16 vol_mon; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int bus_num = 0; +#endif

for (i = 0; i < NUM_READINGS; i++) { +#ifdef CONFIG_DM_I2C + ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, (void *)&vol_mon, 2); +#else ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -250,7 +281,7 @@ static int adjust_vdd(ulong vdd_override) unsigned voltage; };

- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0); if (ret) { debug("VID: I2c failed to switch channel\n"); ret = -1; @@ -348,7 +379,7 @@ int config_frontside_crossbar_vsc3316(void) u32 srds_prtcl_s1, srds_prtcl_s2; int ret;

- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0); if (ret) return ret;

@@ -567,7 +598,7 @@ int board_early_init_r(void) /* Configure board SERDES ports crossbar */ config_frontside_crossbar_vsc3316(); config_backside_crossbar_mux(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

return 0; } @@ -732,11 +763,11 @@ void board_detail(void) }

/* Voltage secion */ - if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { + if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) { vdd = read_voltage(); if (vdd > 0) printf("Core voltage= %d mV\n", vdd); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); }

printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 94e0ddbd88..f89d43c3a3 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -280,6 +280,19 @@ unsigned long get_board_ddr_clk(void); #endif

/* I2C */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#else +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_FSL_I2C2_OFFSET +#undef CONFIG_SYS_FSL_I2C2_SLAVE +#undef CONFIG_SYS_FSL_I2C2_SPEED +#undef CONFIG_SYS_FSL_I2C_SLAVE +#undef CONFIG_SYS_FSL_I2C_SPEED +#undef CONFIG_SYS_FSL_I2C_OFFSET +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 042757c20e..4c0b9ada62 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -159,12 +160,18 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL

/* * General PCI

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC T2080/T2081

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/t2080.dtsi | 4 +++- board/freescale/t208xqds/t208xqds.c | 19 ++++++++++++++++--- include/configs/T208xQDS.h | 7 ++++++- include/configs/T208xRDB.h | 10 +++++++++- 4 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index 458019ae92..a9e9b404f6 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -3,7 +3,7 @@ * T2080/T2081 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2018 NXP + * Copyright 2018,2020 NXP */

/dts-v1/; @@ -96,6 +96,8 @@ sata-number = <2>; sata-fpdma = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe240000 { diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 79cc1543f9..9100401022 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -75,11 +76,23 @@ int checkboard(void) return 0; }

-int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret;

+#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -90,7 +103,7 @@ int select_i2c_ch_pca9547(u8 ch)

int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); }

int brd_mux_lane_to_slot(void) @@ -368,7 +381,7 @@ int board_early_init_r(void) printf("Warning: Adjusting core voltage failed.\n");

brd_mux_lane_to_slot(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

return 0; } diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index be5a658d7e..fb44ae9a4c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -385,8 +386,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -399,6 +400,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 68de90fbbb..71dd9e79c7 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

/* @@ -333,8 +334,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -347,6 +348,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */

From: Biwen Li biwen.li@nxp.com

This supports i2c DM for SoC T1040/T1042

Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/powerpc/dts/t104x.dtsi | 4 +++- board/freescale/t1040qds/diu.c | 5 +++-- board/freescale/t1040qds/t1040qds.c | 18 ++++++++++++++++-- board/freescale/t1040qds/t1040qds.h | 3 ++- include/configs/T1040QDS.h | 7 +++++++ include/configs/T104xRDB.h | 10 +++++++++- 6 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index 093aaab834..0a08a69f31 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -3,7 +3,7 @@ * T104X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */

/dts-v1/; @@ -85,6 +85,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" };

pcie@ffe240000 { diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ab9e922a92..0b1aeed69e 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * Author: Priyanka Jain Priyanka.Jain@freescale.com */

@@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock)

/* Program HDMI encoder */ /* Switch channel to DIU */ - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);

/* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); @@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock) }

/* Switch channel to default */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

/* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 92dd9237ec..90c5d15ab2 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#include <common.h> @@ -79,11 +80,24 @@ int checkboard(void) return 0; }

-int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret;

+#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -154,7 +168,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

return 0; } diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h index d2f0203f17..781bcdefc9 100644 --- a/board/freescale/t1040qds/t1040qds.h +++ b/board/freescale/t1040qds/t1040qds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#ifndef __T1040_QDS_H__ @@ -8,6 +9,6 @@

void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_bum);

#endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index aa2a8b00de..f7e6376587 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -1,5 +1,6 @@ /* * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * See file CREDITS for list of people who contributed to this * project. @@ -360,6 +361,8 @@ unsigned long get_board_ddr_clk(void); #endif

/* I2C */ + +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ @@ -374,6 +377,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */

#define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -385,6 +391,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0

/* * RTC configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 50b37acf05..1c8fc6c3dd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */

#ifndef __CONFIG_H @@ -27,6 +28,7 @@ #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_DM_I2C #endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif

/* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 @@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif

+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0

/* * RTC configuration

-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Biwen Li Sent: Friday, April 17, 2020 3:57 PM To: Jagdish Gediya jagdish.gediya@nxp.com; Priyanka Jain priyanka.jain@nxp.com; hs@denx.de; jagan@amarulasolutions.com; aford173@gmail.com; Alison Wang alison.wang@nxp.com; jh80.chung@samsung.com; Pramod Kumar pramod.kumar_1@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com; olteanv@gmail.com Cc: Xiaobo Xie xiaobo.xie@nxp.com; Jiafei Pan jiafei.pan@nxp.com; u- boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; Biwen Li biwen.li@nxp.com Subject: [v2 01/27] rtc: ds1337: Add driver model support

From: Biwen Li biwen.li@nxp.com

Add support of driver model of ds1337

Signed-off-by: Biwen Li biwen.li@nxp.com

drivers/rtc/ds1337.c | 127 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+)

diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 9b31048e97..e12d368675 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /*

• (C) Copyright 2001-2008

• • Copyright 2020 NXP

• Wolfgang Denk, DENX Software Engineering, wd@denx.de.
• Keith Outwater, keith_outwater@mvis.com`

*/ @@ -12,6 +13,7 @@

#include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h>

@@ -60,6 +62,7 @@ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */

+#if !CONFIG_IS_ENABLED(DM_RTC) static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val);

@@ -188,3 +191,127 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } +#else +static uchar rtc_read (struct udevice *dev, uchar reg) {

• return (dm_i2c_reg_read (dev, reg));

+}

+static void rtc_write (struct udevice *dev, uchar reg, uchar val) {

• dm_i2c_reg_write (dev, reg, val);

+}

+static int ds1337_rtc_get (struct udevice *dev, struct rtc_time *tmp) {

• int rel = 0;
• uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
• control = rtc_read (dev, RTC_CTL_REG_ADDR);
• status = rtc_read (dev, RTC_STAT_REG_ADDR);
• sec = rtc_read (dev, RTC_SEC_REG_ADDR);
• min = rtc_read (dev, RTC_MIN_REG_ADDR);
• hour = rtc_read (dev, RTC_HR_REG_ADDR);
• wday = rtc_read (dev, RTC_DAY_REG_ADDR);
• mday = rtc_read (dev, RTC_DATE_REG_ADDR);
• mon_cent = rtc_read (dev, RTC_MON_REG_ADDR);
• year = rtc_read (dev, RTC_YR_REG_ADDR);
• /* No century bit, assume year 2000 */ #ifdef CONFIG_RTC_DS1388
• mon_cent |= 0x80;

+#endif

• debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x

"

• "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
  

• year, mon_cent, mday, wday, hour, min, sec, control, status);
  

• if (status & RTC_STAT_BIT_OSF) {

• printf ("### Warning: RTC oscillator has stopped\n");
  

• /* clear the OSF flag */
  

• rtc_write (dev, RTC_STAT_REG_ADDR,
  

• 	   rtc_read (dev, RTC_STAT_REG_ADDR) &
  

~RTC_STAT_BIT_OSF);

• rel = -1;
  

• }
• tmp->tm_sec = bcd2bin (sec & 0x7F);
• tmp->tm_min = bcd2bin (min & 0x7F);
• tmp->tm_hour = bcd2bin (hour & 0x3F);
• tmp->tm_mday = bcd2bin (mday & 0x3F);
• tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
• tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
• tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
• tmp->tm_yday = 0;
• tmp->tm_isdst= 0;
• debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME:

%2d:%02d:%02d\n",

• tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
  

...

tm_wday,

• tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  

• return rel;

+}

+static int ds1337_rtc_set (struct udevice *dev, const struct rtc_time +*tmp) {

• uchar century;
• debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME:

%2d:%02d:%02d\n",

• tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
  

...

tm_wday,

• tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  

• rtc_write (dev, RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
• century = (tmp->tm_year >= 2000) ? 0x80 : 0;
• rtc_write (dev, RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) |

century);

• rtc_write (dev, RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
• rtc_write (dev, RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
• rtc_write (dev, RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
• rtc_write (dev, RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
• rtc_write (dev, RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
• return 0;

+}

+#ifdef CONFIG_RTC_DS1337_NOOSC

• #define RTC_DS1337_RESET_VAL \
• (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #else

#define +RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #endif static +int ds1337_rtc_reset (struct udevice *dev) { #ifdef CONFIG_RTC_DS1337

• rtc_write (dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); #elif

defined +CONFIG_RTC_DS1388

• rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ #endif

#ifdef +CONFIG_RTC_DS1339_TCR_VAL

• rtc_write (dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);

#endif +#ifdef CONFIG_RTC_DS1388_TCR_VAL

• rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);

#endif

• return 0;

+}

+static const struct rtc_ops ds1337_rtc_ops = {

• .get = ds1337_rtc_get,
• .set = ds1337_rtc_set,
• .reset = ds1337_rtc_reset,

+};

+static const struct udevice_id ds1337_rtc_ids[] = {

• { .compatible = "ds1337" },
• { .compatible = "ds1338" },
• { .compatible = "ds1338" },
• { }

+};

+U_BOOT_DRIVER(rtc_ds1337) = {

• .name = "rtc-ds1337",
• .id = UCLASS_RTC,
• .of_match = ds1337_rtc_ids,
• .ops = &ds1337_rtc_ops,

+};

+#endif

2.17.1

Reviewed-by: Priyanka Jain priyanka.jain@nxp.com