[U-Boot] [PATCH 1/4] ARM: uniphier: enable DWC3 xHCI driver

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Masahiro Yamada

13 Oct 2017 13 Oct '17

7:21 p.m.

Enable CONFIGs for the DWC3 core and the UniPhier specific glue layer.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

configs/uniphier_v7_defconfig | 2 ++ configs/uniphier_v8_defconfig | 2 ++ 2 files changed, 4 insertions(+)

diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 12b24bc..96e962d 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -48,4 +48,6 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_UNIPHIER=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 796839b..31dd9b3 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -45,4 +45,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_UNIPHIER=y CONFIG_USB_STORAGE=y

-- 2.7.4

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Masahiro Yamada

13 Oct 13 Oct

7:21 p.m.

New subject: [U-Boot] [PATCH 2/4] ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG

Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/clk/clk-pro4.c | 6 +++--- arch/arm/mach-uniphier/clk/clk-pro5.c | 6 +++--- arch/arm/mach-uniphier/clk/clk-pxs2.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 19be4f3..8a978d2 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -17,7 +17,7 @@ void uniphier_pro4_clk_init(void)

/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | SC_RSTCTRL_NRST_GIO; #endif @@ -30,7 +30,7 @@ void uniphier_pro4_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */

-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; writel(tmp, SC_RSTCTRL2); @@ -39,7 +39,7 @@ void uniphier_pro4_clk_init(void)

/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c index 823bb06..dd86cad 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-pro5.c @@ -15,7 +15,7 @@ void uniphier_pro5_clk_init(void)

/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI @@ -24,7 +24,7 @@ void uniphier_pro5_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */

-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); @@ -33,7 +33,7 @@ void uniphier_pro5_clk_init(void)

/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 0d92405..9775127 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -16,7 +16,7 @@ void uniphier_pxs2_clk_init(void)

/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_UNIPHIER_ETH @@ -28,7 +28,7 @@ void uniphier_pxs2_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */

-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); @@ -41,7 +41,7 @@ void uniphier_pxs2_clk_init(void)

/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif

-- 2.7.4

Masahiro Yamada

7:21 p.m.

New subject: [U-Boot] [PATCH 3/4] mtd: nand: denali_dt: add clock support

Enable clock in the probe hook. The clock rate will be necessary when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/mtd/nand/denali.h | 1 + drivers/mtd/nand/denali_dt.c | 12 ++++++++++++ 2 files changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 08db488..f796f0d 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -435,6 +435,7 @@ struct nand_buf {

struct denali_nand_info { struct nand_chip nand; + unsigned long clk_x_rate; /* bus interface clock rate */ int flash_bank; /* currently selected chip */ int status; int platform; diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 4afd679..805c066 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -6,6 +6,7 @@ */

#include <common.h> +#include <clk.h> #include <dm.h> #include <linux/io.h> #include <linux/ioport.h> @@ -52,6 +53,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; + struct clk clk; struct resource res; int ret;

@@ -73,6 +75,16 @@ static int denali_dt_probe(struct udevice *dev)

denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));

+ ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + denali->clk_x_rate = clk_get_rate(&clk); + return denali_init(denali); }

-- 2.7.4

Masahiro Yamada

7:21 p.m.

New subject: [U-Boot] [PATCH 4/4] clk: uniphier: add NAND controller clock

This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index f8cf6da..c852c78 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -7,10 +7,20 @@

#include "clk-uniphier.h"

+/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ +#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ + UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) + +#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ + UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) + const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + UNIPHIER_LD4_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ @@ -23,6 +33,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {

const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ @@ -33,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {

const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */

-- 2.7.4

Masahiro Yamada

15 Oct 15 Oct

3:37 p.m.

2017-10-14 2:21 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:

...

Enable CONFIGs for the DWC3 core and the UniPhier specific glue layer.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com

Series, applied to u-boot-uniphier.

-- Best Regards Masahiro Yamada

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Masahiro Yamada