The driver makes it possible to use an application UART as the U-Boot output console for Freescale i.MX23/i.MX28 devices.

Signed-off-by: Andreas Wass andreas.wass@dalelven.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Marek Vasut marex@denx.de --- Changes for v2: - Added comment that regs-uartapp.h is pulled from LTIB - BM_ prefixes removed and _MASK suffixes added instead - BP_ prefixes removed and _OFFSET suffixes added instead - BF_ defines removed altogether - CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed - Added comments describing what is set and unset during init of driver - Added newline that was accidently removed from serial.c

Changes for v3: - All BV_ values are now on the form (value << something) - BV_ prefix removed and double underscore substituted with a single - File comment of mxs_auart.c now attributes what the driver is based on - Uses gd->baudrate instead of CONFIG_BAUDRATE - If gd->baudrate is 0 it reverts back to CONFIG_BAUDRATE - Checks the validity of the div value calculated when setting the baudrate - Magic numbers are now defines instead - Cleanup of comments - Cleanup of commit message

Changes for v4: - Fixed UARTAPP_LINECTRL2_WLEN_*BITS values

drivers/serial/Makefile | 1 + drivers/serial/mxs_auart.c | 151 ++++++++++++++++ drivers/serial/serial.c | 2 + 4 files changed, 403 insertions(+) create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h create mode 100644 drivers/serial/mxs_auart.c

diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644 index 0000000..abd62c2 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -0,0 +1,249 @@ +/* + * Freescale MXS UARTAPP Register Definitions + * + * Copyright (C) 2013 Andreas Wass andreas.wass@dalelven.com + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include <asm/imx-common/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) + mxs_reg_32(hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) + mxs_reg_32(hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) + mxs_reg_32(hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) + mxs_reg_32(hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 << 4) +#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF0000 +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL1_RSVD2_OFFSET 29 +#define UARTAPP_CTRL1_RSVD2_MASK 0xE0000000 + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) +#define UARTAPP_CTRL1_RSVD1_OFFSET 16 +#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF0000 + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RSVD2_MASK (1 << 23) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK 0x00700000 + +#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) +#define UARTAPP_CTRL2_RSVD3_MASK (1 << 19) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK 0x00070000 +#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) +#define UARTAPP_CTRL2_RSVD4_OFFSET 3 +#define UARTAPP_CTRL2_RSVD4_MASK 0x00000038 + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK (1 << 0) + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK 0xFFFF0000 +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL_RSVD_OFFSET 14 +#define UARTAPP_LINECTRL_RSVD_MASK 0x0000C000 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK 0x00003F00 +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x0000003F + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK 0x00000060 +#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK (1 << 0) + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK 0xFFFF0000 +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL2_RSVD_OFFSET 14 +#define UARTAPP_LINECTRL2_RSVD_MASK 0x0000C000 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK 0x00003F00 +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x0000003F + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK 0x00000060 +#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) + + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL2_RSVD1_MASK (1 << 0) + +#define UARTAPP_INTR_RSVD1_OFFSET 28 +#define UARTAPP_INTR_RSVD1_MASK 0xF0000000 + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) +#define UARTAPP_INTR_RSVD2_OFFSET 12 +#define UARTAPP_INTR_RSVD2_MASK 0x0000F000 + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK (1 << 0) + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) +#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) +#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK 0x00F00000 + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0x0000FFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK 0xFFFF0000 + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK 0x0000FC00 + +#define UARTAPP_DEBUG_RSVD1_OFFSET 6 +#define UARTAPP_DEBUG_RSVD1_MASK 0x000003C0 + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK (1 << 0) + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK 0xFF000000 + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK 0x00FF0000 + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0x0000FFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK 0xFF000000 + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK 0x00FF0000 + +#define UARTAPP_AUTOBAUD_RSVD1_OFFSET 5 +#define UARTAPP_AUTOBAUD_RSVD1_MASK 0x0000FFE0 + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK (1 << 0) +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 697f2bb..4c45bfa 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o +COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o

ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/mxs_auart.c b/drivers/serial/mxs_auart.c new file mode 100644 index 0000000..7cfe5bc --- /dev/null +++ b/drivers/serial/mxs_auart.c @@ -0,0 +1,151 @@ +/* + * Freescale i.MX23/i.MX28 AUART driver + * + * Copyright (C) 2013 Andreas Wass andreas.wass@dalelven.com + * + * Based on the MXC serial driver: + * + * (c) 2007 Sascha Hauer s.hauer@pengutronix.de + * + * Further based on the Linux mxs-auart.c driver: + * + * Freescale STMP37XX/STMP38X Application UART drkiver + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> +#include <asm/arch/regs-base.h> +#include <asm/arch/regs-uartapp.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_MXS_AUART_BASE +#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use" +#endif + +/* AUART clock always supplied by XTAL and always 24MHz */ +#define MXS_AUART_CLK 24000000 + +static struct mxs_uartapp_regs *get_uartapp_registers(void) +{ + return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE; +} + +/** + * Sets the baud rate and settings. + * The settings are: 8 data bits, no parit and 1 stop bit. + */ +void mxs_auart_setbrg(void) +{ + u32 div; + u32 linectrl = 0; + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + /* + * From i.MX28 datasheet: + * div is calculated by calculating UARTCLK*32/baudrate, rounded to int + * div must be between 0xEC and 0x003FFFC0 inclusive + * Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register + * Next 16 bits goes in BAUD_DIVINT part of LINECTRL register + */ + div = (MXS_AUART_CLK * 32) / gd->baudrate; + if (div < 0xEC || div > 0x003FFFC0) + return; + + linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) << + UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) & + UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK; + linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) << + UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) & + UARTAPP_LINECTRL_BAUD_DIVINT_MASK; + + /* Word length: 8 bits */ + linectrl |= UARTAPP_LINECTRL_WLEN_8BITS; + + /* Enable FIFOs. */ + linectrl |= UARTAPP_LINECTRL_FEN_MASK; + + /* Write above settings, no parity, 1 stop bit */ + writel(linectrl, &regs->hw_uartapp_linectrl); +} + +int mxs_auart_init(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Reset everything */ + mxs_reset_block(&regs->hw_uartapp_ctrl0_reg); + /* Disable interrupts */ + writel(0, &regs->hw_uartapp_intr); + /* Set baud rate and settings */ + serial_setbrg(); + /* Disable RTS and CTS, ignore LINECTRL2 register */ + writel(UARTAPP_CTRL2_RTSEN_MASK | + UARTAPP_CTRL2_CTSEN_MASK | + UARTAPP_CTRL2_USE_LCR2_MASK, + &regs->hw_uartapp_ctrl2_clr); + /* Enable receiver, transmitter and UART */ + writel(UARTAPP_CTRL2_RXE_MASK | + UARTAPP_CTRL2_TXE_MASK | + UARTAPP_CTRL2_UARTEN_MASK, + &regs->hw_uartapp_ctrl2_set); + return 0; +} + +void mxs_auart_putc(const char c) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Wait in loop while the transmit FIFO is full */ + while (readl(&regs->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK) + ; + + writel(c, &regs->hw_uartapp_data); + + if (c == '\n') + mxs_auart_putc('\r'); +} + +int mxs_auart_tstc(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Checks if receive FIFO is empty */ + return !(readl(&regs->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK); +} + +int mxs_auart_getc(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Wait until a character is available to read */ + while (!mxs_auart_tstc()) + ; + /* Read the character from the data register */ + return readl(&regs->hw_uartapp_data) & 0xFF; +} + +static struct serial_device mxs_auart_drv = { + .name = "mxs_auart_serial", + .start = mxs_auart_init, + .stop = NULL, + .setbrg = mxs_auart_setbrg, + .putc = mxs_auart_putc, + .puts = default_serial_puts, + .getc = mxs_auart_getc, + .tstc = mxs_auart_tstc, +}; + +void mxs_auart_initialize(void) +{ + serial_register(&mxs_auart_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &mxs_auart_drv; +} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 6730135..336ff35 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -159,6 +159,7 @@ serial_initfunc(pl01x_serial_initialize); serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); +serial_initfunc(mxs_auart_initialize);

/** * serial_register() - Register serial driver with serial driver core @@ -251,6 +252,7 @@ void serial_initialize(void) s3c44b0_serial_initialize(); sa1100_serial_initialize(); sh_serial_initialize(); + mxs_auart_initialize();

serial_assign(default_serial_console()->name); }