Some PCIe devices require longer time to response. Increase polling counter to 20000 (~100ms).

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- drivers/pci/pcie_intel_fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 3cdf05b314..e74b35ac16 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -56,7 +56,7 @@ #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) #define TLP_HDR_SIZE 3 -#define TLP_LOOP 500 +#define TLP_LOOP 20000 #define DWORD_MASK 3

#define IS_ROOT_PORT(pcie, bdf) \

Hardware return completion status non-zero when read from non exist function in multi-function PCIe device. Return error will cause PCIe enumeration fail.

Change it to return 0 and return value 0xffffffff when error.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- drivers/pci/pcie_intel_fpga.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index e74b35ac16..a096d1c697 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -161,8 +161,10 @@ static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value) dw[count++] = cra_readl(pcie, RP_RXCPL_REG); if (ctrl & RP_RXCPL_EOP) { comp_status = TLP_COMP_STATUS(dw[1]); - if (comp_status) - return -EFAULT; + if (comp_status) { + *value = pci_get_ff(PCI_SIZE_32); + return 0; + }

if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&

This fix issue when access config from PCIe switch.

The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link.

The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- drivers/pci/pcie_intel_fpga.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index a096d1c697..a5ea4888f3 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -36,16 +36,18 @@

#define RP_CFG_ADDR(pcie, reg) \ ((pcie->hip_base) + (reg) + (1 << 20)) +#define RP_SECONDARY(pcie) \ + readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))

#define TLP_CFGRD_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \ - : TLP_FMTTYPE_CFGRD1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \ + : TLP_FMTTYPE_CFGRD0) << 24) | \ TLP_PAYLOAD_SIZE)

#define TLP_CFGWR_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \ - : TLP_FMTTYPE_CFGWR1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \ + : TLP_FMTTYPE_CFGWR0) << 24) | \ TLP_PAYLOAD_SIZE)

#define TLP_CFG_DW1(pcie, tag, be) \