Enable the PIO peripherals early that other peripherals.

Signed-off-by: Bo Shen voice.shen@atmel.com --- board/atmel/sama5d3xek/sama5d3xek.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index b0965ef..7fa3ae7 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -158,6 +158,9 @@ void lcd_show_board_info(void)

int board_early_init_f(void) { + at91_periph_clk_enable(ATMEL_ID_PIOA | ATMEL_ID_PIOB | ATMEL_ID_PIOC | + ATMEL_ID_PIOD | ATMEL_ID_PIOE); + at91_seriald_hw_init();

return 0;

As the DBGU and PIT has its own ID on sama5d3 SoC, while not share with SYS ID. So, correct them.

Signed-off-by: Bo Shen voice.shen@atmel.com --- arch/arm/cpu/armv7/at91/sama5d3_devices.c | 2 +- arch/arm/cpu/armv7/at91/timer.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 51f0a6d..ebe99d2 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -82,7 +82,7 @@ void at91_seriald_hw_init(void) at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */

/* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_DBGU); }

#if defined(CONFIG_ATMEL_SPI) diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c index 3808aed..e3ebfe0 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/cpu/armv7/at91/timer.c @@ -60,7 +60,7 @@ int timer_init(void) at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;

/* Enable PITC Clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_PIT);

/* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

Correct the error define of DIV.

Signed-off-by: Bo Shen voice.shen@atmel.com --- arch/arm/include/asm/arch-at91/at91_pmc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 0d82960..c063213 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -128,8 +128,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif

-#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 +#define AT91_PMC_MCKR_PLLADIV_1 0x00000000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00001000

#define AT91_PMC_IXR_MOSCS 0x00000001 #define AT91_PMC_IXR_LOCKA 0x00000002

The MPDDRC supports different type of SDRAM This patch add ddr2 initialization function

Signed-off-by: Bo Shen voice.shen@atmel.com --- arch/arm/cpu/armv7/at91/Makefile | 1 + arch/arm/cpu/armv7/at91/mpddrc.c | 123 +++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 111 ++++++++++++++++++++++ 3 files changed, 235 insertions(+) create mode 100644 arch/arm/cpu/armv7/at91/mpddrc.c create mode 100644 arch/arm/include/asm/arch-at91/atmel_mpddrc.h

diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile index 90b9bd6..4a02d06 100644 --- a/arch/arm/cpu/armv7/at91/Makefile +++ b/arch/arm/cpu/armv7/at91/Makefile @@ -17,6 +17,7 @@ COBJS-y += clock.o COBJS-y += cpu.o COBJS-y += reset.o COBJS-y += timer.o +COBJS-$(CONFIG_SPL_BUILD) += mpddrc.o

SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/arm/cpu/armv7/at91/mpddrc.c b/arch/arm/cpu/armv7/at91/mpddrc.c new file mode 100644 index 0000000..1abde1e --- /dev/null +++ b/arch/arm/cpu/armv7/at91/mpddrc.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen voice.shen@atmel.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/atmel_mpddrc.h> + +static void atmel_mpddr_op(int mode, u32 ram_address) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + + writel(mode, &mpddr->mr); + writel(0, ram_address); +} + +int ddr2_init(u32 ram_address, struct atmel_mpddr *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 ba_off, cr; + + /* Compute bank offset according to NC in configuration register */ + ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; + if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) + ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + + ba_off += (mpddr_value->mdr & ATMEL_MPDDRC_MDR_DBW_MASK) ? 1 : 2; + + /* Program the memory device type into the memory device register */ + writel(mpddr_value->mdr, &mpddr->mdr); + + /* Program the configuration register */ + writel(mpddr_value->cr, &mpddr->cr); + + /* Program the timing register */ + writel(mpddr_value->tp0r, &mpddr->tp0r); + writel(mpddr_value->tp1r, &mpddr->tp1r); + writel(mpddr_value->tp2r, &mpddr->tp2r); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_NOP_CMD, ram_address); + + /* A 200 us is provided to precede any signal toggle */ + udelay(200); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_NOP_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_PRCGALL_CMD, ram_address); + + /* Issue an extended mode register set(EMRS2) to choose operation */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD, + ram_address + (0x2 << ba_off)); + + /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD, + ram_address + (0x3 << ba_off)); + + /* + * Issue an extended mode register set(EMRS1) to enable DLL and + * program D.I.C (output driver impedance control) + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* Enable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_EN_RESET_DLL, &mpddr->cr); + + /* A mode register set(MRS) cycle is issued to reset DLL */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_LMR_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_PRCGALL_CMD, ram_address); + + /* Two auto-refresh (CBR) cycles are provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_RFSH_CMD, ram_address); + atmel_mpddr_op(ATMEL_MPDDRC_MR_RFSH_CMD, ram_address); + + /* Disable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_EN_RESET_DLL), &mpddr->cr); + + /* A mode register set (MRS) cycle is issued to disable DLL reset */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_LMR_CMD, ram_address); + + /* Set OCD calibration in defautl state */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to OCD default value + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* OCD calibration mode exit */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to enable OCD exit + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* A nornal mode command is provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_NORMAL_CMD, ram_address); + + /* Perform a write access to any DDR2-SDRAM address */ + writel(0, ram_address); + + /* Write the refresh rate */ + writel(mpddr_value->rtr, &mpddr->rtr); + + return 0; +} diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h new file mode 100644 index 0000000..abd8b68 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen voice.shen@atmel.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_MPDDRC_H__ +#define __ATMEL_MPDDRC_H__ + +struct atmel_mpddr { + u32 mr; + u32 rtr; + u32 cr; + u32 tp0r; + u32 tp1r; + u32 tp2r; + u32 reserved[2]; + u32 mdr; +}; + +int ddr2_init(unsigned int ram_address, + struct atmel_mpddr *mpddr); + +/* bit field in mode register */ +#define ATMEL_MPDDRC_MR_NORMAL_CMD 0x0 +#define ATMEL_MPDDRC_MR_NOP_CMD 0x1 +#define ATMEL_MPDDRC_MR_PRCGALL_CMD 0x2 +#define ATMEL_MPDDRC_MR_LMR_CMD 0x3 +#define ATMEL_MPDDRC_MR_RFSH_CMD 0x4 +#define ATMEL_MPDDRC_MR_EXT_LMR_CMD 0x5 +#define ATMEL_MPDDRC_MR_DEEP_CMD 0x6 +#define ATMEL_MPDDRC_MR_LPDDR2_CMD 0x7 + +/* bit field in configuration register */ +#define ATMEL_MPDDRC_CR_NC_MASK 0x3 +#define ATMEL_MPDDRC_CR_NC_COL_9 0x0 +#define ATMEL_MPDDRC_CR_NC_COL_10 0x1 +#define ATMEL_MPDDRC_CR_NC_COL_11 0x2 +#define ATMEL_MPDDRC_CR_NC_COL_12 0x3 +#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) +#define ATMEL_MPDDRC_CR_CAS (0x7 << 4) +#define ATMEL_MPDDRC_CR_CAS_2 (0x2 << 4) +#define ATMEL_MPDDRC_CR_CAS_3 (0x3 << 4) +#define ATMEL_MPDDRC_CR_CAS_4 (0x4 << 4) +#define ATMEL_MPDDRC_CR_CAS_5 (0x5 << 4) +#define ATMEL_MPDDRC_CR_CAS_6 (0x6 << 4) +#define ATMEL_MPDDRC_CR_EN_RESET_DLL (0x1 << 7) +#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) +#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) +#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_EN_ENRDM (0x1 << 17) +#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) +#define ATMEL_MPDDRC_CR_DIS_NDQS (0x1 << 21) +#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) +#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) + +/* bit field in timing parameter 0 register */ +#define ATMEL_MPDDRC_TP0R_TRAS_OFFSET 0 +#define ATMEL_MPDDRC_TP0R_TRAS_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TRCD_OFFSET 4 +#define ATMEL_MPDDRC_TP0R_TRCD_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TWR_OFFSET 8 +#define ATMEL_MPDDRC_TP0R_TWR_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TRC_OFFSET 12 +#define ATMEL_MPDDRC_TP0R_TRC_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TRP_OFFSET 16 +#define ATMEL_MPDDRC_TP0R_TRP_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TRRD_OFFSET 20 +#define ATMEL_MPDDRC_TP0R_TRRD_MASK 0xf +#define ATMEL_MPDDRC_TP0R_TWTR_OFFSET 24 +#define ATMEL_MPDDRC_TP0R_TWTR_MASK 0x7 +#define ATMEL_MPDDRC_TP0R_RDC_WRRD_OFFSET 27 +#define ATMEL_MPDDRC_TP0R_RDC_WRRD_MASK 0x1 +#define ATMEL_MPDDRC_TP0R_TMRD_OFFSET 28 +#define ATMEL_MPDDRC_TP0R_TMRD_MASK 0xf + +/* bit field in timing parameter 1 register */ +#define ATMEL_MPDDRC_TP1R_TRFC_OFFSET 0 +#define ATMEL_MPDDRC_TP1R_TRFC_MASK 0x7f +#define ATMEL_MPDDRC_TP1R_TXSNR_OFFSET 8 +#define ATMEL_MPDDRC_TP1R_TXSNR_MASK 0xff +#define ATMEL_MPDDRC_TP1R_TXSRD_OFFSET 16 +#define ATMEL_MPDDRC_TP1R_TXSRD_MASK 0xff +#define ATMEL_MPDDRC_TP1R_TXP_OFFSET 24 +#define ATMEL_MPDDRC_TP1R_TXP_MASK 0xf + +/* bit field in timing parameter 2 register */ +#define ATMEL_MPDDRC_TP2R_TXARD_OFFSET 0 +#define ATMEL_MPDDRC_TP2R_TXARD_MASK 0xf +#define ATMEL_MPDDRC_TP2R_TXARDS_OFFSET 4 +#define ATMEL_MPDDRC_TP2R_TXARDS_MASK 0xf +#define ATMEL_MPDDRC_TP2R_TRPA_OFFSET 8 +#define ATMEL_MPDDRC_TP2R_TRPA_MASK 0xf +#define ATMEL_MPDDRC_TP2R_TRTP_OFFSET 12 +#define ATMEL_MPDDRC_TP2R_TRTP_MASK 0x7 +#define ATMEL_MPDDRC_TP2R_TFAW_OFFSET 16 +#define ATMEL_MPDDRC_TP2R_TFAW_MASK 0xf + +/* bit field in Memory Device Register */ +#define ATMEL_MPDDRC_MDR_LPDDR_SDRAM 0x3 +#define ATMEL_MPDDRC_MDR_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MDR_DBW_MASK (0x1 << 4) +#define ATMEL_MPDDRC_MDR_DBW_32BITS (0x0 << 4) +#define ATMEL_MPDDRC_MDR_DBW_16BITS (0x1 << 4) + +#endif