[U-Boot] [PATCH v2 1/4] imx: mx6slevk: Add I2C1 support
Add I2C1 pin and pad settings, and enable the MXC I2C driver.
Signed-off-by: Ye.Li B37916@freescale.com --- Changes since v1: - None
arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++++ board/freescale/mx6slevk/mx6slevk.c | 26 ++++++++++++++++++++++++++ include/configs/mx6slevk.h | 6 ++++++ 3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4..ac84270 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -34,5 +34,10 @@ enum { MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), + MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), + MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index a990b4c..fedd5c3 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -13,12 +13,14 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <linux/sizes.h> #include <common.h> #include <fsl_esdhc.h> #include <mmc.h> #include <netdev.h> +#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info0 = { + .sda = { + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, + .scl = { + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, +}; + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -162,6 +185,9 @@ int board_init(void) #ifdef CONFIG_FEC_MXC setup_fec(); #endif + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + return 0; }
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3d05a64..bf5066f 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -60,6 +60,12 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li B37916@freescale.com --- Changes since v1: - None
board/freescale/mx6slevk/mx6slevk.c | 57 +++++++++++++++++++++++++++++++++++ include/configs/mx6slevk.h | 7 ++++ 2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index fedd5c3..8b6a79c 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,6 +21,8 @@ #include <mmc.h> #include <netdev.h> #include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define I2C_PMIC 0 + /* I2C1 for PMIC */ struct i2c_pads_info i2c_pad_info0 = { .sda = { @@ -191,6 +195,59 @@ int board_init(void) return 0; }
+static int pfuze_init(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE%s ID=0x%02x\n", + ((reg & 0xf) == 0) ? "100" : "200", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return 0; +} + +int board_late_init(void) +{ + pfuze_init(); + + return 0; +} + u32 get_board_rev(void) { return get_cpu_rev(); diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index bf5066f..09d0896 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -30,6 +30,7 @@ #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART @@ -66,6 +67,12 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1
Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.
Signed-off-by: Ye.Li B37916@freescale.com --- Changes since v1: - None
board/freescale/mx6sabresd/mx6sabresd.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5f65f1b..72d6562 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -472,7 +472,8 @@ static int pfuze_init(void) return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + printf("PMIC: PFUZE%s ID=0x%02x\n", + ((reg & 0xf) == 0) ? "100" : "200", reg);
/* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.
Changes for boards: -mx6 sabreauto -mx6 sabresd -mx6slevk -mx6sxsabresd
Signed-off-by: Ye.Li B37916@freescale.com --- Changes since v1: - Correct the return code per Fabio's comments.
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 36 +++++++++++++++++++++++++ board/freescale/mx6sabresd/mx6sabresd.c | 36 +++++++++++++++++++++++++ board/freescale/mx6slevk/mx6slevk.c | 36 +++++++++++++++++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 36 +++++++++++++++++++++++++ 4 files changed, 144 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 76b024b..9e79915 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -263,6 +263,37 @@ int board_init(void) return 0; }
+/* set all switches APS in normal and PFM mode in standby */ +static int pfuze_setup_mode(struct pmic *p, int chip) +{ + unsigned char offset, i, switch_num, value; + + if (!chip) { + /* pfuze100 */ + switch_num = 6; + offset = 0x31; + } else { + /* pfuze200 */ + switch_num = 4; + offset = 0x38; + } + + value = 0xc; + if (pmic_reg_write(p, 0x23, value)) { + printf("Set SW1AB mode error!\n"); + return -1; + } + + for (i = 0; i < switch_num - 1; i++) { + if (pmic_reg_write(p, offset + i * 7, value)) { + printf("Set switch%x mode error!\n", offset); + return -1; + } + } + + return 0; +} + static int pfuze_init(void) { struct pmic *p; @@ -281,6 +312,11 @@ static int pfuze_init(void) pmic_reg_read(p, PFUZE100_DEVICEID, ®); printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ if (pfuze_setup_mode(p, (reg & 0xf))) { + printf("setup pfuze mode error!\n"); + return -1; + } + /* Set SW1AB stanby volage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~0x3f; diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 72d6562..810fe13 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -456,6 +456,37 @@ int board_init(void) return 0; }
+/* set all switches APS in normal and PFM mode in standby */ +static int pfuze_setup_mode(struct pmic *p, int chip) +{ + unsigned char offset, i, switch_num, value; + + if (!chip) { + /* pfuze100 */ + switch_num = 6; + offset = 0x31; + } else { + /* pfuze200 */ + switch_num = 4; + offset = 0x38; + } + + value = 0xc; + if (pmic_reg_write(p, 0x23, value)) { + printf("Set SW1AB mode error!\n"); + return -1; + } + + for (i = 0; i < switch_num - 1; i++) { + if (pmic_reg_write(p, offset + i * 7, value)) { + printf("Set switch%x mode error!\n", offset); + return -1; + } + } + + return 0; +} + static int pfuze_init(void) { struct pmic *p; @@ -475,6 +506,11 @@ static int pfuze_init(void) printf("PMIC: PFUZE%s ID=0x%02x\n", ((reg & 0xf) == 0) ? "100" : "200", reg);
+ if (pfuze_setup_mode(p, (reg & 0xf))) { + printf("setup pfuze mode error!\n"); + return -1; + } + /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); reg &= ~0xf; diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 8b6a79c..fe5e37d 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -195,6 +195,37 @@ int board_init(void) return 0; }
+/* set all switches APS in normal and PFM mode in standby */ +static int pfuze_setup_mode(struct pmic *p, int chip) +{ + unsigned char offset, i, switch_num, value; + + if (!chip) { + /* pfuze100 */ + switch_num = 6; + offset = 0x31; + } else { + /* pfuze200 */ + switch_num = 4; + offset = 0x38; + } + + value = 0xc; + if (pmic_reg_write(p, 0x23, value)) { + printf("Set SW1AB mode error!\n"); + return -1; + } + + for (i = 0; i < switch_num - 1; i++) { + if (pmic_reg_write(p, offset + i * 7, value)) { + printf("Set switch%x mode error!\n", offset); + return -1; + } + } + + return 0; +} + static int pfuze_init(void) { struct pmic *p; @@ -214,6 +245,11 @@ static int pfuze_init(void) printf("PMIC: PFUZE%s ID=0x%02x\n", ((reg & 0xf) == 0) ? "100" : "200", reg);
+ if (pfuze_setup_mode(p, (reg & 0xf))) { + printf("setup pfuze mode error!\n"); + return -1; + } + /* Set SW1AB stanby volage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~0x3f; diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 80d2d99..d6a33cd 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -170,6 +170,37 @@ struct i2c_pads_info i2c_pad_info1 = { }, };
+/* set all switches APS in normal and PFM mode in standby */ +static int pfuze_setup_mode(struct pmic *p, int chip) +{ + unsigned char offset, i, switch_num, value; + + if (!chip) { + /* pfuze100 */ + switch_num = 6; + offset = 0x31; + } else { + /* pfuze200 */ + switch_num = 4; + offset = 0x38; + } + + value = 0xc; + if (pmic_reg_write(p, 0x23, value)) { + printf("Set SW1AB mode error!\n"); + return -1; + } + + for (i = 0; i < switch_num - 1; i++) { + if (pmic_reg_write(p, offset + i * 7, value)) { + printf("Set switch%x mode error!\n", offset); + return -1; + } + } + + return 0; +} + static int pfuze_init(void) { struct pmic *p; @@ -188,6 +219,11 @@ static int pfuze_init(void) pmic_reg_read(p, PFUZE100_DEVICEID, ®); printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ if (pfuze_setup_mode(p, (reg & 0xf))) { + printf("setup pfuze mode error!\n"); + return -1; + } + /* Set SW1AB standby voltage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~0x3f;
On Wed, Sep 10, 2014 at 11:25 PM, Ye.Li B37916@freescale.com wrote:
Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.
Changes for boards: -mx6 sabreauto -mx6 sabresd -mx6slevk -mx6sxsabresd
Signed-off-by: Ye.Li B37916@freescale.com
Changes since v1:
- Correct the return code per Fabio's comments.
Are you sure about that?
I still see a lot of return -1 in this patch ;-)
On 9/11/2014 10:28 AM, Fabio Estevam wrote:
On Wed, Sep 10, 2014 at 11:25 PM, Ye.Li B37916@freescale.com wrote:
Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.
Changes for boards: -mx6 sabreauto -mx6 sabresd -mx6slevk -mx6sxsabresd
Signed-off-by: Ye.Li B37916@freescale.com
Changes since v1:
- Correct the return code per Fabio's comments.
Are you sure about that?
I still see a lot of return -1 in this patch ;-)
Sorry, my fault. Send out v3 soon.
Best regards, Ye Li
participants (3)
-
Fabio Estevam -
Li Ye-B37916 -
Ye.Li