Hello,

the I2C source clock frequency for the MPC8544 is determined in cpu/mpc85xx/speed.c:

#elif defined(CONFIG_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See * 4.4.3.3 of the 8544 RM. Note that this might actually work for all * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) gd->i2c1_clk = sys_info.freqSystemBus / 3; else gd->i2c1_clk = sys_info.freqSystemBus / 2;

On our MPC8544 the MPC85xx_PORDEVSR2_SEC_CFG is set and the diver 3 therefore used. But that seems to be wrong. Measurements show, that the used divider is 2. Any idea what's going wrong? Is there an errata for the MPC8544?

Wolfgang.