[PATCH 1/2] riscv: cpu: Add callback to init each core

Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup.
Signed-off-by: Green Wan green.wan@sifive.com Reviewed-by: Rick Chen rick@andestech.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- arch/riscv/cpu/cpu.c | 11 +++++++++++ arch/riscv/cpu/start.S | 4 ++++ 2 files changed, 15 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 85592f5bee..296e458db4 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -140,3 +140,14 @@ int arch_early_init_r(void) { return riscv_cpu_probe(); } + +/** + * harts_early_init() - A callback function called by start.S to configure + * feature settings of each hart. + * + * In a multi-core system, memory access shall be careful here, it shall + * take care of race conditions. + */ +__weak void harts_early_init(void) +{ +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..308b0a97a5 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,10 @@ call_board_init_f_0: mv sp, a0 #endif
+ /* Configure proprietary settings and customized CSRs of harts */ +call_harts_early_init: + jal harts_early_init + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts

Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_si...
Signed-off-by: Green Wan green.wan@sifive.com Reviewed-by: Sean Anderson seanga2@gmail.com Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Rick Chen rick@andestech.com --- arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index ea0b2283a2..55e30346ff 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -6,6 +6,9 @@
#include <dm.h> #include <log.h> +#include <asm/csr.h> + +#define CSR_U74_FEATURE_DISABLE 0x7c1
int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void)
return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +}
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Green Wan