From: Ludwig Zenz lzenz@dh-electronics.de

The four x16 DDR3 are wired in T-topology. From NXP AN4467: 'Although not required, T-Topologies may also benefit from performing Write Leveling as there are package delays on both the processor and DDR devices that can be de-skewed by performing Write Leveling. Therefore, Freescale recommends determining Write Leveling calibration parameters for all boards, regardless of topology used.' That is why write level calibration is also done.

Signed-off-by: Ludwig Zenz lzenz@dh-electronics.com --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 04e9eab272a..bbd2dc26828 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -482,6 +482,29 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); }

+/* Perform DDR DRAM calibration */ +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret = 0; + +#ifdef CONFIG_MX6_DDRCAL + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR3: Write level calibration error [%d]\n", ret); + return ret; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR3: DQS calibration error [%d]\n", ret); + return ret; + } +#endif /* CONFIG_MX6_DDRCAL */ + + return ret; +} +

/* DRAM */ static void dhcom_spl_dram_init(void) @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void) }

/* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit);

} else if (is_cpu_type(MXC_CPU_MX6DL)) { mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void) }

/* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit);

} else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void) }

/* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + spl_dram_perform_cal(&dhcom_ddr_32bit); } }