[U-Boot] [PATCH] ARM: arch-mx6: fix PLL2_PFD2_FREQ
From: Markus Niebel Markus.Niebel@tqs.de
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000
Signed-off-by: Markus Niebel Markus.Niebel@tqs.de --- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..2813593 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000
From: Markus Niebel Markus.Niebel@tqs.de
Currently the dual cora variant is detected and displayed as quad core. Add a define for MXC_CPU_MX6DUAL and implement the same SCU based approach done for MX6DL / MX6S
Signed-off-by: Markus Niebel Markus.Niebel@tqs.de --- arch/arm/cpu/armv7/mx6/soc.c | 6 ++++++ arch/arm/imx-common/cpu.c | 2 ++ arch/arm/include/asm/arch-mx5/sys_proto.h | 1 + arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 4 files changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a390296..1f65d85 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -42,6 +42,12 @@ u32 get_cpu_rev(void)
if (!cfg) type = MXC_CPU_MX6SOLO; + } else if (type == MXC_CPU_MX6Q) { + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; + + if (1 == cfg) + type = MXC_CPU_MX6DUAL; } } reg &= 0xff; /* mx6 silicon revision */ diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 0cd2538..77ef912 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -104,6 +104,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX6DUAL: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ case MXC_CPU_MX6DL: diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1..c2bec45 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -14,6 +14,7 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6DUAL 0x64
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 8c21364..227998c 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -16,6 +16,7 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6DUAL 0x64
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void);
On 11/09/2013 15:30, Markus Niebel wrote:
From: Markus Niebel Markus.Niebel@tqs.de
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000
Signed-off-by: Markus Niebel Markus.Niebel@tqs.de
arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..2813593 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Stefano Babic wrote
On 11/09/2013 15:30, Markus Niebel wrote:
From: Markus Niebel <
Markus.Niebel@
>
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000
Signed-off-by: Markus Niebel <
Markus.Niebel@
>
arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..2813593 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000
Acked-by: Stefano Babic <
sbabic@
>
Hello Markus, Hello Stephano I think it's better to compute this frequencies rather than hard coding values. The default PFD frequencies are not the same for the Quad and for the other Socs. Furthermore, if you modify PLL2_PFD2_FREQ, you must also change PLL2_PFD2_DIV_FREQ.
Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL PFD frequencies rather than using defines)
Best regards
-- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-ARM-arch-mx6-fix-PLL2-PFD2-FREQ-tp16... Sent from the U-Boot mailing list archive at Nabble.com.
Hello Pierre,
Am 20.09.2013 16:32, wrote Pierre Aubert:
Stefano Babic wrote
On 11/09/2013 15:30, Markus Niebel wrote:
From: Markus Niebel <
Markus.Niebel@
>
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000
Signed-off-by: Markus Niebel <
Markus.Niebel@
>
arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..2813593 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000
Acked-by: Stefano Babic <
sbabic@
>
Hello Markus, Hello Stephano I think it's better to compute this frequencies rather than hard coding values. The default PFD frequencies are not the same for the Quad and for the other Socs.
As far as I read the manual for i.MX6Q/D and i.MX6DL/S have the same default values.
Furthermore, if you modify PLL2_PFD2_FREQ, you must also change PLL2_PFD2_DIV_FREQ.
Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL PFD frequencies rather than using defines)
Hmm. Sounds reasonable.Do you expect any side effects? (We came accross the mismatch that was fixed with my original patch when looking over DRAM configuration)
Best regards
-- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-ARM-arch-mx6-fix-PLL2-PFD2-FREQ-tp16... Sent from the U-Boot mailing list archive at Nabble.com. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hello Markus,
Le 25/09/2013 09:24, Markus Niebel a écrit :
Hello Pierre,
arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..2813593 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000
Hello Markus, Hello Stephano I think it's better to compute this frequencies rather than hard coding values. The default PFD frequencies are not the same for the Quad and for the other Socs.
As far as I read the manual for i.MX6Q/D and i.MX6DL/S have the same default values.
For the i.MX6Q/D, the PLL2-PFD0 is 352MHz and the PLL2-PFD1 is 594MHz. For the i.MX6DL/S, the PLL2-PFD0 is 302.58MHz and the PLL2-PFD1 is 528MHz. The definitions in the crm_regs.h are for the i.MX6Q/D.
Furthermore, if you modify PLL2_PFD2_FREQ, you must also change PLL2_PFD2_DIV_FREQ.
Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL PFD frequencies rather than using defines)
Hmm. Sounds reasonable.Do you expect any side effects? (We came accross the mismatch that was fixed with my original patch when looking over DRAM configuration)
I've tested it on the SabreSD with i.MX6DL and on a custom board with i.MX6Q and i.MX6S and I didn't noticed any side effects.
Best regards
Hello Markus, Hello Stephano I think it's better to compute this frequencies rather than hard coding values. The default PFD frequencies are not the same for the Quad and for the other Socs. Furthermore, if you modify PLL2_PFD2_FREQ, you must also change PLL2_PFD2_DIV_FREQ.
Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL PFD frequencies rather than using defines)
This V2 patch: applied to u-boot-imx, -next branch, thanks !
Best regards, Stefano Babic
On 11/09/2013 15:30, Markus Niebel wrote:
From: Markus Niebel Markus.Niebel@tqs.de
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000
Signed-off-by: Markus Niebel Markus.Niebel@tqs.de
Applied to u-boot-imx, thanks!
Best regards, Stefano Babic
participants (5)
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Markus Niebel -
Markus Niebel -
Pierre AUBERT -
Pierre Aubert
-
Stefano Babic