Add a common board_interface_eth_init() called by the DWC MAC driver to setup the MAC <-> PHY interface according to the PHY mode obtained from DT. Remove the board-side configuration in the i.MX93 EVK files.

Signed-off-by: Sébastien Szymanski sebastien.szymanski@armadeus.com ---

Changes for v2: - none

arch/arm/mach-imx/imx9/clock.c | 53 +++++++++++++++++++++++++++ board/freescale/imx93_evk/imx93_evk.c | 16 -------- 2 files changed, 53 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 766a8811c1fa..92c41e9a67bf 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <log.h> +#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -832,6 +833,58 @@ u32 imx_get_fecclk(void) return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); }

+#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS) +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + clrbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_MII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + default: + return -EINVAL; + } + + return 0; +} +#else +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + return 0; +} +#endif + +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) +{ + if (IS_ENABLED(CONFIG_IMX93) && + IS_ENABLED(CONFIG_DWC_ETH_QOS) && + device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) + return imx93_eqos_interface_init(dev, interface_type); + + return -EINVAL; +} + int set_clk_enet(enum enet_freq type) { u32 div; diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index f4297f8fd4d4..c54dc9d05c5c 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -49,27 +49,11 @@ int board_phy_config(struct phy_device *phydev) return 0; }

-static int setup_eqos(void) -{ - struct blk_ctrl_wakeupmix_regs *bctrl = - (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&bctrl->eqos_gpr, - BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, - BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); - - return set_clk_eqos(ENET_125MHZ); -} - int board_init(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec();

- if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) - setup_eqos(); - return 0; }

The correct compatible string for i.MX93 variant of DWC EQoS MAC is now "nxp,imx93-dwmac-eqos".

Signed-off-by: Sébastien Szymanski sebastien.szymanski@armadeus.com ---

Changes for v4: - none

arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 4 ---- 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index a9dffa5a71e9..4ecb53ed8be1 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -131,10 +131,6 @@ phy-reset-post-delay = <100>; };

-&eqos { - compatible = "fsl,imx-eqos"; -}; - &ethphy1 { reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>;