[U-Boot] [PATCH v7 00/11] rockchip: Add new rk3399 boards
This is v7 patchset for New rk3399 boards support wrt previous version[1]
Unfortunately initial version of creating rk3399-u-boot.dtsi and orangepi rk3399 changes are merged, so this is rework on top of u-boot-rockchip/master.
Overall this series add support below rk3399 boards - NanoPI M4 - NanoPC T4 - NanoPI NEO4 - Orangepi RK3399 - Rock PI 4 - Rockpro64
All the respective dts(i) files are synced from Linux 5.1-rc2 and few dts(i) from linux-next.
SoC u-boot specific dtsi rk3399-u-boot.dtsi changes are part of another series [3].
Out of all above boards Rockpor64, Rock-PI and Nanopi NEO4 would support booting via Rockchip miniloader as of now.
For booting the same with SPL NEO4 would require dynamic dram timing detection and rest require LPDDR4 code. There is WIP[2] for these dependencies and this would require big chunk of changes will effect all the rk3399 boards, so I'm planning to mark it for next MW.
Changes for v7: - rebase on top of u-boot-rockchip/master - add SPL_TEXT_BASE on each board defconfig - rebase on required changes Changes for v6: - Include Nanopc T4 support patch - drop rk3399-u-boot.dtsi patch since it is send separately. Changes for v5: - Make all changes related to move sdmmc, spi1 u-boot,dm-pre-reloc properties into all rk3399 dts(i) files. Changes for v4: - don't include existing dts(i) sdmmc, u-boot,dm-pre-reloc into rk3399-u-boot.dtsi Changes for v3: - drop NanoPC T4 for now, since board is yet to receive. - add Rock PI-4 board. - add separate -u-boot.dtsi file for nanopi4 sdram changes. - collect Paul, Philipp and Kever Reviewed-by tags
Travis-CI: https://travis-ci.org/openedev/u-boot-amarula/builds/529284236
[1] https://patchwork.ozlabs.org/cover/1091914/ [2] https://github.com/amarula/u-boot-amarula/tree/rockdev-lpddr4 [3] https://patchwork.ozlabs.org/cover/1091909/
Any inputs? Jagan.
Jagan Teki (11): rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 Kconfig: Add default SPL_FIT_GENERATOR for rockchip arm: rockchip: rk3399: Move common configs in Kconfig rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 rockchip: rk3399: Add Nanopi M4 board support rockchip: rk3399: Add Nanopc T4 board support rockchip: rk3399: Add Nanopi NEO4 board support rockchip: rk3399: Add Rockpro64 board support rockchip: rk3399: Add Rock PI 4 support doc: rockchip: Add global doc for rk3399 build/flash
Kconfig | 1 + arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++ arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopi-m4.dts | 66 ++ arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-nanopi-neo4.dts | 50 ++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 11 + arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++++++++++++++++++ arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-pi-4.dts | 606 +++++++++++++++++ arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 ++++++++++++++++++++ arch/arm/dts/rk3399.dtsi | 5 + arch/arm/mach-rockchip/Kconfig | 16 + board/rockchip/evb_rk3399/MAINTAINERS | 32 + configs/chromebook_bob_defconfig | 17 - configs/evb-rk3399_defconfig | 17 - configs/ficus-rk3399_defconfig | 17 - configs/firefly-rk3399_defconfig | 17 - configs/nanopc-t4-rk3399_defconfig | 59 ++ configs/nanopi-m4-rk3399_defconfig | 59 ++ configs/nanopi-neo4-rk3399_defconfig | 59 ++ configs/orangepi-rk3399_defconfig | 17 - configs/puma-rk3399_defconfig | 16 - configs/rock-pi-4-rk3399_defconfig | 59 ++ configs/rock960-rk3399_defconfig | 17 - configs/rockpro64-rk3399_defconfig | 59 ++ doc/README.rockchip | 233 ++++++- 30 files changed, 2857 insertions(+), 119 deletions(-) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig create mode 100644 configs/nanopi-m4-rk3399_defconfig create mode 100644 configs/nanopi-neo4-rk3399_defconfig create mode 100644 configs/rock-pi-4-rk3399_defconfig create mode 100644 configs/rockpro64-rk3399_defconfig
To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com --- arch/arm/dts/rk3399.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index b53e41b4dc..b73442ee34 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -2495,6 +2495,11 @@ rockchip,pins = <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + }; };
pwm3a {
On 05/08/2019 02:36 AM, Jagan Teki wrote:
To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index b53e41b4dc..b73442ee34 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -2495,6 +2495,11 @@ rockchip,pins = <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; };
pwm2_pin_pull_down: pwm2-pin-pull-down {rockchip,pins =<1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;};};
pwm3a {
Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT.
So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator.
Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/Kconfig b/Kconfig index 7a5491bd67..91c1082ace 100644 --- a/Kconfig +++ b/Kconfig @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce07a7f0ff..bd836acad5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 5bb910e8d4..94963e4280 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 79da86b32f..926d244fbe 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 301b27e3a4..5016fb8993 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index ba13976cc6..22ddd8dce3 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 8d490be18c..48d14ef7d8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT.
So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator.
Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/Kconfig b/Kconfig index 7a5491bd67..91c1082ace 100644 --- a/Kconfig +++ b/Kconfig @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
- default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce07a7f0ff..bd836acad5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 5bb910e8d4..94963e4280 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 79da86b32f..926d244fbe 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 301b27e3a4..5016fb8993 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index ba13976cc6..22ddd8dce3 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 8d490be18c..48d14ef7d8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig.
Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-rockchip/Kconfig | 16 ++++++++++++++++ configs/chromebook_bob_defconfig | 16 ---------------- configs/evb-rk3399_defconfig | 16 ---------------- configs/ficus-rk3399_defconfig | 16 ---------------- configs/firefly-rk3399_defconfig | 16 ---------------- configs/orangepi-rk3399_defconfig | 16 ---------------- configs/puma-rk3399_defconfig | 16 ---------------- configs/rock960-rk3399_defconfig | 16 ---------------- 8 files changed, 16 insertions(+), 112 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 926d244fbe..6a1b279cc9 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -49,17 +39,11 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5016fb8993..61f05b784f 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 22ddd8dce3..3f02c89983 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -47,16 +37,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 964464ac0f..03f0bfdb59 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y @@ -32,8 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -52,12 +48,6 @@ CONFIG_OF_LIVE=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -76,20 +66,14 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 48d14ef7d8..1958b7e190 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -46,16 +36,10 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig.
Moved configs:
- SPL_ATF
- SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- SPL_LOAD_FIT
- SPL_CLK if SPL
- SPL_PINCTRL if SPL
- SPL_RAM if SPL
- SPL_REGMAP if SPL
- SPL_SYSCON if SPL
- CLK
- FIT
- PINCTRL
- RAM
- REGMAP
- SYSCON
- DM_PMIC
- DM_REGULATOR_FIXED
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 16 ++++++++++++++++ configs/chromebook_bob_defconfig | 16 ---------------- configs/evb-rk3399_defconfig | 16 ---------------- configs/ficus-rk3399_defconfig | 16 ---------------- configs/firefly-rk3399_defconfig | 16 ---------------- configs/orangepi-rk3399_defconfig | 16 ---------------- configs/puma-rk3399_defconfig | 16 ---------------- configs/rock960-rk3399_defconfig | 16 ---------------- 8 files changed, 16 insertions(+), 112 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL
- select SPL_ATF
- select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- select SPL_LOAD_FIT
- select SPL_CLK if SPL
- select SPL_PINCTRL if SPL
- select SPL_RAM if SPL
- select SPL_REGMAP if SPL
- select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT
- select CLK
- select FIT
- select PINCTRL
- select RAM
- select REGMAP
- select SYSCON
- select DM_PMIC
- select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 926d244fbe..6a1b279cc9 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -49,17 +39,11 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5016fb8993..61f05b784f 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 22ddd8dce3..3f02c89983 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -47,16 +37,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 964464ac0f..03f0bfdb59 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y @@ -32,8 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -52,12 +48,6 @@ CONFIG_OF_LIVE=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -76,20 +66,14 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 48d14ef7d8..1958b7e190 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -46,16 +36,10 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com --- arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++++++++++++++++++++++++++++++ 1 file changed, 703 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi new file mode 100644 index 0000000000..d325e11728 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vdd_5v>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus_typec"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + + status { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_cam: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_cam"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_touch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vbus_typec>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pcie_phy { + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + status = "okay"; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +};
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Paul Kocialkowski paul.kocialkowski@bootlin.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++++++++++++++++++++++++++++++ 1 file changed, 703 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi new file mode 100644 index 0000000000..d325e11728 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- RK3399-based FriendlyElec boards device tree source
- Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
- Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
- Copyright (c) 2018 Collabora Ltd.
- Copyright (c) 2019 Arm Ltd.
- */
+/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi"
+/ {
- chosen {
stdout-path = "serial2:1500000n8";- };
- clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "clkin_gmac";#clock-cells = <0>;- };
- vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc3v3_sys";- };
- vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-name = "vcc5v0_sys";vin-supply = <&vdd_5v>;- };
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc1v8_s3";vin-supply = <&vcc_1v8>;- };
- vcc3v0_sd: vcc3v0-sd {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&sdmmc0_pwr_h>;regulator-always-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-name = "vcc3v0_sd";vin-supply = <&vcc3v3_sys>;- };
- vbus_typec: vbus-typec {
compatible = "regulator-fixed";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-name = "vbus_typec";- };
- gpio-keys {
compatible = "gpio-keys";autorepeat;pinctrl-names = "default";pinctrl-0 = <&power_key>;power {debounce-interval = <100>;gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;label = "GPIO Key Power";linux,code = <KEY_POWER>;wakeup-source;};- };
- leds: gpio-leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&leds_gpio>;status {gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;label = "status_led";linux,default-trigger = "heartbeat";};- };
- sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";clocks = <&rk808 1>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_reg_on_h>;reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;- };
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&emmc_phy {
- status = "okay";
+};
+&gmac {
- assigned-clock-parents = <&clkin_gmac>;
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- clock_in_out = "input";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy-supply = <&vcc3v3_s3>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
+};
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c7>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
+};
+&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <160>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
- vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";reg = <0x40>;fcs,suspend-voltage-selector = <1>;pinctrl-names = "default";pinctrl-0 = <&cpu_b_sleep>;regulator-always-on;regulator-boot-on;regulator-min-microvolt = <712500>;regulator-max-microvolt = <1500000>;regulator-name = "vdd_cpu_b";regulator-ramp-delay = <1000>;vin-supply = <&vcc3v3_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- vdd_gpu: regulator@41 {
compatible = "silergy,syr828";reg = <0x41>;fcs,suspend-voltage-selector = <1>;pinctrl-names = "default";pinctrl-0 = <&gpu_sleep>;regulator-always-on;regulator-boot-on;regulator-min-microvolt = <712500>;regulator-max-microvolt = <1500000>;regulator-name = "vdd_gpu";regulator-ramp-delay = <1000>;vin-supply = <&vcc3v3_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- rk808: pmic@1b {
compatible = "rockchip,rk808";reg = <0x1b>;clock-output-names = "xin32k", "rtc_clko_wifi";#clock-cells = <1>;interrupt-parent = <&gpio1>;interrupts = <21 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc3v3_sys>;vcc2-supply = <&vcc3v3_sys>;vcc3-supply = <&vcc3v3_sys>;vcc4-supply = <&vcc3v3_sys>;vcc6-supply = <&vcc3v3_sys>;vcc7-supply = <&vcc3v3_sys>;vcc8-supply = <&vcc3v3_sys>;vcc9-supply = <&vcc3v3_sys>;vcc10-supply = <&vcc3v3_sys>;vcc11-supply = <&vcc3v3_sys>;vcc12-supply = <&vcc3v3_sys>;vddio-supply = <&vcc_3v0>;regulators {vdd_center: DCDC_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-name = "vdd_center";regulator-ramp-delay = <6001>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_l: DCDC_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-name = "vdd_cpu_l";regulator-ramp-delay = <6001>;regulator-state-mem {regulator-off-in-suspend;};};vcc_ddr: DCDC_REG3 {regulator-always-on;regulator-boot-on;regulator-name = "vcc_ddr";regulator-state-mem {regulator-on-in-suspend;};};vcc_1v8: DCDC_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc1v8_cam: LDO_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc1v8_cam";regulator-state-mem {regulator-off-in-suspend;};};vcc3v0_touch: LDO_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-name = "vcc3v0_touch";regulator-state-mem {regulator-off-in-suspend;};};vcc1v8_pmupll: LDO_REG3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc1v8_pmupll";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc_sdio: LDO_REG4 {regulator-always-on;regulator-boot-on;regulator-init-microvolt = <3000000>;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc_sdio";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3000000>;};};vcca3v0_codec: LDO_REG5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-name = "vcca3v0_codec";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v5: LDO_REG6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-name = "vcc_1v5";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1500000>;};};vcca1v8_codec: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcca1v8_codec";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v0: LDO_REG8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-name = "vcc_3v0";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3000000>;};};vcc3v3_s3: SWITCH_REG1 {regulator-always-on;regulator-boot-on;regulator-name = "vcc3v3_s3";regulator-state-mem {regulator-off-in-suspend;};};vcc3v3_s0: SWITCH_REG2 {regulator-always-on;regulator-boot-on;regulator-name = "vcc3v3_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
+&i2c1 {
- clock-frequency = <200000>;
- i2c-scl-rising-time-ns = <150>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&i2c4 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <160>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
- fusb0: typec-portc@22 {
compatible = "fcs,fusb302";reg = <0x22>;interrupt-parent = <&gpio1>;interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&fusb0_int>;vbus-supply = <&vbus_typec>;- };
+};
+&i2c7 {
- status = "okay";
+};
+&io_domains {
- bt656-supply = <&vcc_1v8>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
- status = "okay";
+};
+&pcie_phy {
- assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
- assigned-clock-rates = <100000000>;
- assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
- status = "okay";
+};
+&pcie0 {
- ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
- num-lanes = <4>;
- status = "okay";
+};
+&pinctrl {
- fusb30x {
fusb0_int: fusb0-int {rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- gpio-leds {
leds_gpio: leds-gpio {rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
cpu_b_sleep: cpu-b-sleep {rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;};gpu_sleep: gpu-sleep {rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;};pmic_int_l: pmic-int-l {rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- rockchip-key {
power_key: power-key {rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- sdio {
bt_host_wake_l: bt-host-wake-l {rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;};bt_reg_on_h: bt-reg-on-h {/* external pullup to VCC1V8_PMUPLL */rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;};bt_wake_l: bt-wake-l {rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;};wifi_reg_on_h: wifi-reg_on-h {rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- sdmmc {
sdmmc0_det_l: sdmmc0-det-l {rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;};sdmmc0_pwr_h: sdmmc0-pwr-h {rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
+};
+&pwm0 {
- status = "okay";
+};
+&pwm1 {
- status = "okay";
+};
+&pwm2 {
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2_pin_pull_down>;
- status = "okay";
+};
+&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
+};
+&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
+};
+&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
+};
+&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
+};
+&tcphy0 {
- status = "okay";
+};
+&tcphy1 {
- status = "okay";
+};
+&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
+};
+&u2phy0 {
- status = "okay";
+};
+&u2phy0_host {
- status = "okay";
+};
+&u2phy0_otg {
- status = "okay";
+};
+&u2phy1 {
- status = "okay";
+};
+&u2phy1_host {
- status = "okay";
+};
+&u2phy1_otg {
- status = "okay";
+};
+&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
- status = "okay";
- bluetooth {
compatible = "brcm,bcm43438-bt";clocks = <&rk808 1>;clock-names = "lpo";device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;max-speed = <4000000>;pinctrl-names = "default";pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;vbat-supply = <&vcc3v3_sys>;vddio-supply = <&vcc_1v8>;- };
+};
+&uart2 {
- status = "okay";
+};
+&usbdrd3_0 {
- status = "okay";
+};
+&usbdrd3_1 {
- status = "okay";
+};
+&usbdrd_dwc3_0 {
- status = "okay";
+};
+&usbdrd_dwc3_1 {
- dr_mode = "host";
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+};
+&vopb {
- status = "okay";
+};
+&vopb_mmu {
- status = "okay";
+};
+&vopl {
- status = "okay";
+};
+&vopl_mmu {
- status = "okay";
+};
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which is already defined in rk3399.dts so make use of same like other boards.
Add these changes in -u-boot.dtsi to make Linux sync easy for future changes.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi new file mode 100644 index 0000000000..20db99c0b8 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com + */ + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; +};
On 05/08/2019 02:36 AM, Jagan Teki wrote:
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which is already defined in rk3399.dts so make use of same like other boards.
Add these changes in -u-boot.dtsi to make Linux sync easy for future changes.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi new file mode 100644 index 0000000000..20db99c0b8 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
- */
+&sdmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
Add initial support for Nanopi M4 board.
Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - eMMC socket - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI - USB 3.0 x4 - USB Type C power and data - GPIO1, GPIO2 expansion ports - DC5V/3A
Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Refine nanopi4 differences" (sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++++++++++++++++++++++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 + board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-m4-rk3399_defconfig | 59 ++++++++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 configs/nanopi-m4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 35cbbfabd0..2a5bfd3fb5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts b/arch/arm/dts/rk3399-nanopi-m4.dts new file mode 100644 index 0000000000..60358ab8c7 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index 20db99c0b8..05708b6f55 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com */
+#include "rk3399-u-boot.dtsi" + &sdmmc { pinctrl-names = "default"; pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 07ee8ce92c..ae43805a6a 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig
+NANOPI-M4 +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki jagan@amarulasolutions.com S: Maintained diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig new file mode 100644 index 0000000000..c2832788f0 --- /dev/null +++ b/configs/nanopi-m4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
Add initial support for Nanopc T4 board.
Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - 16GB eMMC - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Add NanoPC-T4 IR receiver" (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber dxld@darkboxed.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/nanopc-t4-rk3399_defconfig | 59 +++++++++++++++ 5 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2a5bfd3fb5..adaca524c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts new file mode 100644 index 0000000000..84433cf02b --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPC-T4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "vcc12v0_sys"; + }; + + vcc5v0_host0: vcc5v0-host0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0"; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <18000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; +}; + +&pinctrl { + ir { + ir_rx: ir-rx { + /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host0>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host0>; +}; + +&vcc5v0_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index ae43805a6a..f55c92f80c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig
+NANOPC-T4 +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/nanopc-t4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi + NANOPI-M4 M: Jagan Teki jagan@amarulasolutions.com S: Maintained diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig new file mode 100644 index 0000000000..d9f2137b4c --- /dev/null +++ b/configs/nanopc-t4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Add NanoPC-T4 IR receiver" (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber dxld@darkboxed.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/nanopc-t4-rk3399_defconfig | 59 +++++++++++++++ 5 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2a5bfd3fb5..adaca524c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \
- rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \
diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
- */
+#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts new file mode 100644 index 0000000000..84433cf02b --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- FriendlyElec NanoPC-T4 board device tree source
- Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
- Copyright (c) 2018 Collabora Ltd.
- */
+/dts-v1/; +#include "rk3399-nanopi4.dtsi"
+/ {
- model = "FriendlyElec NanoPC-T4";
- compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
- vcc12v0_sys: vcc12v0-sys {
compatible = "regulator-fixed";regulator-always-on;regulator-boot-on;regulator-max-microvolt = <12000000>;regulator-min-microvolt = <12000000>;regulator-name = "vcc12v0_sys";- };
- vcc5v0_host0: vcc5v0-host0 {
compatible = "regulator-fixed";regulator-always-on;regulator-boot-on;regulator-name = "vcc5v0_host0";vin-supply = <&vcc5v0_sys>;- };
- adc-keys {
compatible = "adc-keys";io-channels = <&saradc 1>;io-channel-names = "buttons";keyup-threshold-microvolt = <1800000>;poll-interval = <100>;recovery {label = "Recovery";linux,code = <KEY_VENDOR>;press-threshold-microvolt = <18000>;};- };
- ir-receiver {
compatible = "gpio-ir-receiver";gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&ir_rx>;- };
+};
+&pinctrl {
- ir {
ir_rx: ir-rx {/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;};- };
+};
+&sdhci {
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
+};
+&u2phy0_host {
- phy-supply = <&vcc5v0_host0>;
+};
+&u2phy1_host {
- phy-supply = <&vcc5v0_host0>;
+};
+&vcc5v0_sys {
- vin-supply = <&vcc12v0_sys>;
+};
+&vcc3v3_sys {
- vin-supply = <&vcc12v0_sys>;
+};
+&vbus_typec {
- enable-active-high;
- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_sys>;
+}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index ae43805a6a..f55c92f80c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig
+NANOPC-T4 +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/nanopc-t4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
NANOPI-M4 M: Jagan Teki jagan@amarulasolutions.com S: Maintained diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig new file mode 100644 index 0000000000..d9f2137b4c --- /dev/null +++ b/configs/nanopc-t4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
Add initial support for Nanopi NEO4 board.
Specification - Rockchip RK3399 - 1GB DDR3-1866 - SD card slot - eMMC Socket - RTL8211E 1Gbps - AP6212 WiFI/BT - HDMI In/Out, DP, MIPI CSI - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 5V/3A
Commit details of rk3399-nanopi-neo4.dts sync from Linux: "arm64: dts: rockchip: Add Nanopi NEO4 initial support" (sha1: 092470b537f19788d957aed12d835a179b606014)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++ arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-neo4-rk3399_defconfig | 59 +++++++++++++++++++++ 5 files changed, 122 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 configs/nanopi-neo4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index adaca524c3..529c506b4d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-gru-bob.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ + rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi new file mode 100644 index 0000000000..7d22528f49 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com + */ + +#include "rk3399-nanopi4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts b/arch/arm/dts/rk3399-nanopi-neo4.dts new file mode 100644 index 0000000000..195410b089 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +/dts-v1/; + +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyARM NanoPi NEO4"; + compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f55c92f80c..1f51f65160 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -18,6 +18,12 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+NANOPI-NEO4 +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/nanopi-neo4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki jagan@amarulasolutions.com S: Maintained diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig new file mode 100644 index 0000000000..188656a2b4 --- /dev/null +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Add initial support for Nanopi NEO4 board.
Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A
Commit details of rk3399-nanopi-neo4.dts sync from Linux: "arm64: dts: rockchip: Add Nanopi NEO4 initial support" (sha1: 092470b537f19788d957aed12d835a179b606014)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++ arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-neo4-rk3399_defconfig | 59 +++++++++++++++++++++ 5 files changed, 122 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 configs/nanopi-neo4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index adaca524c3..529c506b4d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-gru-bob.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \
- rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi new file mode 100644 index 0000000000..7d22528f49 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
- */
+#include "rk3399-nanopi4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts b/arch/arm/dts/rk3399-nanopi-neo4.dts new file mode 100644 index 0000000000..195410b089 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (C) 2019 Amarula Solutions B.V.
- Author: Jagan Teki jagan@amarulasolutions.com
- */
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+/ {
- model = "FriendlyARM NanoPi NEO4";
- compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
- vdd_5v: vdd-5v {
compatible = "regulator-fixed";regulator-name = "vdd_5v";regulator-always-on;regulator-boot-on;- };
- vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";regulator-name = "vcc5v0_core";regulator-always-on;regulator-boot-on;vin-supply = <&vdd_5v>;- };
- vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb1";regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;- };
+};
+&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
+};
+&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
+};
+&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
+}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f55c92f80c..1f51f65160 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -18,6 +18,12 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+NANOPI-NEO4 +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/nanopi-neo4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
ORANGEPI-RK3399 M: Jagan Teki jagan@amarulasolutions.com S: Maintained diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig new file mode 100644 index 0000000000..188656a2b4 --- /dev/null +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
Add initial support for Rockpro64 board.
Specification - Rockchip RK3399 - 2/4GB Dual-Channel LPDDR3 - SD card slot - eMMC socket - 128Mb SPI Flash - Gigabit ethernet - PCIe 4X slot - WiFI/BT module socket - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: rockpro64 dts add usb regulator" (sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar akash@openedev.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 ++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 7 + configs/rockpro64-rk3399_defconfig | 59 ++ 5 files changed, 785 insertions(+) create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 configs/rockpro64-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 529c506b4d..8522f01aca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-rock960.dtb \ + rk3399-rockpro64.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com + */ + +#include "rk3399-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts new file mode 100644 index 0000000000..1f2394e058 --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar Akash_Gajjar@mentor.com + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 RockPro64"; + compatible = "pine64,rockpro64", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 1f51f65160..295730c91b 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -30,3 +30,10 @@ S: Maintained F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi + +ROCKPRO64 +M: Akash Gajjar akash@openedev.com +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/rockpro64-rk3399_defconfig +F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig new file mode 100644 index 0000000000..bde931953a --- /dev/null +++ b/configs/rockpro64-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
On 05/08/2019 02:36 AM, Jagan Teki wrote:
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: rockpro64 dts add usb regulator" (sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar akash@openedev.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 ++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 7 + configs/rockpro64-rk3399_defconfig | 59 ++ 5 files changed, 785 insertions(+) create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 configs/rockpro64-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 529c506b4d..8522f01aca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-rock960.dtb \
- rk3399-rockpro64.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
- */
+#include "rk3399-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts new file mode 100644 index 0000000000..1f2394e058 --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- Copyright (c) 2018 Akash Gajjar Akash_Gajjar@mentor.com
- */
+/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi"
+/ {
- model = "Pine64 RockPro64";
- compatible = "pine64,rockpro64", "rockchip,rk3399";
- chosen {
stdout-path = "serial2:1500000n8";- };
- clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "clkin_gmac";#clock-cells = <0>;- };
- gpio-keys {
compatible = "gpio-keys";autorepeat;pinctrl-names = "default";pinctrl-0 = <&pwrbtn>;power {debounce-interval = <100>;gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;label = "GPIO Key Power";linux,code = <KEY_POWER>;wakeup-source;};- };
- leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;work-led {label = "work";default-state = "on";gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;};diy-led {label = "diy";default-state = "off";gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;};- };
- sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";clocks = <&rk808 1>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_enable_h>;/** On the module itself this is one of these (depending* on the actual card populated):* - SDIO_RESET_L_WL_REG_ON* - PDN (power down when low)*/reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;- };
- vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";regulator-name = "vcc1v8_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;vin-supply = <&vcc_1v8>;- };
- vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pcie_pwr_en>;regulator-name = "vcc3v3_pcie";regulator-always-on;regulator-boot-on;vin-supply = <&vcc12v_dcin>;- };
- vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";regulator-name = "vcc3v3_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc5v0_sys>;- };
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;regulator-name = "vcc5v0_host";regulator-always-on;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_typec_en>;regulator-name = "vcc5v0_typec";regulator-always-on;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vdd_log: vdd-log {
compatible = "pwm-regulator";pwms = <&pwm2 0 25000 1>;regulator-name = "vdd_log";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <800000>;regulator-max-microvolt = <1400000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
+};
+&emmc_phy {
- status = "okay";
+};
+&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
+};
+&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
+};
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
+&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
- rk808: pmic@1b {
compatible = "rockchip,rk808";reg = <0x1b>;interrupt-parent = <&gpio1>;interrupts = <21 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <1>;clock-output-names = "xin32k", "rk808-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc3v3_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc5v0_sys>;vcc12-supply = <&vcc3v3_sys>;vddio-supply = <&vcca_1v8>;regulators {vdd_center: DCDC_REG1 {regulator-name = "vdd_center";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-ramp-delay = <6001>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_l: DCDC_REG2 {regulator-name = "vdd_cpu_l";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-ramp-delay = <6001>;regulator-state-mem {regulator-off-in-suspend;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_1v8: DCDC_REG4 {regulator-name = "vcc_1v8";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc1v8_dvp: LDO_REG1 {regulator-name = "vcc1v8_dvp";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;};};vcc3v0_touch: LDO_REG2 {regulator-name = "vcc3v0_touch";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-state-mem {regulator-off-in-suspend;};};vcca_1v8: LDO_REG3 {regulator-name = "vcca_1v8";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc_sdio: LDO_REG4 {regulator-name = "vcc_sdio";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3000000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3000000>;};};vcca3v0_codec: LDO_REG5 {regulator-name = "vcca3v0_codec";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v5: LDO_REG6 {regulator-name = "vcc_1v5";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1500000>;regulator-max-microvolt = <1500000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1500000>;};};vcca1v8_codec: LDO_REG7 {regulator-name = "vcca1v8_codec";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_3v0: LDO_REG8 {regulator-name = "vcc_3v0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3000000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3000000>;};};vcc3v3_s3: vcc_lan: SWITCH_REG1 {regulator-name = "vcc3v3_s3";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;};};vcc3v3_s0: SWITCH_REG2 {regulator-name = "vcc3v3_s0";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;};};};- };
- vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";reg = <0x40>;fcs,suspend-voltage-selector = <1>;pinctrl-names = "default";pinctrl-0 = <&vsel1_gpio>;regulator-name = "vdd_cpu_b";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <1000>;regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- vdd_gpu: regulator@41 {
compatible = "silergy,syr828";reg = <0x41>;fcs,suspend-voltage-selector = <1>;pinctrl-names = "default";pinctrl-0 = <&vsel2_gpio>;regulator-name = "vdd_gpu";regulator-min-microvolt = <712500>;regulator-max-microvolt = <1500000>;regulator-ramp-delay = <1000>;regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
+};
+&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
+};
+&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
+};
+&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- fusb0: typec-portc@22 {
compatible = "fcs,fusb302";reg = <0x22>;interrupt-parent = <&gpio1>;interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&fusb0_int>;vbus-supply = <&vcc5v0_typec>;status = "okay";- };
+};
+&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
+};
+&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
+};
+&i2s2 {
- status = "okay";
+};
+&io_domains {
- status = "okay";
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
+};
+&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
+};
+&pinctrl {
- buttons {
pwrbtn: pwrbtn {rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- fusb302x {
fusb0_int: fusb0-int {rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- leds {
work_led_gpio: work_led-gpio {rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;};diy_led_gpio: diy_led-gpio {rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pcie {
pcie_pwr_en: pcie-pwr-en {rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
pmic_int_l: pmic-int-l {rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;};vsel1_gpio: vsel1-gpio {rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;};vsel2_gpio: vsel2-gpio {rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;};- };
- sdio-pwrseq {
wifi_enable_h: wifi-enable-h {rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb-typec {
vcc5v0_typec_en: vcc5v0_typec_en {rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- usb2 {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pwm0 {
- status = "okay";
+};
+&pwm2 {
- status = "okay";
+};
+&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
+};
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
+};
+&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
+};
+&tcphy0 {
- status = "okay";
+};
+&tcphy1 {
- status = "okay";
+};
+&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
+};
+&u2phy0 {
- status = "okay";
- u2phy0_otg: otg-port {
status = "okay";- };
- u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;status = "okay";- };
+};
+&u2phy1 {
- status = "okay";
- u2phy1_otg: otg-port {
status = "okay";- };
- u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;status = "okay";- };
+};
+&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
- status = "okay";
+};
+&uart2 {
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+};
+&usbdrd3_0 {
- status = "okay";
+};
+&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
+};
+&usbdrd3_1 {
- status = "okay";
+};
+&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
+};
+&vopb {
- status = "okay";
+};
+&vopb_mmu {
- status = "okay";
+};
+&vopl {
- status = "okay";
+};
+&vopl_mmu {
- status = "okay";
+}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 1f51f65160..295730c91b 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -30,3 +30,10 @@ S: Maintained F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+ROCKPRO64 +M: Akash Gajjar akash@openedev.com +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: configs/rockpro64-rk3399_defconfig +F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig new file mode 100644 index 0000000000..bde931953a --- /dev/null +++ b/configs/rockpro64-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y
participants (2)
-
Jagan Teki -
Kever Yang