[U-Boot] [PATCH v3 2/4] sf: Add dual memories support - DUAL_STACKED - U-Boot

6 Jan 2014

This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com
---
 doc/SPI/README.dual-flash  | 65 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/mtd/spi/sf.c       |  3 +++
 drivers/mtd/spi/sf_ops.c   | 55 ++++++++++++++++++++++++++++++++-------
 drivers/mtd/spi/sf_probe.c |  8 +++++-
 include/spi.h              |  8 ++++++
 include/spi_flash.h        |  8 ++++++
 6 files changed, 137 insertions(+), 10 deletions(-)
 create mode 100644 doc/SPI/README.dual-flash

diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
new file mode 100644
index 0000000..ba0aa26
--- /dev/null
+++ b/doc/SPI/README.dual-flash
@@ -0,0 +1,65 @@
+SPI/QSPI Dual flash connection modes:
+=====================================
+
+This describes how SPI/QSPI flash memories are connected to a given
+controller in a single chip select line.
+
+Current spi_flash framework supports, single flash memory connected
+to a given controller with single chip select line, but there are some
+hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
+connected with a single chip select line from a controller.
+
+"dual_flash" from include/spi.h describes these types of connection mode
+
+Possible connections:
+--------------------
+SF_SINGLE_FLASH:
+       - single spi flash memory connected with single chip select line.
+
+  +------------+             CS         +---------------+
+  |            |----------------------->|               |
+  | Controller |         I0[3:0]        | Flash memory  |
+  | SPI/QSPI   |<======================>| (SPI/QSPI)    |
+  |            |           CLK          |               |
+  |            |----------------------->|               |
+  +------------+                        +---------------+
+
+SF_DUAL_STACKED_FLASH:
+       - dual spi/qspi flash memories are connected with a single chipselect
+         line and these two memories are operating stacked fasion with shared buses.
+       - xilinx zynq qspi controller has implemented this feature [1]
+
+  +------------+        CS             +---------------+
+  |            |---------------------->|               |
+  |            |              I0[3:0]  | Upper Flash   |
+  |            |            +=========>| memory        |
+  |            |            |     CLK  | (SPI/QSPI)    |
+  |            |            |    +---->|               |
+  | Controller |        CS  |    |     +---------------+
+  | SPI/QSPI   |------------|----|---->|               |
+  |            |    I0[3:0] |    |     | Lower Flash   |
+  |            |<===========+====|====>| memory        |
+  |            |          CLK    |     | (SPI/QSPI)    |
+  |            |-----------------+---->|               |
+  +------------+                       +---------------+
+
+       - two memory flash devices should has same hw part attributes (like size,
+         vendor..etc)
+       - Configurations:
+               on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
+               Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
+               Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
+       - Operation:
+               accessing memories serially like one after another.
+               by default, if U_PAGE is unset lower memory should accessible,
+               once user wants to access upper memory need to set U_PAGE.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
+[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM....
+
+--
+Jagannadha Sutradharudu Teki jaganna@xilinx.com
+05-01-2014.
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index d5e175c..c780a81 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,6 +18,9 @@ static int spi_flash_read_write(struct spi_slave *spi,
    unsigned long flags = SPI_XFER_BEGIN;
    int ret;
+	if (spi->flags & SPI_XFER_U_PAGE)
+		flags |= SPI_XFER_U_PAGE;
+
    if (data_len == 0)
    	flags |= SPI_XFER_END;
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index d039cc5..9fab40d 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -131,10 +131,28 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 }
 #endif
+static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
+{
+	switch (flash->dual_flash) {
+	case SF_DUAL_STACKED_FLASH:
+		if (*addr >= (flash->size >> 1)) {
+			*addr -= flash->size >> 1;
+			flash->spi->flags |= SPI_XFER_U_PAGE;
+		} else {
+			flash->spi->flags &= ~SPI_XFER_U_PAGE;
+		}
+		break;
+	default:
+		debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
+		break;
+	}
+}
+
 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 {
    struct spi_slave *spi = flash->spi;
    unsigned long timebase;
+	unsigned long flags = SPI_XFER_BEGIN;
    int ret;
    u8 status;
    u8 check_status = 0x0;
@@ -146,6 +164,9 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
    	check_status = poll_bit;
    }
+	if (spi->flags & SPI_XFER_U_PAGE)
+		flags |= SPI_XFER_U_PAGE;
+
    ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
    if (ret) {
    	debug("SF: fail to read %s status register\n",
@@ -219,7 +240,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 {
-	u32 erase_size;
+	u32 erase_size, erase_addr;
    u8 cmd[SPI_FLASH_CMD_LEN];
    int ret = -1;
@@ -231,15 +252,20 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
cmd[0] = flash->erase_cmd;
    while (len) {
+		erase_addr = offset;
+
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &erase_addr);
+
 #ifdef CONFIG_SPI_FLASH_BAR
-		ret = spi_flash_bank(flash, offset);
+		ret = spi_flash_bank(flash, erase_addr);
    	if (ret < 0)
    		return ret;
 #endif
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(erase_addr, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
-		      cmd[2], cmd[3], offset);
+		      cmd[2], cmd[3], erase_addr);
ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
    	if (ret < 0) {
@@ -258,6 +284,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
    	size_t len, const void *buf)
 {
    unsigned long byte_addr, page_size;
+	u32 write_addr;
    size_t chunk_len, actual;
    u8 cmd[SPI_FLASH_CMD_LEN];
    int ret = -1;
@@ -266,8 +293,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
cmd[0] = flash->write_cmd;
    for (actual = 0; actual < len; actual += chunk_len) {
+		write_addr = offset;
+
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &write_addr);
+
 #ifdef CONFIG_SPI_FLASH_BAR
-		ret = spi_flash_bank(flash, offset);
+		ret = spi_flash_bank(flash, write_addr);
    	if (ret < 0)
    		return ret;
 #endif
@@ -277,7 +309,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
    	if (flash->spi->max_write_size)
    		chunk_len = min(chunk_len, flash->spi->max_write_size);
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(write_addr, cmd);
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
    	      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
@@ -322,7 +354,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
    	size_t len, void *data)
 {
    u8 *cmd;
-	u32 remain_len, read_len;
+	u32 remain_len, read_len, read_addr;
    int bank_sel = 0;
    int ret = -1;
@@ -345,8 +377,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
    cmd[0] = flash->read_cmd;
while (len) {
+		read_addr = offset;
+
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &read_addr);
+
 #ifdef CONFIG_SPI_FLASH_BAR
-		bank_sel = spi_flash_bank(flash, offset);
+		bank_sel = spi_flash_bank(flash, read_addr);
    	if (bank_sel < 0)
    		return ret;
 #endif
@@ -356,7 +393,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
    	else
    		read_len = remain_len;
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(read_addr, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
    						data, read_len);
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index ac42b60..12196c6 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -134,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
    flash->spi = spi;
    flash->name = params->name;
    flash->memory_map = spi->memory_map;
+	flash->dual_flash = flash->spi->option;
/* Assign spi_flash ops */
    flash->write = spi_flash_cmd_write_ops;
@@ -148,6 +149,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
    flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
    flash->sector_size = params->sector_size;
    flash->size = flash->sector_size * params->nr_sectors;
+	if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
+		flash->size <<= 1;
/* Compute erase sector and command */
    if (params->flags & SECT_4K) {
@@ -324,7 +327,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
    puts("\n");
 #endif
 #ifndef CONFIG_SPI_FLASH_BAR
-	if (flash->size > SPI_FLASH_16MB_BOUN) {
+	if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+	     (flash->size > SPI_FLASH_16MB_BOUN)) ||
+	     ((flash->dual_flash != SF_SINGLE_FLASH) &&
+	     (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
    	puts("SF: Warning - Only lower 16MiB accessible,");
    	puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
    }
diff --git a/include/spi.h b/include/spi.h
index c8a9d87..d214d82 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,6 +30,7 @@
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_U_PAGE		(1 << 5)
/* SPI TX operation modes */
 #define SPI_OPM_TX_QPP		1 << 0
@@ -44,6 +45,9 @@
    			SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
    			SPI_OPM_RX_QIOF
+/* SPI bus connection options */
+#define SPI_CONN_DUAL_SHARED	1 << 0
+
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
@@ -62,6 +66,8 @@
  * @max_write_size:	If non-zero, the maximum number of bytes which can
  *			be written at once, excluding command bytes.
  * @memory_map:		Address of read-only SPI flash access.
+ * @option:		Varies SPI bus options - separate bus.
+ * @flags:		Indication of SPI flags.
  */
 struct spi_slave {
    unsigned int bus;
@@ -71,6 +77,8 @@ struct spi_slave {
    unsigned int wordlen;
    unsigned int max_write_size;
    void *memory_map;
+	u8 option;
+	u8 flags;
 };
/**
diff --git a/include/spi_flash.h b/include/spi_flash.h
index f9d640c..fafcf6a 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -33,6 +33,12 @@ enum spi_read_cmds {
 #define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
 #define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
+/* Dual SPI flash memories */
+enum spi_dual_flash {
+	SF_SINGLE_FLASH = 0,
+	SF_DUAL_STACKED_FLASH = 1 << 0,
+};
+
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
@@ -61,6 +67,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
  *
  * @spi:		SPI slave
  * @name:		Name of SPI flash
+ * @dual_flash:		Indicates dual flash memories - dual stacked
  * @size:		Total flash size
  * @page_size:		Write (page) size
  * @sector_size:	Sector size
@@ -85,6 +92,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
 struct spi_flash {
    struct spi_slave *spi;
    const char *name;
+	u8 dual_flash;
u32 size;
    u32 page_size;
-- 
1.8.3



    

[U-Boot] [PATCH v3 2/4] sf: Add dual memories support - DUAL_STACKED

Jagannadha Sutradharudu Teki

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