Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/nx823/* - Remove include/configs/NX823.h - Clean-up ifdef(CONFIG_NX823) - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

arch/powerpc/include/asm/u-boot.h | 3 - board/nx823/Makefile | 8 - board/nx823/flash.c | 449 -------------------------------------- board/nx823/nx823.c | 374 ------------------------------- board/nx823/u-boot.lds | 82 ------- board/nx823/u-boot.lds.debug | 121 ---------- boards.cfg | 1 - doc/README.scrapyard | 5 +- include/asm-generic/u-boot.h | 3 - include/commproc.h | 27 --- include/configs/NX823.h | 344 ----------------------------- 11 files changed, 3 insertions(+), 1414 deletions(-) delete mode 100644 board/nx823/Makefile delete mode 100644 board/nx823/flash.c delete mode 100644 board/nx823/nx823.c delete mode 100644 board/nx823/u-boot.lds delete mode 100644 board/nx823/u-boot.lds.debug delete mode 100644 include/configs/NX823.h

diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 3c28420..f4d4a6b 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -106,9 +106,6 @@ typedef struct bd_info { unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) diff --git a/board/nx823/Makefile b/board/nx823/Makefile deleted file mode 100644 index a22be5c..0000000 --- a/board/nx823/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = nx823.o flash.o diff --git a/board/nx823/flash.c b/board/nx823/flash.c deleted file mode 100644 index fbe17dd..0000000 --- a/board/nx823/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); break; - default: printf ("Unknown Chip Type\n"); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0x00AA00AA; - addr[0x2AAA] = (FPW)0x00550055; - addr[0x5555] = (FPW)0x00900090; - - value = addr[0]; - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0x00B000B0; /* suspend erase */ - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* save sernum if needed */ - if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE) - { - u_long dest = CONFIG_SYS_FLASH_SN_BASE; - u_short *sn = (u_short *)gd->bd->bi_sernum; - - printf("(saving sernum)"); - for (i=0; i<4; i++) - { - if ((rc = write_data(info, dest, sn[i])) != 0) { - return (rc); - } - dest += port_width; - } - } - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<port_width && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i=0; i<port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) - { - putc('.'); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c deleted file mode 100644 index d49fa8c..0000000 --- a/board/nx823/nx823.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <mpc8xx.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { -#if (MPC8XX_SPEED <= 50000000L) - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, - 0xFFFFFFFF, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FE7F434, 0xEFABE834, 0x1FA7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -#else - - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, - 0x1FF7F447, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF7F434, 0xEFEBE834, 0x1FB7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - printf ("Board: Nexus NX823"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Up to 2 Banks of 64Mbit x 2 devices - * Initial builds only have 1 - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br1 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -int misc_init_r (void) -{ - int i; - char tmp[50]; - uchar ethaddr[6]; - bd_t *bd = gd->bd; - ulong *my_sernum = (unsigned long *)&bd->bi_sernum; - - /* load unique serial number */ - for (i = 0; i < 8; ++i) - bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); - - /* save env variables according to sernum */ - sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); - setenv ("serial#", tmp); - - if (!eth_getenv_enetaddr("ethaddr", ethaddr)) { - ethaddr[0] = 0x10; - ethaddr[1] = 0x20; - ethaddr[2] = 0x30; - ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; - ethaddr[4] = bd->bi_sernum[5]; - ethaddr[5] = bd->bi_sernum[6]; - } - - return 0; -} diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds deleted file mode 100644 index 7ae91ff..0000000 --- a/board/nx823/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug deleted file mode 100644 index b0091db..0000000 --- a/board/nx823/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index a2e69d9..7318b7d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1250,4 +1250,3 @@ Orphan powerpc mpc8xx - - fads Orphan powerpc mpc8xx - - genietv GENIETV - - Orphan powerpc mpc8xx - - mbx8xx MBX - - Orphan powerpc mpc8xx - - mbx8xx MBX860T - - -Orphan powerpc mpc8xx - - nx823 NX823 - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0a6c6b5..7f51991 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,9 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -idmr m68k mcf52x2 - 2014-01-28 -M5271EVB m68k mcf52x2 - 2014-01-28 +nx823 powerpc mpc8xx - 2014-04-04 +idmr m68k mcf52x2 ba650e9b 2014-01-28 +M5271EVB m68k mcf52x2 ba650e9b 2014-01-28 dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen michael@schwingen.org actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen michael@schwingen.org actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen michael@schwingen.org diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index e781967..c18e4ca 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -108,9 +108,6 @@ typedef struct bd_info { unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) diff --git a/include/commproc.h b/include/commproc.h index c10a79c..12b9421 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -888,33 +888,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00003E00) #endif /* CONFIG_LWMON */

-/*** NX823 ***********************************************/ - -#if defined(CONFIG_NX823) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NX823 */ - /*** MBX ************************************************************/

#ifdef CONFIG_MBX diff --git a/include/configs/NX823.h b/include/configs/NX823.h deleted file mode 100644 index 6d468df..0000000 --- a/include/configs/NX823.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/*#define CONFIG_VIDEO 1 */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ - "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ - "nfsaddrs=10.77.77.20:10.77.77.250" -#define CONFIG_BOOTCOMMAND "bootm 400e0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ -#define CONFIG_SOURCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_SOURCE - - -/* call various generic functions */ -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define xEMBED -#ifdef EMBED -#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ -#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE -#else -#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ -#endif - -#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ -#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ -#define CONFIG_SYS_FLASH_SN_BYTES 8 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 12-16 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define MPC8XX_SPEED 66666666L -#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) -#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_8_CLK ) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/2 and OR1/2 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* IO and memory mapped stuff */ -#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ -#define NX823_IO_BASE 0xFF000000 /* start of IO */ -#define GPOUT_OFFSET (3<<16) -#define QUART_OFFSET (4<<16) -#define VIDAC_OFFSET (5<<16) -#define CPLD_OFFSET (6<<16) -#define SED1386_OFFSET (7<<16) - -/* - * BR3 and OR3 (general purpose output latches) - */ -#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) -#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) -#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) -#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V) - -/* - * BR4 and OR4 (QUART) - */ -#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) -#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) -#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) -#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) - -/* - * BR5 and OR5 (Video DAC) - */ -#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) -#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) -#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) - -/* - * BR6 and OR6 (CPLD) - * FIXME timing not verified for CPLD - */ -#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) -#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) -#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) - -/* - * BR7 and OR7 (SED1386) - * FIXME timing not verified for SED controller - */ -#define SED1386_BASE 0xF7000000 -#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) -#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ -#define CONFIG_ETHADDR 00:10:20:30:40:50 -#define CONFIG_IPADDR 10.77.77.20 -#define CONFIG_SERVERIP 10.77.77.250 - -#endif /* __CONFIG_H */

Enough time has passed since these boards were moved to Orphan. Remove.

- Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

arch/powerpc/cpu/mpc8xx/cpu_init.c | 16 -- arch/powerpc/cpu/mpc8xx/scc.c | 4 - arch/powerpc/cpu/mpc8xx/serial.c | 4 - arch/powerpc/include/asm/immap_512x.h | 1 - board/mbx8xx/Makefile | 8 - board/mbx8xx/README | 68 ------ board/mbx8xx/csr.h | 44 ---- board/mbx8xx/dimm.h | 98 --------- board/mbx8xx/flash.c | 392 --------------------------------- board/mbx8xx/mbx8xx.c | 383 -------------------------------- board/mbx8xx/pcmcia.c | 156 -------------- board/mbx8xx/u-boot.lds | 82 ------- board/mbx8xx/u-boot.lds.debug | 122 ----------- board/mbx8xx/vpd.c | 180 ---------------- board/mbx8xx/vpd.h | 119 ---------- boards.cfg | 2 - doc/README.scrapyard | 1 + include/common.h | 7 - include/commproc.h | 32 --- include/configs/MBX.h | 290 ------------------------- include/configs/MBX860T.h | 395 ---------------------------------- post/cpu/mpc8xx/ether.c | 4 - post/cpu/mpc8xx/uart.c | 4 - 23 files changed, 1 insertion(+), 2411 deletions(-) delete mode 100644 board/mbx8xx/Makefile delete mode 100644 board/mbx8xx/README delete mode 100644 board/mbx8xx/csr.h delete mode 100644 board/mbx8xx/dimm.h delete mode 100644 board/mbx8xx/flash.c delete mode 100644 board/mbx8xx/mbx8xx.c delete mode 100644 board/mbx8xx/pcmcia.c delete mode 100644 board/mbx8xx/u-boot.lds delete mode 100644 board/mbx8xx/u-boot.lds.debug delete mode 100644 board/mbx8xx/vpd.c delete mode 100644 board/mbx8xx/vpd.h delete mode 100644 include/configs/MBX.h delete mode 100644 include/configs/MBX860T.h

diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 53f873d..69455c7 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr); */ void cpu_init_f (volatile immap_t * immr) { -#ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; # ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif -#endif ulong reg;

/* SYPCR - contains watchdog control (11-9) */ @@ -74,8 +72,6 @@ void cpu_init_f (volatile immap_t * immr)

immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;

-#ifndef CONFIG_MBX /* MBX board does things different */ - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF @@ -203,8 +199,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif

-#endif /* ! CONFIG_MBX */ - /* * Reset CPM */ @@ -213,16 +207,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

-#ifdef CONFIG_MBX - /* - * on the MBX, things are a little bit different: - * - we need to read the VPD to get board information - * - the plprcr is set up dynamically - * - the memory controller is set up dynamically - */ - mbx_init (); -#endif /* CONFIG_MBX */ - #ifdef CONFIG_RPXCLASSIC rpxclassic_init (); #endif diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 2ef77b4..94c9969 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -492,10 +492,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) immr->im_cpm.cp_pbdat &= ~0x00000010; #endif /* QS860T */

-#ifdef CONFIG_MBX - board_ether_init (); -#endif - #if defined(CONFIG_NETVIA) #if defined(PA_ENET_PDN) immr->im_ioport.iop_papar &= ~PA_ENET_PDN; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 4e84049..cb48ed9 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -225,10 +225,6 @@ static int smc_init (void) up->smc_tstate = 0; #endif

-#if defined(CONFIG_MBX) - board_serial_init(); -#endif /* CONFIG_MBX */ - /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. */ diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index bed80aa..6086a73 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -59,7 +59,6 @@ typedef struct sysconf512x { u8 res2[0x28]; law512x_t ddrlaw; /* DDR Local Access Window */ u8 res3[0x18]; - u32 mbxbar; /* MBX Base Address */ u32 srambar; /* SRAM Base Address */ u32 nfcbar; /* NFC Base Address */ u8 res4[0x34]; diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile deleted file mode 100644 index 2074b6b..0000000 --- a/board/mbx8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mbx8xx.o flash.o vpd.o pcmcia.o diff --git a/board/mbx8xx/README b/board/mbx8xx/README deleted file mode 100644 index c889fe9..0000000 --- a/board/mbx8xx/README +++ /dev/null @@ -1,68 +0,0 @@ -IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board - config file!!! - - -WARNING: Wrong settings of this parameter have the potential to -damage hardware by running the MBX's CPU at frequencies that exceed -it's rating and/or overdriving the it's SPLL! - - -Ramblings: -1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. -2) Of these 12 variants, only 2 were entry level boards. -3) I believe that the 2 entry level boards were the only ones that - used OSCM clocking. I can't be completely certain of this at this - point. -4) Motorola never offered an MBX that ran faster than 50Mhz. -5) The 10, non-entry level boards, ran at 40Mhz. -6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. -7) Motorola no longer sells MBXs. - -Based on this information, I can surmise that the default power-on -reset clocking was one of the following three options. - -Multiplier SPLL Options ------------------------------------- -513 OSCM is SPLL input -5 OSCM is SPLL input -1 EXTCLK is SPLL input - -The forth option: - -5 EXTCLK is SPLL input - -is not possible on MBXs. This is because the minimum EXTCLK input -frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran -above 50 Mhz. - -The board I have borrowed definitely uses a multiplier of 1 for -EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. - -One of the two default OSCM modes are most likely what was used on -the entry level boards to cheapen them by eliminating the external -crystal oscillator. - -To add insult to injury, the stupid 860 PLPRCR register retains it's -multiplication factor through hard resets. You can't clear it out -because it is battery backed and once it is set wrong, it stays -wrong. The only way to reset it, so that it takes on it's default -multiplier is to disconnect all power including external, batteries, -as well discharging caps on the board. This precludes the fact that -your 860 may be quite DEAD by this time! - -If you don't setup the multiplication factor for boards that use the -OSCM input, they won't run correctly, but at least they won't be -dead. - -Addtionally, there is no good way to determine the clock input source -from CPU register data. The only way to deal with this is either hard -code it, determine the correct value with some rather NASTY timing -loops, or try to grok it from external data sources. Motorola -firmware opts for the NASTY timing loops, but needs to configure the -serial ports to do so. - - -You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your -MBX8xx board is using the OSCM clocking mode. - -You better know what you are doing here. diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h deleted file mode 100644 index 9370609..0000000 --- a/board/mbx8xx/csr.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __csr_h -#define __csr_h - -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Control and Status Register definitions for the MBX - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* bits for control register #1 / status register #1 */ -#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ -#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ -#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ -#define CSR1_TPEN 0x10 /* TP manually selected */ -#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ -#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ -#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ -#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ - -/* bits for control register #2 */ -#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define CR2_BRDFAIL 0x08 /* Board fail */ -#define CR2_SWS1 0x04 /* Software Status #2 LED */ -#define CR2_SWS2 0x02 /* Software Status #2 LED */ -#define CR2_QSPANRST 0x01 /* Reset QSPAN */ - -/* bits for status register #2 */ -#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ -#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ -#define SR2_RDY 0x02 /* Flash programming status bit */ -#define SR2_FT 0x01 /* Reserved for Factory test purposes */ - -#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) -#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) - -#endif /* __csr_h */ diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h deleted file mode 100644 index b40f112..0000000 --- a/board/mbx8xx/dimm.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef __dimm_h -#define __dimm_h - -/* - * Module name: %M% - * Description: - * Serial Presence Detect Definitions Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * 1. All data was taken from an IBM application note titled - * "Serial Presence Detect Definitions". - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -/* - * serial PD byte assignment address map (256 byte EEPROM) - */ -typedef struct dimm -{ - uchar n_bytes; /* 00 number of bytes written/used */ - uchar t_bytes; /* 01 total number of bytes in serial PD device */ - uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ - uchar n_row; /* 03 number of rows */ - uchar n_col; /* 04 number of columns */ - uchar n_banks; /* 05 number of banks */ - uchar data_w_lo; /* 06 data width */ - uchar data_w_hi; /* 07 data width */ - uchar ifl; /* 08 interface levels */ - uchar a_ras; /* 09 RAS access */ - uchar a_cas; /* 0A CAS access */ - uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ - uchar refresh_rt; /* 0C refresh rate/type */ - uchar p_dram_o; /* 0D primary DRAM organization */ - uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ - uchar reserved[17]; /* 0F reserved fields for future offerings */ - uchar ss_info[32]; /* 20 superset information (may be used in the future) */ - uchar m_info[64]; /* 40 manufacturer information (optional) */ - uchar unused[128]; /* 80 unused storage locations */ -} dimm_t; - -/* - * memory type definitions - */ -#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ -#define DIMM_MT_EDO 2 /* EDO (extended data out) */ -#define DIMM_MT_PN 3 /* pipelined nibble */ -#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ - -/* - * row addresses definitions - */ -#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ -#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ - -/* - * module interface levels definitions - */ -#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ -#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ -#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ -#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ -#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ - -/* - * DIMM configuration type definitions - */ -#define DIMM_CT_NONE 0 /* none */ -#define DIMM_CT_PARITY 1 /* parity */ -#define DIMM_CT_ECC 2 /* ECC */ - -/* - * row addresses definitions - */ -#define DIMM_RRT_SR (1<<7) /* self refresh flag */ -#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ -#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ -#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ -#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ -#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ -#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ -#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ - -#endif /* __dimm_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c deleted file mode 100644 index fa07152..0000000 --- a/board/mbx8xx/flash.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger mgroeger@sysgo.de - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include "vpd.h" - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size, totsize; - int i; - ulong addr; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - totsize = 0; - addr = 0xfc000000; - for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - size = flash_get_size((vu_long *)addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) - break; - totsize += size; - addr += size; - } - - addr = 0xfe000000; - for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - - size = flash_get_size((vu_long *)addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) - break; - totsize += size; - addr += size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - return (totsize); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01010101) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %08lx\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c deleted file mode 100644 index 98c723f..0000000 --- a/board/mbx8xx/mbx8xx.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Board specific routines for the MBX - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <commproc.h> -#include <mpc8xx.h> -#include <net.h> -#include "dimm.h" -#include "vpd.h" -#include "csr.h" - -/* ------------------------------------------------------------------------- */ - -static const uint sdram_table_40[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, - 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -static const uint sdram_table_50[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, - 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, - /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ - 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, - 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, - /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ - 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, - 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq(void); -#endif -static unsigned int board_get_cpufreq(void); - -void mbx_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, plprcr, sccr; - ulong br0_32 = memctl->memc_br0 & 0x400; - - /* real-time clock status and control register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - immr->im_sit.sit_rtcsc = 0x00C3; - - /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ - immr->im_siu_conf.sc_simask = 0x00000000; - immr->im_siu_conf.sc_siel = 0xAAAA0000; - immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; - - /* - * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: - * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) - * 2. RAM Specs (see dimm.h) - * 2. DIMM Specs (see dimm.h) - */ - vpd_init (); - - /* system clock and reset control register */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - sccr = immr->im_clkrst.car_sccr; - sccr &= SCCR_MASK; - sccr |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = sccr; - - speed = board_get_cpufreq (); - -#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) - plprcr = CONFIG_SYS_PLPRCR; -#else - plprcr = immr->im_clkrst.car_plprcr; - plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ - plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */ -#endif - -#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; -#endif - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - immr->im_clkrst.car_plprcr = plprcr; - - /* - * preliminary setup of memory controller: - * - map Flash, otherwise configuration/status - * registers won't be accessible when read - * by board_init_f. - * - map NVRAM and configuation/status registers. - * - map pci registers. - * - DON'T map ram yet, this is done in initdram(). - */ - switch (speed / 1000000) { - case 40: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800930; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - case 50: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800940; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - default: - hang (); - break; - } -#ifdef CONFIG_USE_PCI - memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR; - memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001; - memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR; - memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001; -#endif - /* - * FIXME: I do not understand why I have to call this to - * initialise the control register here before booting from - * the PCMCIA card but if I do not the Linux kernel falls - * over in a big heap. If you can answer this question I - * would like to know about it. - */ - board_ether_init(); -} - -void board_serial_init (void) -{ - MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); -} - -void board_ether_init (void) -{ - MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); - MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; -} - -static unsigned int board_get_cpufreq (void) -{ -#ifndef CONFIG_8xx_GCLK_FREQ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_ICS); - p = (ulong *)packet->data; - return *p; -#else - return((unsigned int)CONFIG_8xx_GCLK_FREQ ); -#endif /* CONFIG_8xx_GCLK_FREQ */ -} - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq (void) -{ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_RCS); - p = (ulong *)packet->data; - return *p; -} -#endif - -static void board_get_enetaddr(uchar *addr) -{ - int i; - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_EA); - for (i = 0; i < 6; i++) - addr[i] = packet->data[i]; -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - vpd_packet_t *packet; - int i; - const char *const fmt = - "\n *** Warning: Low Battery Status - %s Battery ***"; - - puts ("Board: "); - - packet = vpd_find_packet (VPD_PID_PID); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - packet = vpd_find_packet (VPD_PID_MT); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc ('('); - packet = vpd_find_packet (VPD_PID_FAN); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc (')'); - - if (!(MBX_CSR2 & SR2_BATGD)) - printf (fmt, "On-Board"); - if (!(MBX_CSR2 & SR2_NVBATGD)) - printf (fmt, "NVRAM"); - - serial_putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static ulong get_ramsize (dimm_t * dimm) -{ - ulong size = 0; - - if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 - || dimm->fmt == 4) { - size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * - ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); - } - - return size; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long ram_sz = 0; - unsigned long dimm_sz = 0; - dimm_t vpd_dimm, vpd_dram; - unsigned int speed = board_get_cpufreq () / 1000000; - - if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { - dimm_sz = get_ramsize (&vpd_dimm); - } - if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { - ram_sz = get_ramsize (&vpd_dram); - } - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - ulong dimm_bank; - ulong br0_32 = memctl->memc_br0 & 0x400; - - switch (speed) { - case 40: - upmconfig (UPMA, (uint *) sdram_table_40, - sizeof (sdram_table_40) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; - memctl->memc_or7 = 0xff800930; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - case 50: - upmconfig (UPMA, (uint *) sdram_table_50, - sizeof (sdram_table_50) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; - memctl->memc_or7 = 0xff800940; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - default: - hang (); - break; - } - - /* now map ram and dimm, largest one first */ - dimm_bank = dimm_sz / 2; - if (!dimm_sz) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_br2 = 0; - memctl->memc_br3 = 0; - } else if (ram_sz > dimm_bank) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \ - | 0x81; - } else { - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81; - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81; - } - } - - return ram_sz + dimm_sz; -} diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c deleted file mode 100644 index 497e260..0000000 --- a/board/mbx8xx/pcmcia.c +++ /dev/null @@ -1,156 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#include "csr.h" - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -/* A lot of this has been taken from the RPX code in this file it works from me. - I have added the voltage selection for the MBX board. */ - -/* MBX voltage bit in control register #2 */ -#define CR2_VPP12 ((uchar)0x10) -#define CR2_VPPVDD ((uchar)0x20) -#define CR2_VDD5 ((uchar)0x40) -#define CR2_VDD3 ((uchar)0x80) - -#define PCMCIA_BOARD_MSG "MBX860" - -int pcmcia_voltage_set (int slot, int vcc, int vpp) -{ - uchar reg = 0; - - debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); - - switch (vcc) { - case 0: - break; - case 33: - reg |= CR2_VDD3; - break; - case 50: - reg |= CR2_VDD5; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) { - reg |= CR2_VPPVDD; - } else { - return 1; - } - break; - case 120: - reg |= CR2_VPP12; - break; - default: - return 1; - } - - /* first, turn off all power */ - MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); - - /* enable new powersettings */ - MBX_CSR2 |= reg; - debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); - - return (0); -} - -int pcmcia_hardware_enable (int slot) -{ - volatile pcmconf8xx_t *pcmp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", - 'A' + slot); - - udelay (10000); - - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - udelay (500); - - /* remove all power */ - pcmcia_voltage_set (slot, 0, 0); - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, - (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", - (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - pcmcia_voltage_set (_slot_, 50, 0); - printf (" 5.0V card found: "); - } else { - pcmcia_voltage_set (_slot_, 33, 0); - printf (" 3.3V card found: "); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX (_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - - udelay (250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); - } - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable (int slot) -{ - return 0; /* No hardware to disable */ -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds deleted file mode 100644 index 0eb2fba..0000000 --- a/board/mbx8xx/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug deleted file mode 100644 index 7cfed1f..0000000 --- a/board/mbx8xx/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c deleted file mode 100644 index 1ba754e..0000000 --- a/board/mbx8xx/vpd.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Code in faintly related to linux/arch/powerpc/8xx_io: - * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). - * - * This file implements functions to read the MBX's Vital Product Data - * (VPD). I can't use the more general i2c code in mpc8xx/... since I need - * the VPD at a time where there is no RAM available yet. Hence the VPD is - * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#ifdef CONFIG_8xx -#include <commproc.h> -#endif -#include "vpd.h" - -/* Location of receive/transmit buffer descriptors - * Allocate one transmit bd and one receive bd. - * IIC_BD_FREE points to free bd space which we'll use as tx buffer. - */ -#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) -#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) -#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) -#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) - -/* FIXME -- replace 0x2000 with offsetof */ -#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD)) - -/* transmit/receive buffers */ -#define IIC_RX_LENGTH 128 - -#define WITH_MICROCODE_PATCH - -vpd_packet_t * vpd_find_packet(u_char ident) -{ - vpd_packet_t *packet; - vpd_t *vpd = VPD_P; - - packet = (vpd_packet_t *)&vpd->packets; - while ((packet->identifier != ident) && packet->identifier != 0xFF) - { - packet = (vpd_packet_t *)((char *)packet + packet->size + 2); - } - return packet; -} - -void vpd_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - /* - * kludge: when running from flash, no microcode patch can be - * installed. However, the DPMEM usually contains non-zero - * garbage at the relocatable patch base location, so lets clear - * it now. This way the rest of the code can support the microcode - * patch dynamically. - */ - if ((ulong)vpd_init & 0xff000000) - iip->iic_rpbase = 0; - -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - /* Initialize Port B IIC pins */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - i2c->i2c_i2mod = 0x04; /* filter clock */ - i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ - i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ - i2c->i2c_i2cmr = 0x00; /* disable interrupts */ - i2c->i2c_i2cer = 0x1f; /* clear events */ - i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ - - if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) - { - hang(); - } -} - - -/* Read from I2C. - * This is a two step process. First, we send the "dummy" write - * to set the device offset for the read. Second, we perform - * the read operation. - */ -int vpd_read(uint iic_device, uchar *buf, int count, int offset) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; - volatile cbd_t *tbdf1, *tbdf2, *rbdf; - uchar *tb; - uchar event; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; - tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; - rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; - - /* Send a "dummy write" operation. This is a write request with - * only the offset sent, followed by another start condition. - * This will ensure we start reading from the first location - * of the EEPROM. - */ - tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; - tb[0] = iic_device & 0xfe; /* device address */ - tb[1] = offset; /* offset */ - tbdf1->cbd_bufaddr = (uint)tb; - tbdf1->cbd_datlen = 2; - tbdf1->cbd_sc = 0x8400; - - tb += 2; - tb[0] = iic_device | 1; /* device address */ - tbdf2->cbd_bufaddr = (uint)tb; - tbdf2->cbd_datlen = count+1; - tbdf2->cbd_sc = 0xbc00; - - rbdf->cbd_bufaddr = (uint)buf; - rbdf->cbd_datlen = 0; - rbdf->cbd_sc = 0xb000; - - iip->iic_tbase = IIC_BD_TX1; - iip->iic_tbptr = IIC_BD_TX1; - iip->iic_rbase = IIC_BD_RX; - iip->iic_rbptr = IIC_BD_RX; - iip->iic_rfcr = 0x15; - iip->iic_tfcr = 0x15; - iip->iic_mrblr = count; - iip->iic_rstate = 0; - iip->iic_tstate = 0; - - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - i2c->i2c_i2mod |= 1; /* enable iic operation */ - i2c->i2c_i2com |= 0x80; /* start master */ - - /* wait for IIC transfer */ - do { - __asm__ volatile ("eieio"); - event = i2c->i2c_i2cer; - } while (event == 0); - - if ((event & 0x10) || (event & 0x04)) { - count = -1; - goto bailout; - } - -bailout: - i2c->i2c_i2mod &= ~1; /* turn off iic operation */ - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - - return count; -} diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h deleted file mode 100644 index 1d9eb7f..0000000 --- a/board/mbx8xx/vpd.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __vpd_h -#define __vpd_h - -/* - * Module name: %M% - * Description: - * Vital Product Data (VPD) Header Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ - -/* - * packet tuple identifiers - * - * 0x0D - 0xBF reserved - * 0xC0 - 0xFE user defined - */ -#define VPD_PID_GI 0x00 /* guaranteed illegal */ -#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ -#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ -#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ -#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ -#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ -#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ -#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ -#define VPD_PID_EA 0x08 /* ethernet address (binary) */ -#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ -#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ -#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ -#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ -#define VPD_PID_TERM 0xFF /* termination */ - -/* - * VPD structure (format) - */ -#define VPD_EYE_SIZE 8 /* eyecatcher size */ -typedef struct vpd_header -{ - uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ - ushort size; /* size of EEPROM */ -} vpd_header_t; - -#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) -typedef struct vpd -{ - vpd_header_t header; /* header */ - uchar packets[VPD_DATA_SIZE]; /* data */ -} vpd_t; - -/* - * packet tuple structure (format) - */ -typedef struct vpd_packet -{ - uchar identifier; /* identifier (PIDs above) */ - uchar size; /* size of the following data area */ - uchar data[1]; /* data (size is dependent upon PID) */ -} vpd_packet_t; - -/* - * MBX product configuration options bit definitions - * - * Notes: - * 1. The bit numbering is reversed in perspective with the C compiler. - */ -#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ -#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ -#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ -#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ -#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ -#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ -#define PCO_DIMM (1<<6) /* DIMM module socket */ -#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ -#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ -#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ -#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ -#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ -#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ -#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ -#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ - -/* - * FLASH memory configuration packet data - */ -typedef struct vpd_fmc -{ - ushort mid; /* manufacturer's idenitfier */ - ushort did; /* manufacturer's device idenitfier */ - uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ - uchar nod; /* number of devices present */ - uchar noc; /* number of columns */ - uchar cw; /* column width in bits */ - uchar wedw; /* write/erase data width */ -} vpd_fmc_t; - -/* function prototypes */ -extern void vpd_init(void); -extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); -extern vpd_packet_t *vpd_find_packet(u_char ident); - -#endif /* __vpd_h */ diff --git a/boards.cfg b/boards.cfg index 7318b7d..abf678c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1248,5 +1248,3 @@ Orphan powerpc mpc8xx - - fads Orphan powerpc mpc8xx - - fads FADS850SAR - - Orphan powerpc mpc8xx - - fads FADS860T - - Orphan powerpc mpc8xx - - genietv GENIETV - - -Orphan powerpc mpc8xx - - mbx8xx MBX - - -Orphan powerpc mpc8xx - - mbx8xx MBX860T - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 7f51991..4e0ad32 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +mbx8xx powerpc mpc8xx - 2014-04-04 nx823 powerpc mpc8xx - 2014-04-04 idmr m68k mcf52x2 ba650e9b 2014-01-28 M5271EVB m68k mcf52x2 ba650e9b 2014-01-28 diff --git a/include/common.h b/include/common.h index cbd3c9e..580615b 100644 --- a/include/common.h +++ b/include/common.h @@ -511,13 +511,6 @@ void rpxclassic_init (void);

void rpxlite_init (void);

-#ifdef CONFIG_MBX -/* $(BOARD)/mbx8xx.c */ -void mbx_init (void); -void board_serial_init (void); -void board_ether_init (void); -#endif - #ifdef CONFIG_HERMES /* $(BOARD)/hermes.c */ void hermes_start_lxt980 (int speed); diff --git a/include/commproc.h b/include/commproc.h index 12b9421..62468c3 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -12,10 +12,6 @@ * CPM capabilities. I (or someone else) will add definitions as they * are needed. -- Dan * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. */ #ifndef __CPM_8XX__ #define __CPM_8XX__ @@ -135,7 +131,6 @@ typedef struct cpm_buf_desc { #define PROFF_SMC2 ((uint)0x0380)

/* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. */ typedef struct smc_uart { ushort smc_rbase; /* Rx Buffer descriptor base address */ @@ -888,33 +883,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00003E00) #endif /* CONFIG_LWMON */

-/*** MBX ************************************************************/ - -#ifdef CONFIG_MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_MBX */ - /*** KM8XX *********************************************************/

/* The KM8XX Service Module uses SCC3 for Ethernet */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h deleted file mode 100644 index 96edd44..0000000 --- a/include/configs/MBX.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Configuation settings for the MBX8xx board. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Changed 2002-10-01 - * Added PCMCIA defines mostly taken from other U-Boot boards that - * have PCMCIA already working. If you find any bugs, incorrect assumptions - * feel free to fix them yourself and submit a patch. - * Rod Boyce <rod_boyce@stratexnet.com. - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MBX 1 /* ...on an MBX module */ - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -/* Define this to use the PCI bus */ -#undef CONFIG_USE_PCI - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ (50000000UL) -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_NET -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_IDE - - -#define CONFIG_DOS_PARTITION - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map as defined by the MBX PGM - */ -#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ -#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CONFIG_SYS_PCIMEM_OR 0xA0000108 -#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) -#define CONFIG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CONFIG_SYS_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 - -#define CONFIG_PCMCIA_SLOT_A 1 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h deleted file mode 100644 index 74f44df..0000000 --- a/include/configs/MBX860T.h +++ /dev/null @@ -1,395 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T MBX board. - * Copied from the FADS stuff, which was originally copied from the MBX stuff! - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * Rob Taylor coverted it back to MBX - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MBX 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_CPUCLOCK 40 -#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) -#define TARGET_SYSTEM_FREQUENCY 40 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 40000000 /* 50 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_8xx_TFTP_MODE -#else -#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_8xx_TFTP_MODE -#endif - -#define CONFIG_MISC_INIT_R - -#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTARGS " " -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFA00000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) -#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CONFIG_SYS_PCIMEM_OR 0xA0000108 -#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -/*0xFE000000*/ -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_HWINFO_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) -#define CONFIG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CONFIG_SYS_SCCR SCCR_TBS - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 -#define CONFIG_SYS_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13821000 - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_40MHZ 1 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#define CONFIG_CMD_NET -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC1_ENET 1 -#define CONFIG_FEC_ENET 1 -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index 9150547..53c0e4d 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -374,10 +374,6 @@ static void scc_init (int scc_index) *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif

-#ifdef CONFIG_MBX - board_ether_init (); -#endif - /* * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive */ diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index 106a9b8..25d63d8 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -141,10 +141,6 @@ static void smc_init (int smc_index) up->smc_rfcr = SMC_EB; up->smc_tfcr = SMC_EB;

-#if defined(CONFIG_MBX) - board_serial_init (); -#endif - /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. * Set local loopback mode.

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/genietv/* - Remove include/configs/GENIETV.h - Clean-up if defined(CONFIG_GENIETV) - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

board/genietv/Makefile | 8 - board/genietv/flash.c | 449 ----------------------------------------- board/genietv/genietv.c | 360 --------------------------------- board/genietv/u-boot.lds | 101 --------- board/genietv/u-boot.lds.debug | 127 ------------ boards.cfg | 1 - doc/README.console | 1 - doc/README.scrapyard | 1 + doc/README.video | 2 - include/commproc.h | 26 --- include/configs/GENIETV.h | 354 -------------------------------- 11 files changed, 1 insertion(+), 1429 deletions(-) delete mode 100644 board/genietv/Makefile delete mode 100644 board/genietv/flash.c delete mode 100644 board/genietv/genietv.c delete mode 100644 board/genietv/u-boot.lds delete mode 100644 board/genietv/u-boot.lds.debug delete mode 100644 include/configs/GENIETV.h

diff --git a/board/genietv/Makefile b/board/genietv/Makefile deleted file mode 100644 index fd11f14..0000000 --- a/board/genietv/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = genietv.o flash.o diff --git a/board/genietv/flash.c b/board/genietv/flash.c deleted file mode 100644 index 5f57978..0000000 --- a/board/genietv/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - - now = get_timer(start); - - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return 2; - - while (count--) { - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c deleted file mode 100644 index 0a015ea..0000000 --- a/board/genietv/genietv.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * genietv/genietv.c - * - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ - -#include <common.h> -#include <mpc8xx.h> - -#define CONFIG_SYS_PA7 0x0100 - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00, - 0x1FFDDC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity - */ - -int checkboard (void) -{ - puts ("Board: GenieTV\n"); - return 0; -} - -#if 0 -static void PrintState (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - - printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, - memctl->memc_or0); - printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, - memctl->memc_or1); - printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, - memctl->memc_or2); -} -#endif - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - long int size_b0, size_b1, size8; - - /* Enable SDRAM */ - - /* Configuring PA7 for general purpouse output pin */ - im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7; /* 0 = general purpouse */ - im->im_ioport.iop_padir |= CONFIG_SYS_PA7; /* 1 = output */ - - /* Enable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat |= CONFIG_SYS_PA7; /* value of PA7 */ - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - /* perform SDRAM initialization sequence */ - memctl->memc_mar = 0x00000088; - - memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ - - /* Execute refresh 8 times */ - memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; - - memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ - - memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ - - /* Execute refresh 4 times */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - -#if 0 - PrintState (); -#endif -/* printf ("\nChecking bank1..."); */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - size_b0 = size8; - -/* printf ("\nChecking bank2..."); */ - size_b1 = - dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - /* - * Final mapping: map bigger bank first - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + - (size_b0 & BR_BA_MSK); - } else { - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - /* adjust refresh rate depending on SDRAM type, one bank */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - } - - /* If no memory detected, disable SDRAM */ - if ((size_b0 + size_b1) == 0) { - printf ("disabling SDRAM!\n"); - /* Disable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7; /* value of PA7 */ - } -/* else */ -/* printf("done! (%08lx)\n", size_b0 + size_b1); */ - -#if 0 - PrintState (); -#endif - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - long size; - - /*memctl->memc_mbmr = mbmr_value; */ - - size = get_ram_size (base, maxsize); - - if (size) { -/* printf("(%08lx)", size); */ - } else { - printf ("(0)"); - } - - return (size); -} - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init (void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota, slotb; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* Check if any PCMCIA card is luged in. */ - slota = (pcmp->pcmc_pipr & 0x18000000) == 0; - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0; - - if (!(slota || slotb)) { - printf ("No card present\n"); -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - return -1; - } else - printf ("Unknown card ("); - - v = 0; - - switch ((pcmp->pcmc_pipr >> 14) & 3) { - case 0x00: - printf ("5V"); - v = 5; - break; - case 0x01: - printf ("5V and 3V"); - v = 3; - break; - case 0x03: - printf ("5V, 3V and x.xV"); - v = 3; - break; - } - - switch (v) { - case 3: - printf ("; using 3V"); - /* Enable 3 volt Vcc. */ - - break; - - default: - printf ("; unknown voltage"); - return -1; - } - printf (")\n"); - /* disable pcmcia reset after a while */ - - udelay (20); - - pcmp->pcmc_pgcrb = 0; - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay (CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} -#endif diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds deleted file mode 100644 index 70ab702..0000000 --- a/board/genietv/u-boot.lds +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - board/genietv/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - *(.text.do_load_serial*) - *(.text.do_mem_*) - *(.text.do_bootm*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug deleted file mode 100644 index cc8cd3a..0000000 --- a/board/genietv/u-boot.lds.debug +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index abf678c..e4ef38b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1247,4 +1247,3 @@ Orphan powerpc mpc8xx - - fads Orphan powerpc mpc8xx - - fads FADS823 - - Orphan powerpc mpc8xx - - fads FADS850SAR - - Orphan powerpc mpc8xx - - fads FADS860T - - -Orphan powerpc mpc8xx - - genietv GENIETV - - diff --git a/doc/README.console b/doc/README.console index e7970ed..aadf596 100644 --- a/doc/README.console +++ b/doc/README.console @@ -99,4 +99,3 @@ The driver has been tested with the following configurations (see CREDITS for other contact informations):

- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it -- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 4e0ad32..b068544 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +genietv powerpc mpc8xx - 2014-04-04 mbx8xx powerpc mpc8xx - 2014-04-04 nx823 powerpc mpc8xx - 2014-04-04 idmr m68k mcf52x2 ba650e9b 2014-01-28 diff --git a/doc/README.video b/doc/README.video index f09d5f9..dadbfcd 100644 --- a/doc/README.video +++ b/doc/README.video @@ -11,8 +11,6 @@ U-Boot MPC8xx video controller driver The driver has been tested with the following configurations:

- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it -- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it -

"video-mode" environment variable =============================== diff --git a/include/commproc.h b/include/commproc.h index 62468c3..e3bc6d6 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -704,32 +704,6 @@ typedef struct scc_enet { #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ #endif /* CONFIG_GEN860T */

-/*** GENIETV ********************************************************/ - -#if defined(CONFIG_GENIETV) -/* Ethernet is only on SCC2 */ - -#define CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 - -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) - -#endif /* CONFIG_GENIETV */ - /*** HERMES-PRO ******************************************************/

/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h deleted file mode 100644 index 6a34b12..0000000 --- a/include/configs/GENIETV.h +++ /dev/null @@ -1,354 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 30000000 -> 300fffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - Lon (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CONFIG_SYS_ALLOC_DPRAM /* Use dynamic DPRAM allocation */ - -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -/*#define CONFIG_VIDEO 1 / To enable the video initialization */ -/*#define CONFIG_VIDEO_ADDR 0x00200000 */ -/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */ -/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */ - -/*#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 */ -/*#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 */ -/*#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 */ -/*#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 */ - -/* Video related */ - -/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */ -/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */ -/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 0 */ -/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_GENIETV 1 -#define CONFIG_MPC823 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ - -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ -"bootm " -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ - -/* values according to the manual */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - * -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - * - * #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0(FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ - -/* FLASH timing */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX ) - -/*#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) */ -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 0xfff80ff4 */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ - -/* - * BR1/2 and OR1/2 (SDRAM) -*/ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */ -#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MBMR_PTB 0x5d /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \ - | MAMR_TLFA_4X) /* 0x5d802114 */ - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 -#define PCMCIA_SLOT_B 1 - -#endif /* __CONFIG_H */

Enough time has passed since these boards were moved to Orphan. Remove.

- Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h} - Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS), defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD) - Remove the entries from boards.cfg

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

arch/powerpc/cpu/mpc8xx/scc.c | 12 - arch/powerpc/cpu/mpc8xx/serial.c | 2 +- board/fads/fads.c | 65 ------ board/fads/fads.h | 5 - board/fads/lamp.c | 4 - board/fads/pcmcia.c | 13 -- boards.cfg | 4 - include/commproc.h | 88 -------- include/configs/ADS860.h | 60 ----- include/configs/FADS823.h | 472 --------------------------------------- include/configs/FADS850SAR.h | 415 ---------------------------------- include/configs/FADS860T.h | 58 ----- include/pcmcia.h | 2 - 13 files changed, 1 insertion(+), 1199 deletions(-) delete mode 100644 include/configs/ADS860.h delete mode 100644 include/configs/FADS823.h delete mode 100644 include/configs/FADS850SAR.h delete mode 100644 include/configs/FADS860T.h

diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 94c9969..647f058 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,18 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif

-#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - #ifdef CONFIG_RPXCLASSIC *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index cb48ed9..f7ca11e 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -173,7 +173,7 @@ static int smc_init (void) # endif #endif

-#if defined(CONFIG_FADS) || defined(CONFIG_ADS) +#if defined(CONFIG_FADS) /* Enable RS232 */ #if defined(CONFIG_8xx_CONS_SMC1) *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; diff --git a/board/fads/fads.c b/board/fads/fads.c index 89dd9ef..fdb46b1 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -210,11 +210,7 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)

switch (noMbytes) { case 4: /* 4 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS - memctl->memc_mamr = 0xc0a21114; -#else memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ -#endif memctl->memc_or2 = 0xffc00800; /* 4M */ break;

@@ -226,11 +222,7 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay) break;

case 16: /* 16 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */ - memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */ -#else memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ -#endif memctl->memc_or2 = 0xff000800; /* 16M */ break;

@@ -674,42 +666,6 @@ int testdram (void) * Check Board Identity: */

-#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) -static void checkdboard(void) -{ - /* get db type from BCSR 3 */ - uint k = (*((uint *)BCSR3) >> 24) & 0x3f; - - puts (" with db "); - - switch(k) { - case 0x03 : - puts ("MPC823"); - break; - case 0x20 : - puts ("MPC801"); - break; - case 0x21 : - puts ("MPC850"); - break; - case 0x22 : - puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); - break; - case 0x23 : - puts ("MPC860SAR"); - break; - case 0x24 : - case 0x2A : - puts ("MPC860T"); - break; - case 0x3F : - puts ("MPC850SAR"); - break; - default : printf("0x%x", k); - } -} -#endif /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */ - int checkboard (void) { #if defined(CONFIG_MPC86xADS) @@ -732,27 +688,12 @@ int checkboard (void) puts (" rev ");

switch (r) { -#if defined(CONFIG_ADS) - case 0x00: - puts ("ENG - this board sucks, check the errata, not supported\n"); - return -1; - case 0x01: - puts ("PILOT - warning, read errata \n"); - break; - case 0x02: - puts ("A - warning, read errata \n"); - break; - case 0x03: - puts ("B\n"); - break; -#else /* FADS */ case 0x00: puts ("ENG\n"); break; case 0x01: puts ("PILOT\n"); break; -#endif /* CONFIG_ADS */ default: printf ("unknown (0x%x)\n", r); return -1; @@ -865,12 +806,6 @@ int pcmcia_init(void) #endif case 5: printf("; using 5V"); -#ifdef CONFIG_ADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; -#endif #ifdef CONFIG_FADS /* ** Enable 5 volt Vcc. diff --git a/board/fads/fads.h b/board/fads/fads.h index fa49080..1be00b9 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -66,13 +66,8 @@ * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * got FEC so FEC is the default. */ -#ifndef CONFIG_ADS #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ #define CONFIG_FEC_ENET /* Use FEC ethernet */ -#else /* Old ADS has not got FEC option */ -#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* No FEC ethernet */ -#endif /* !CONFIG_ADS */

#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured diff --git a/board/fads/lamp.c b/board/fads/lamp.c index 4e58291..ffcc2b3 100644 --- a/board/fads/lamp.c +++ b/board/fads/lamp.c @@ -1,7 +1,5 @@ #include <config.h>

-#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */ - #include <common.h>

void @@ -43,5 +41,3 @@ fast_blink(unsigned int n) signal_delay(0x00100000); } } - -#endif /* !CONFIG_ADS */ diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c index 99fe0b4..996f032 100644 --- a/board/fads/pcmcia.c +++ b/board/fads/pcmcia.c @@ -14,11 +14,7 @@

#ifdef CONFIG_PCMCIA

-#ifdef CONFIG_ADS -#define PCMCIA_BOARD_MSG "ADS" -#else #define PCMCIA_BOARD_MSG "FADS" -#endif

int pcmcia_voltage_set(int slot, int vcc, int vpp) { @@ -33,9 +29,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)

switch(vcc) { case 0: reg = 0; break; -#ifdef CONFIG_ADS - case 50: reg = BCSR1_PCCVCCON; break; -#endif #ifdef CONFIG_FADS case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; case 50: reg = BCSR1_PCCVCC1; break; @@ -45,9 +38,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)

/* first, turn off all power */

-#ifdef CONFIG_ADS - *((uint *)BCSR1) |= BCSR1_PCCVCCON; -#endif #ifdef CONFIG_FADS *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); #endif @@ -55,9 +45,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)

/* enable new powersettings */

-#ifdef CONFIG_ADS - *((uint *)BCSR1) &= ~reg; -#endif #ifdef CONFIG_FADS *((uint *)BCSR1) |= reg; #endif diff --git a/boards.cfg b/boards.cfg index e4ef38b..e54f8f1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1243,7 +1243,3 @@ Orphan powerpc mpc8260 - - - Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - Orphan powerpc mpc8xx - - - RPXClassic - - Orphan powerpc mpc8xx - - - RPXlite - - -Orphan powerpc mpc8xx - - fads ADS860 - - -Orphan powerpc mpc8xx - - fads FADS823 - - -Orphan powerpc mpc8xx - - fads FADS850SAR - - -Orphan powerpc mpc8xx - - fads FADS860T - - diff --git a/include/commproc.h b/include/commproc.h index e3bc6d6..605aac2 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -429,38 +429,6 @@ typedef struct scc_enet { * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. **********************************************************************/

- -/*** ADS *************************************************************/ - -#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) -/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - -/* 68160 PHY control */ - -#define PC_ENET_ETHLOOP ((ushort)0x0800) -#define PC_ENET_TPFLDL ((ushort)0x0400) -#define PC_ENET_TPSQEL ((ushort)0x0200) - -#endif /* MPC860ADS */ - /*** BSEIP **********************************************************/

#ifdef CONFIG_BSEIP @@ -563,62 +531,6 @@ typedef struct scc_enet {

#endif

-/*** FADS823 ********************************************************/ - -#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. - */ -#ifdef CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 -#endif - -#ifdef CONFIG_SCC1_ENET -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define CPMVEC_ENET CPMVEC_SCC1 -#endif - -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00002000) - -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) - -#endif /* CONFIG_FADS823FADS */ - -/*** FADS850SAR ********************************************************/ - -#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of - * this may be unique to the FADS850SAR configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ -#endif /* CONFIG_FADS850SAR */ - /*** FADS860T********************************************************/

#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h deleted file mode 100644 index 82ea172..0000000 --- a/include/configs/ADS860.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860 ADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ - -/* Processor type */ -#define CONFIG_MPC860 1 - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* Console baudrate */ - -#if 0 -#define CONFIG_SYS_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ -#else -#define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#endif - -#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -/* This is picked up again in fads.h */ -#define FADS_COMMANDS_ALREADY_DEFINED - -#include "../../board/fads/fads.h" - -#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h deleted file mode 100644 index 50de4ea..0000000 --- a/include/configs/FADS823.h +++ /dev/null @@ -1,472 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia io remapping - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot - * ff000000 -> ff00ffff : IMAP internal in the cpu - * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia - * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot - * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot -*/ - -#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 -#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define BCSR_ADDR ((uint) 0xff010000) -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CONFIG_VIDEO 1 /* To enable video controller support */ -#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ - -/* Video related */ - -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ -#define CONFIG_VIDEO_SIZE (2*1024*1024) -/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 1 */ -#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 -#define CONFIG_MPC823FADS 1 -#define CONFIG_FADS 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -/* Set the CPU speed to 50Mhz on the FADS */ - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#else -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ -"bootm" -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC2_ENET 1 -#undef CONFIG_FEC_ENET -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CONFIG_SYS_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h deleted file mode 100644 index d48460b..0000000 --- a/include/configs/FADS850SAR.h +++ /dev/null @@ -1,415 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom - * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC850 1 -#define CONFIG_MPC850SAR 1 -#define CONFIG_FADS 1 - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 50000000 /* 50 MHz in */ -#else -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ -#define CONFIG_BOOTARGS " " - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0x02100000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CONFIG_SYS_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h deleted file mode 100644 index ed7484b..0000000 --- a/include/configs/FADS860T.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* board type */ -#define CONFIG_FADS 1 /* old/new FADS + new ADS */ - -/* processor type */ -#define CONFIG_MPC860T 1 /* 860T */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if 0 /* old FADS */ -# define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#else /* new FADS */ -# define CONFIG_SYS_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ -#endif - -#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "../../board/fads/fads.h" - -#ifdef USE_REAL_FLASH_VALUES -/* - * These values fit our FADS860T ... - * The "default" behaviour with 1Mbyte initial doesn't work for us! - */ -#undef CONFIG_SYS_OR0_PRELIM -#undef CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x02800001 /* Real values for the board */ -#endif - -#define CONFIG_SYS_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index ce8c8ed..1ad3e63 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -24,8 +24,6 @@ /* The RPX series use SLOT_B */ #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) # define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ -# define CONFIG_PCMCIA_SLOT_A #elif defined(CONFIG_FADS) /* The FADS series are a mess */ # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) # define CONFIG_PCMCIA_SLOT_A

Enough time has passed since these boards were moved to Orphan. Remove.

- Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

arch/powerpc/cpu/mpc8xx/cpu_init.c | 5 - arch/powerpc/cpu/mpc8xx/scc.c | 7 - arch/powerpc/cpu/mpc8xx/serial.c | 2 +- board/RPXClassic/Makefile | 8 - board/RPXClassic/README | 19 - board/RPXClassic/RPXClassic.c | 260 ----------- board/RPXClassic/eccx.c | 335 -------------- board/RPXClassic/flash.c | 431 ------------------ board/RPXClassic/u-boot.lds | 82 ---- board/RPXClassic/u-boot.lds.debug | 121 ----- board/RPXlite/Makefile | 8 - board/RPXlite/README | 877 ------------------------------------- board/RPXlite/README.PlanetCore | 163 ------- board/RPXlite/RPXlite.c | 149 ------- board/RPXlite/flash.c | 508 --------------------- board/RPXlite/u-boot.lds | 82 ---- board/RPXlite/u-boot.lds.debug | 121 ----- boards.cfg | 2 - doc/README.scrapyard | 2 + drivers/pcmcia/mpc8xx_pcmcia.c | 2 +- drivers/pcmcia/rpx_pcmcia.c | 4 +- include/common.h | 4 - include/commproc.h | 35 -- include/configs/RPXClassic.h | 483 -------------------- include/configs/RPXlite.h | 395 ----------------- include/pcmcia.h | 2 +- post/cpu/mpc8xx/ether.c | 7 - post/cpu/mpc8xx/uart.c | 2 +- 28 files changed, 8 insertions(+), 4108 deletions(-) delete mode 100644 board/RPXClassic/Makefile delete mode 100644 board/RPXClassic/README delete mode 100644 board/RPXClassic/RPXClassic.c delete mode 100644 board/RPXClassic/eccx.c delete mode 100644 board/RPXClassic/flash.c delete mode 100644 board/RPXClassic/u-boot.lds delete mode 100644 board/RPXClassic/u-boot.lds.debug delete mode 100644 board/RPXlite/Makefile delete mode 100644 board/RPXlite/README delete mode 100644 board/RPXlite/README.PlanetCore delete mode 100644 board/RPXlite/RPXlite.c delete mode 100644 board/RPXlite/flash.c delete mode 100644 board/RPXlite/u-boot.lds delete mode 100644 board/RPXlite/u-boot.lds.debug delete mode 100644 include/configs/RPXClassic.h delete mode 100644 include/configs/RPXlite.h

diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 69455c7..9c3102d 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) @@ -207,10 +206,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

-#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) rpxlite_init (); #endif diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 647f058..5da6973 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,11 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif

-#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - #ifdef CONFIG_RPXLITE *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif @@ -512,8 +507,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ #endif

return 1; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index f7ca11e..9321411 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -182,7 +182,7 @@ static int smc_init (void) #endif #endif /* CONFIG_FADS */

-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +#if defined(CONFIG_RPXLITE) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; #endif /* CONFIG_RPXLITE */ diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile deleted file mode 100644 index 87db754..0000000 --- a/board/RPXClassic/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXClassic.o flash.o eccx.o diff --git a/board/RPXClassic/README b/board/RPXClassic/README deleted file mode 100644 index e03f670..0000000 --- a/board/RPXClassic/README +++ /dev/null @@ -1,19 +0,0 @@ -# Porting U-Boot onto RPXClassic LF_BW31 board -# Written by Pierre AUBERT -# E-Mail p.aubert@staubli.com -# Stäubli Faverges - <www.staubli.com> -# -# Sept. 20 2001 -# -# Cross compile: Montavista Hardhat ported on HP-UX 10.20 -# - -Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 -DRAM : 16 Mb from 0 -NVRAM : 512 kb from 0xfa000000 - - -- environment is stored in NVRAM -- Mac address is read from EEPROM -- ethernet on SCC1 or fast ethernet on FEC are running (depending on the - configuration flag CONFIG_FEC_ENET) diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c deleted file mode 100644 index 15b7232..0000000 --- a/board/RPXClassic/RPXClassic.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <config.h> -#include <mpc8xx.h> -#include <net.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static unsigned char aschex_to_byte (unsigned char *cp); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXClassic\n"); - return (0); -} - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -static void board_get_enetaddr(uchar *enet) -{ - int i; - char buff[256], *cp; - - /* Initialize I2C */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x54, 0, 1, (uchar *)buff, 128); - i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); - - /* Retrieve MAC address in buffer (key EA) */ - for (cp = buff;;) { - if (cp[0] == 'E' && cp[1] == 'A') { - cp += 3; - /* Read MAC address */ - for (i = 0; i < 6; i++, cp += 2) { - enet[i] = aschex_to_byte ((unsigned char *)cp); - } - } - /* Scan to the end of the record */ - while ((*cp != '\n') && (*cp != (char)0xff)) { - cp++; - } - /* If the next character is a \n, 0 or ff, we are done. */ - cp++; - if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) - break; - } - -#ifdef CONFIG_FEC_ENET - /* The MAC address is the same as normal ethernet except the 3rd byte */ - /* (See the E.P. Planet Core Overview manual */ - enet[3] |= 0x80; -#endif - - printf("MAC address = %pM\n", enet); -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -void rpxclassic_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; - -#ifdef CONFIG_FEC_ENET - - /* Validate the fast ethernet tranceiver */ - *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; - *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; - *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; - *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; -#endif - -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} -/*----------------------------------------------------------------------------- - * aschex_to_byte -- - *----------------------------------------------------------------------------- - */ -static unsigned char aschex_to_byte (unsigned char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte += c; - - return (byte); -} diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c deleted file mode 100644 index 766a19e..0000000 --- a/board/RPXClassic/eccx.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Video support for the ECCX daughter board */ - - -#include <common.h> -#include <config.h> - -#ifdef CONFIG_VIDEO_SED13806 -#include <sed13806.h> - - -/* Screen configurations: the initialization of the SD13806 depends on - screen and on display mode. We handle only 8bpp and 16 bpp modes */ - -/* ECCX board is supplied with a NEC NL6448BC20 screen */ -#ifdef CONFIG_NEC_NL6448BC20 -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP - -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x01}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SED13806_16BPP */ -#endif /* CONFIG_NEC_NL6448BC20 */ - - -#ifdef CONFIG_CONSOLE_EXTRA_INFO - -/*----------------------------------------------------------------------------- - * video_get_info_str -- setup a board string: type, speed, etc. - * line_number= location to place info string beside logo - * info= buffer for info string - *----------------------------------------------------------------------------- - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " RPXClassic board"); - } - else { - info [0] = '\0'; - } - -} -#endif - -/*----------------------------------------------------------------------------- - * board_video_init -- init de l'EPSON, config du CS - *----------------------------------------------------------------------------- - */ -unsigned int board_video_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Program ECCX registers */ - *(ECCX_CSR12) |= ECCX_860; - *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; - *(ECCX_CSR8) |= ECCX_ENEPSON; - - memctl->memc_or2 = SED13806_OR; - memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; - - return (SED13806_REG_ADDR); -} - -/*----------------------------------------------------------------------------- - * board_validate_screen -- - *----------------------------------------------------------------------------- - */ -void board_validate_screen (unsigned int base) -{ - /* Activate the panel bias power */ - *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; -} -/*----------------------------------------------------------------------------- - * board_get_regs -- - *----------------------------------------------------------------------------- - */ -const S1D_REGS *board_get_regs (void) -{ - return (init_regs); -} -/*----------------------------------------------------------------------------- - * board_get_width -- - *----------------------------------------------------------------------------- - */ -int board_get_width (void) -{ - return (DISPLAY_WIDTH); -} - -/*----------------------------------------------------------------------------- - * board_get_height -- - *----------------------------------------------------------------------------- - */ -int board_get_height (void) -{ - return (DISPLAY_HEIGHT); -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c deleted file mode 100644 index 97ffa68..0000000 --- a/board/RPXClassic/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * RPXClassic uses Am29DL323B flash memory with 2 banks - * - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ - - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - - /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank 1 */ - addr = (volatile unsigned long *)info->start[23]; - - *addr = 0xF0F0F0F0; /* reset bank 2 */ - - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds deleted file mode 100644 index 0eb2fba..0000000 --- a/board/RPXClassic/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug deleted file mode 100644 index b9c84c7..0000000 --- a/board/RPXClassic/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index c17cbac..0000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite.o flash.o diff --git a/board/RPXlite/README b/board/RPXlite/README deleted file mode 100644 index 3ca6711..0000000 --- a/board/RPXlite/README +++ /dev/null @@ -1,877 +0,0 @@ -# Porting U-Boot onto RPXlite board -# Written by Yoo. Jonghoon -# E-Mail : yooth@ipone.co.kr -# IP ONE Inc. - -# Since 2001. 1. 29 - -# Shell : bash -# Cross-compile tools : Montavista Hardhat -# Debugging tools : Windriver VisionProbe (PowerPC BDM) -# ppcboot ver. : ppcboot-0.8.1 - -############################################################### -# 1. Hardware setting -############################################################### - -1.1. Board, BDM settings - Install board, BDM, connect each other - -1.2. Save Register value - Boot with board-on monitor program and save the - register values with BDM. - -1.3. Configure flash programmer - Check flash memory area in the memory map. - 0xFFC00000 - 0xFFFFFFFF - - Boot monitor program is at - 0xFFF00000 - - You can program on-board flash memory with VisionClick - flash programmer. Set the target flash device as: - - 29DL800B - - (?) The flash memory device in the board *is* 29LV800B, - but I cannot program it with '29LV800B' option. - (in VisionClick flash programming tools) - I don't know why... - -1.4. Save boot monitor program *IMPORTANT* - Upload boot monitor program from board to file. - boot monitor program starts at 0xFFF00000 - -1.5. Test flash memory programming - Try to erase boot program in the flash memory, - and re-write them. - *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE - BEFORE ERASING FLASH - -############################################################### -# 2. U-Boot setting -############################################################### - -2.1. Download U-Boot tarball at - ftp://ftp.denx.de - (The latest version is ppcboot-0.8.1.tar.bz2) - - To extract the archive use the following syntax : - > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - - -2.2. Add the following lines in '.profile' - export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin - -2.3. Make board specific config, for example: - > cd ppcboot-0.8.1 - > make TQM860L_config - - Now we can build ppcboot bin files. - After make all, you must see these files in your - ppcboot root directory. - - ppcboot - ppcboot.bin - ppcboot.srec - ppcboot.map - -2.4. Make your own board directory into the - ppcboot-0.8.1/board - and make your board-specific files here. - - For exmanple, tqm8xx files are composed of - .depend : Nothing - Makefile : To make config file - config.mk : Sets base address - flash.c : Flash memory control files - ppcboot.lds : linker(ld) script? (I don't know this yet) - tqm8xx.c : DRAM control and board check routines - - And, add your board config lines in the - ppcboot-0.8.1/Makefile - - Finally, add config_(your board).h file in the - ppcboot-0.8.1/include/ - - I've made board/rpxlite directory, and just copied - tqm8xx settings for now. - - Rebuild ppcboot for rpxlite board: - > make rpxlite_config - > make - -############################################################### -# 3. U-Boot porting -############################################################### - -3.1. My RPXlite files are based on tqm8xx board files. - > cd board - > cp -r tqm8xx RPXLITE - > cd RPXLITE - > mv tqm8xx.c RPXLITE.c - > cd ../../include - > cp config_tqm8xx.h config_RPXLITE.h - -3.2. Modified files are: - board/RPXLITE/RPXLITE.c /* DRAM-related routines */ - board/RPXLITE/flash.c /* flash-related routines */ - board/RPXLITE/config.mk /* set text base address */ - arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ - include/config_RPXLITE.h /* board specific registers */ - - See 'reg_config.txt' for register values in detail. - -############################################################### -# 4. Running Linux -############################################################### - - -############################################################### -# Misc Information -############################################################### - -mem_config.txt: -=============== - -Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device -manufacturer id : 01 (AMD) -device id : 5B (AM29LV800B) -size : 4Mbyte -sector # : 19 - -Sector information : - -number start addr. size -00 FFC0_0000 64 -01 FFC1_0000 32 -02 FFC1_8000 32 -03 FFC2_0000 128 -04 FFC4_0000 256 -05 FFC8_0000 256 -06 FFCC_0000 256 -07 FFD0_0000 256 -08 FFD4_0000 256 -09 FFD8_0000 256 -10 FFDC_0000 256 -11 FFE0_0000 256 -12 FFE4_0000 256 -13 FFE8_0000 256 -14 FFEC_0000 256 -15 FFF0_0000 256 -16 FFF4_0000 256 -17 FFF8_0000 256 -18 FFFC_0000 256 - - -reg_config.txt: -=============== - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* SIU (System Interface Unit) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - - -/*### IMMR */ -/*### Internal Memory Map Register */ -/*### Chap. 11.4.1 */ - - ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ - PARTNUM = 0x21 - MASKNUM = 0x00 - - => 0xFA20 2100 - ---------------------------------------------------------------------- - -/*### SIUMCR */ -/*### SIU Module Configuration Register */ -/*### Chap. 11.4.2 */ -/*### Offset : 0x0000 0000 */ - - EARB = 0 - EARP = 0 - DSHW = 0 - DBGC = 0 - DBPC = 0 - FRC = 0 - DLK = 0 - OPAR = 0 - PNCS = 0 - DPC = 0 - MPRE = 0 - MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ - AEME = 0 - SEME = 0 - BSC = 0 - GB5E = 0 - B2DD = 0 - B3DD = 0 - - => 0x0000 0800 - ---------------------------------------------------------------------- - -/*### SYPCR */ -/*### System Protection Control Register */ -/*### Chap. 11.4.3 */ -/*### Offset : 0x0000 0004 */ - - SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ - BMT = 0x06 /* BUS monitoring timing */ - BME = 1 /* BUS monitor enable */ - SWF = 1 - SWE = 0 /* SW watchdog disable */ - SWRI = 0 - SWP = 1 - - => 0xFFFF 0689 - ---------------------------------------------------------------------- - -/*### TESR */ -/*### Transfer Error Status Register */ -/*### Chap. 11.4.4 */ -/*### Offset : 0x0000 0020 */ - - IEXT = 0 - ITMT = 0 - IPB = 0000 - DEXT = 0 - DTMT = 0 - DPB = 0000 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIPEND */ -/*### SIU Interrupt Pending Register */ -/*### Chap. 11.5.4.1 */ -/*### Offset : 0x0000 0010 */ - - IRQ0~IRQ7 = 0 - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIMASK */ -/*### SIU Interrupt Mask Register */ -/*### Chap. 11.5.4.2 */ -/*### Offset : 0x0000 0014 */ - - IRM0~IRM7 = 0 /* Mask all interrupts */ - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIEL */ -/*### SIU Interrupt Edge/Level Register */ -/*### Chap. 11.5.4.3 */ -/*### Offset : 0x0000 0018 */ - - ED0~ED7 = 0 /* Low level triggered */ - WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIVEC */ -/*### SIU Interrupt Vector Register */ -/*### Chap. 11.5.4.4 */ -/*### Offset : 0x0000 001C */ - - INTC = 3C /* The lowest interrupt is pending..(?) */ - - => 0x3C00 0000 - ---------------------------------------------------------------------- - -/*### SWSR */ -/*### Software Service Register */ -/*### Chap. 11.7.1 */ -/*### Offset : 0x0000 001E */ - - SEQ = 0 - - => 0x0000 - ---------------------------------------------------------------------- - -/*### SDCR */ -/*### SDMA Configuration Register */ -/*### Chap. 20.2.1 */ -/*### Offset : 0x0000 0032 */ - - FRZ = 0 - RAID = 01 /* Priority level 5 (BR5) (normal operation) */ - - => 0x0000 0001 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMA (User Programmable Machine A) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - -/*### Chap. 16.6.4.1 */ -/*### Offset = 0x0000 017c */ - - T0 = CFFF CC24 /* Single Read */ - T1 = 0FFF CC04 - T2 = 0CAF CC04 - T3 = 03AF CC08 - T4 = 3FBF CC27 /* last */ - T5 = FFFF CC25 - T6 = FFFF CC25 - T7 = FFFF CC25 - T8 = CFFF CC24 /* Burst Read */ - T9 = 0FFF CC04 - T10 = 0CAF CC84 - T11 = 03AF CC88 - T12 = 3FBF CC27 /* last */ - T13 = FFFF CC25 - T14 = FFFF CC25 - T15 = FFFF CC25 - T16 = FFFF CC25 - T17 = FFFF CC25 - T18 = FFFF CC25 - T19 = FFFF CC25 - T20 = FFFF CC25 - T21 = FFFF CC25 - T22 = FFFF CC25 - T23 = FFFF CC25 - T24 = CFFF CC24 /* Single Write */ - T25 = 0FFF CC04 - T26 = 0CFF CC04 - T27 = 03FF CC00 - T28 = 3FFF CC27 /* last */ - T29 = FFFF CC25 - T30 = FFFF CC25 - T31 = FFFF CC25 - T32 = CFFF CC24 /* Burst Write */ - T33 = 0FFF CC04 - T34 = 0CFF CC80 - T35 = 03FF CC8C - T36 = 0CFF CC00 - T37 = 33FF CC27 /* last */ - T38 = FFFF CC25 - T39 = FFFF CC25 - T40 = FFFF CC25 - T41 = FFFF CC25 - T42 = FFFF CC25 - T43 = FFFF CC25 - T44 = FFFF CC25 - T45 = FFFF CC25 - T46 = FFFF CC25 - T47 = FFFF CC25 - T48 = C0FF CC24 /* Refresh */ - T49 = 03FF CC24 - T50 = 0FFF CC24 - T51 = 0FFF CC24 - T52 = 3FFF CC27 /* last */ - T53 = FFFF CC25 - T54 = FFFF CC25 - T55 = FFFF CC25 - T56 = FFFF CC25 - T57 = FFFF CC25 - T58 = FFFF CC25 - T59 = FFFF CC25 - T60 = FFFF CC25 /* Exception */ - T61 = FFFF CC25 - T62 = FFFF CC25 - T63 = FFFF CC25 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMB */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### Chap. 16.6.4.1 */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* MEMC */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### BR0 & OR0 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ -/*### Flash memory */ - - BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFE00 0001 - - AM = 1111 1110 0000 0000 0 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 0 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0100 /* cycle length = 4 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0140 - -/*### BR1 & OR1 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ -/*### SDRAM */ - - BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 1 /* UPMA */ - V = 1 /* Valid */ - - => 0x0000 0081 - - AM = 1111 1110 0000 0000 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 11 - BIH = 0 - SCY = 0000 /* cycle length = 0 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0E00 - -/*### BR2 & OR2 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ - - BR2 & OR2 = 0x0000 0000 /* Not used */ - -/*### BR3 & OR3 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ -/*### BCSR */ - - BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA40 0001 - - AM = 1111 1111 0111 1111 1 /* (?) */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0001 /* cycle length = 1 */ - SETA = 0 - TRLX = 0 - - => 0xFF7F 8910 - -/*### BR4 & OR4 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ -/*### NVRAM & SRAM */ - - BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ - AT = 000 - PS = 01 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA00 0401 - - AM = 1111 1111 1111 1000 0 /* 8MByte */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0111 /* cycle length = 7 */ - SETA = 0 - TRLX = 0 - - => 0xFFF8 0970 - -/*### BR5 & OR5 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ - - BR5 & OR5 = 0x0000 0000 /* Not used */ - -/*### BR6 & OR6 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ - - BR6 & OR6 = 0x0000 0000 /* Not used */ - -/*### BR7 & OR7 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ - - BR7 & OR7 = 0x0000 0000 /* Not used */ - -/*### MAR */ -/*### Memory Address Register */ -/*### Chap. 16.4.7 */ -/*### Offset : 0x0000 0164 */ - - MA = External memory address - -/*### MCR */ -/*### Memory Command Register */ -/*### Chap. 16.4.5 */ -/*### Offset : 0x0000 0168 */ - - OP = xx /* Command op code */ - UM = 1 /* Select UPMA */ - MB = 001 /* Select CS1 */ - MCLF = xxxx /* Loop times */ - MAD = xx xxxx /* Memory array index */ - -/*### MAMR */ -/*### Machine A Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0170 */ - - PTA = 0101 1000 - PTAE = 1 /* Periodic timer A enabled */ - AMA = 010 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0100 - WLFA = 0011 - TLFA = 0000 - - => 0x58A0 1430 - -/*### MBMR */ -/*### Machine B Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0174 */ - - PTA = 0100 1110 - PTAE = 0 /* Periodic timer B disabled */ - AMA = 000 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0000 - WLFA = 0000 - TLFA = 0000 - - => 0x4E00 1000 - -/*### MSTAT */ -/*### Memory Status Register */ -/*### Chap. 16.4.3 */ -/*### Offset : 0x0000 0178 */ - - PER0~PER7 = Parity error - WPER = Write protection error - - => 0x0000 - -/*### MPTPR */ -/*### Memory Periodic Timer Prescaler Register */ -/*### Chap. 16.4.8 */ -/*### Offset : 0x0000 017A */ - - PTP = 0000 1000 /* Divide by 8 */ - - => 0x0800 - -/*### MDR */ -/*### Memory Data Register */ -/*### Chap. 16.4.6 */ -/*### Offset : 0x0000 017C */ - - MD = Memory data contains the RAM array word - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* TIMERS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### TBREFx */ -/*### Timebase Reference Registers */ -/*### Chap. 11.9.2 */ -/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ -/*### (Locked) */ - - TBREFF0 = 0xFFFF FFFF - TBREFF1 = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### TBSCR */ -/*### Timebase Status and Control Registers */ -/*### Chap. 11.9.3 */ -/*### Offset : 0x0000 0200 */ -/*### (Locked) */ - - TBIRQ = 00000000 - REF0 = 0 - REF1 = 0 - REFE0 = 0 /* Reference interrupt disable */ - REFE1 = 0 - TBF = 1 - TBE = 1 /* Timebase enable */ - - => 0x0003 - ---------------------------------------------------------------------- - -/*### RTCSC */ -/*### Real-Time Clock Status and Control Registers */ -/*### Chap. 11.10.1 */ -/*### Offset : 0x0000 0220 */ -/*### (Locked) */ - - RTCIRQ = 00000000 - SEC = 1 - ALR = 0 - 38K = 0 /* PITRTCLK is driven by 32.768KHz */ - SIE = 0 - ALE = 0 - RTF = 0 - RTE = 1 /* Real-Time clock enabled */ - - => 0x0081 - ---------------------------------------------------------------------- - -/*### RTC */ -/*### Real-Time Clock Registers */ -/*### Chap. 11.10.2 */ -/*### Offset : 0x0000 0224 */ -/*### (Locked) */ - - RTC = Real time clock measured in second - ---------------------------------------------------------------------- - -/*### RTCAL */ -/*### Real-Time Clock Alarm Registers */ -/*### Chap. 11.10.3 */ -/*### Offset : 0x0000 022C */ -/*### (Locked) */ - - ALARM = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### RTSEC */ -/*### Real-Time Clock Alarm Second Registers */ -/*### Chap. 11.10.4 */ -/*### Offset : 0x0000 0228 */ -/*### (Locked) */ - - COUNTER = Counter bits(fraction of a second) - ---------------------------------------------------------------------- - -/*### PISCR */ -/*### Periodic Interrupt Status and Control Register */ -/*### Chap. 11.11.1 */ -/*### Offset : 0x0000 0240 */ -/*### (Locked) */ - - PIRQ = 0 - PS = 0 /* Write 1 to clear */ - PIE = 0 - PITF = 1 - PTE = 0 /* PIT disabled */ - ---------------------------------------------------------------------- - -/*### PITC */ -/*### PIT Count Register */ -/*### Chap. 11.11.2 */ -/*### Offset : 0x0000 0244 */ -/*### (Locked) */ - - PITC = PIT count - ---------------------------------------------------------------------- - -/*### PITR */ -/*### PIT Register */ -/*### Chap. 11.11.3 */ -/*### Offset : 0x0000 0248 */ -/*### (Locked) */ - - PIT = PIT count /* Read only */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* CLOCKS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - - ---------------------------------------------------------------------- - -/*### SCCR */ -/*### System Clock and Reset Control Register */ -/*### Chap. 15.6.1 */ -/*### Offset : 0x0000 0280 */ -/*### (Locked) */ - - COM = 11 /* Clock output disabled */ - TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ - RTDIV = 0 /* The clock is divided by 4 */ - RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ - CRQEN = 0 - PRQEN = 0 - EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ - DFSYNC = 00 /* Divided by 1 (normal operation) */ - DFBRG = 00 /* Divided by 1 (normal operation) */ - DFNL = 000 - DFNH = 000 - - => 0x6200 0000 - ---------------------------------------------------------------------- - -/*### PLPRCR */ -/*### PLL, Low-Power, and Reset Control Register */ -/*### Chap. 15.6.2 */ -/*### Offset : 0x0000 0284 */ -/*### (Locked) */ - - MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ - SPLSS = 0 - TEXPS = 0 - TMIST = 0 - CSRC = 0 /* The general system clock is generated by the DFNH field */ - LPM = 00 /* Normal high/normal low mode */ - CSR = 0 - LOLRE = 0 - FIOPD = 0 - - => 0x0050 0000 - ---------------------------------------------------------------------- - -/*### RSR */ -/*### Reset Status Register */ -/*### Chap. 12.2 */ -/*### Offset : 0x0000 0288 */ -/*### (Locked) */ - - EHRS = External hard reset - ESRS = External soft reset - LLRS = Loss-of-lock reset - SWRS = Software watchdog reset - CSRS = Check stop reset - DBHRS = Debug port hard reset - DBSRS = Debug port soft reset - JTRS = JTAG reset - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* DMA */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### SDSR */ -/*### SDMA Status Register */ -/*### Chap. 20.2.2 */ -/*### Offset : 0x0000 0908 */ - - SBER = 0 /* SDMA channel bus error */ - DSP2 = 0 /* DSP chain2 (Tx) interrupt */ - DSP1 = 0 /* DSP chain1 (Rx) interrupt */ - - => 0x00 - -/*### SDMR */ -/*### SDMA Mask Register */ -/*### Chap. 20.2.3 */ -/*### Offset : 0x0000 090C */ - - SBER = 0 - DSP2 = 0 - DSP1 = 0 /* All interrupts are masked */ - - => 0x00 - -/*### SDAR */ -/*### SDMA Address Register */ -/*### Chap. 20.2.4 */ -/*### Offset : 0x0000 0904 */ - - AR = 0xxxxx xxxx /* current system address */ - - => 0xFA20 23AC - -/*### IDSRx */ -/*### IDMA Status Register */ -/*### Chap. 20.3.3.2 */ -/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ - - AD = 0 - DONE = 0 - OB = 0 - - => 0x00 - -/*### IDMRx */ -/*### IDMA Mask Register */ -/*### Chap. 20.3.3.3 */ -/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ - - AD = 0 - DONE = 0 - OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore deleted file mode 100644 index b73c5f5..0000000 --- a/board/RPXlite/README.PlanetCore +++ /dev/null @@ -1,163 +0,0 @@ -After several heart-struck failure, I got one workable way to program -each other in FLASH between PlanetCore and U-Boot. - -Hardware Platform : RPXlite DW(EP 823 H1 DW) - -1. From U-Boot to PlanetCore - -Utilities : PlanetCore Boot Loader - PCL200.mot - -[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot -PCL200.mot pcl200.bin - -[Target Operation] -u-boot>t 100000 pcl200.bin -u-boot>go 0x100000 -## Starting application at 0x00100000 ... - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - - -Program MPC8xx PlanetCore Boot Loader v2.00 -Built Sep 19, 2001 at 14:34:42 -Image located from FC000000 to FC01B5D1. -(Skipping an image, only loading low boot image) - -Low boot board detected, skipping high boot image. -Erasing, programming and verifying will start in 20 -seconds -Press P to start immediately or ESC to cancel -Press Space or Enter for more options. -.............. - -Erasing -Programming -FLASH programmed successfully! -Press R to induce a hard reset - -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK -> - -2. From PlanetCore to U-Boot - -Utilities : PlanetCore FLASH Burner - PCB200.mot - -Use Flash Burner to finish the work: - -First, TFTP the U-Boot image file to RAM; For example, -RPXlite_DW.bin to 0x400000 -Second, TFTP FLASH Burner to RAM; For example, -0x100000 -Third, run the FLASH Burner and Program the U-Boot -image into the correct location in FLASH. - -[Target Operation] -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <PCL200.mot> : RPXlite_DW.bin -Enter (B)inary or (S)record input mode <S> : B -Enter address offset : <00400000 hex> : - -Total bytes = 120096 in 232184 uSecs -Loaded addresses 00400000 through 0041D51F. -Start address = 00400000 ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <RPXlite_DW.bin> : PCB200.mot -Enter (B)inary or (S)record input mode <B> : S -Enter address offset : <00000000 hex> : -.512.1024..2048....4096..... -Total bytes = 326280 in 2570249 uSecs -Loaded addresses 00100000 through 0011BB51. -Start address = 00100000 ->go -[Go 00100000] - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - -Bad start address -Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = -0xFFFFFFFF -Forcing Menu Interface - -h[elp] Show commands. -c[ode] Show information on code to be loaded. -di[splay] Display all flash sections. -du[mp] Dump memory. d ? for more info. -e[rase] Erase flash sections. -f[ill] Fill flash sections. -im[age] Toggle load high, low, or both flash -images. -in[fo] Show flash information. -ma[p] Show memory map. -mo[dify] Modify memory. m ? for more info. -p[rogram] Erase, program, and verify now. -reset Restart the loader. -s[how] Show flash sections to erase and program. -t[est] Test flash sections. -q[uit] Quit without programming. -#program 400000 ff000000 1D51F -doProgram( 400000 ff000000 1D51F ) - -Start = 0x00400000, target = 0xFF000000, length = -0x0001D51F -Erasing sector 0xFF000000, length 0x008000. -Erasing sector 0xFF008000, length 0x008000. -Erasing sector 0xFF010000, length 0x008000. -Erasing sector 0xFF018000, length 0x008000. -Programming FF000000 through FF01D51E -FLASH programmed successfully! -Press R to induce a hard reset - -Forcing Hard Reset by MachineCheck and -ResetOnCheckstop... - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB -D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -------------------------------------------------- - -Well, sometimes network function of PlanetCore couldn't work when -switching from U-Boot to PlanetCore. For example, you couldn't -download a file from HOST PC via TFTP. Don't worry, just restart your -HOST PC and everything would work as smooth as clockwork. I don't -know the reason WHY:-) - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Merry Christmas and Happy New Year! - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -===== -Best regards, - -Sam diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index 08575a4..0000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 21b11d4..0000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ -/* - size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } -*/ - /* Remap FLASH according to real size */ -/*%%% - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 0eb2fba..0000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index b9c84c7..0000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index e54f8f1..e0bf130 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1241,5 +1241,3 @@ Orphan powerpc 74xx_7xx - - evb64260 Orphan powerpc mpc824x - - mousse MOUSSE - - Orphan powerpc mpc8260 - - - rsdproto - - Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - -Orphan powerpc mpc8xx - - - RPXClassic - - -Orphan powerpc mpc8xx - - - RPXlite - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b068544..9915500 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,8 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +RPXClassic powerpc mpc8xx - 2014-04-04 +RPXlite powerpc mpc8xx - 2014-04-04 genietv powerpc mpc8xx - 2014-04-04 mbx8xx powerpc mpc8xx - 2014-04-04 nx823 powerpc mpc8xx - 2014-04-04 diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 3732583..6638277 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -211,7 +211,7 @@ static u_int m8xx_get_graycode(u_int size)

#if 0

-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +#if defined(CONFIG_RPXLITE)

/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. * SYPCR is write once only, therefore must the slowest memory be faster diff --git a/drivers/pcmcia/rpx_pcmcia.c b/drivers/pcmcia/rpx_pcmcia.c index c7c425b..5b24f0b 100644 --- a/drivers/pcmcia/rpx_pcmcia.c +++ b/drivers/pcmcia/rpx_pcmcia.c @@ -18,7 +18,7 @@ #endif

#if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)) + && defined(CONFIG_RPXLITE)

#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"

@@ -70,4 +70,4 @@ static int pcmcia_hardware_disable(int slot) #endif

-#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ +#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */ diff --git a/include/common.h b/include/common.h index 580615b..baf361b 100644 --- a/include/common.h +++ b/include/common.h @@ -505,10 +505,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif

-#ifdef CONFIG_RPXCLASSIC -void rpxclassic_init (void); -#endif - void rpxlite_init (void);

#ifdef CONFIG_HERMES diff --git a/include/commproc.h b/include/commproc.h index 605aac2..29a3e61 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -954,41 +954,6 @@ typedef struct scc_enet {

#endif /* CONFIG_QS860T */

-/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC - -#ifdef CONFIG_FEC_ENET - -# define FEC_ENET /* use FEC for EThernet */ -# undef SCC_ENET - -#else /* ! CONFIG_FEC_ENET */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_RPXCLASSIC */ - /*** RPXLITE ********************************************************/

#ifdef CONFIG_RPXLITE diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h deleted file mode 100644 index 0f07d0c..0000000 --- a/include/configs/RPXClassic.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXClassic_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_RPXCLASSIC 1 - -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ - -/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */ -#define CONFIG_FEC_ENET -#ifdef CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#endif /* CONFIG_FEC_ENET */ -#define CONFIG_MISC_INIT_R - -/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */ -#if 1 -#define CONFIG_VIDEO_SED13806 -#define CONFIG_NEC_NL6448BC20 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ELF - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x34 - - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#if defined(CONFIG_SYS_I2C_SOFT) -#define CONFIG_SYS_I2C 1 -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x34 -#endif - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE 0xFF000000 -/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0xfa000100 -#define CONFIG_ENV_SIZE 0x1000 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/* #define CONFIG_SYS_DER 0x2002000F */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xff7f8970 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFF80970 - -/* ECCX CS settings */ -#define SED13806_OR 0xFFC00108 /* - 4 Mo - - Burst inhibit - - external TA */ -#define SED13806_REG_ADDR 0xa0000000 -#define SED13806_ACCES 0x801 /* 16 bit access */ - - -/* Global definitions for the ECCX board */ -#define ECCX_CSR_ADDR (0xfac00000) -#define ECCX_CSR8_OFFSET (0x8) -#define ECCX_CSR11_OFFSET (0xB) -#define ECCX_CSR12_OFFSET (0xC) - -#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) -#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) -#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) - - -#define REG_GPIO_CTRL 0x008 - -/* Definitions for CSR8 */ -#define ECCX_ENEPSON 0x80 /* Bit 0: - 0= disable and reset SED1386 - 1= enable SED1386 */ -/* Bit 1: 0= SED1386 in Big Endian mode */ -/* 1= SED1386 in little endian mode */ -#define ECCX_LE 0x40 -#define ECCX_BE 0x00 - -/* Bit 2,3: Selection */ -/* 00 = Disabled */ -/* 01 = CS2 is used for the SED1386 */ -/* 10 = CS5 is used for the SED1386 */ -/* 11 = reserved */ -#define ECCX_CS2 0x10 -#define ECCX_CS5 0x20 - -/* Definitions for CSR12 */ -#define ECCX_ID 0x02 -#define ECCX_860 0x01 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_MIIRST 0x80 -#define BCSR2_MIIPWRDWN 0x40 -#define BCSR2_MIICTL 0x08 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ -/* #define CONFIG_IPADDR 10.10.106.1 */ -/* #define CONFIG_SERVERIP 10.10.104.11 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h deleted file mode 100644 index a28230a..0000000 --- a/include/configs/RPXlite.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXLite_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* play along with the linux driver */ -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 1ad3e63..952a67c 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -22,7 +22,7 @@ #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)

/* The RPX series use SLOT_B */ -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +#if defined(CONFIG_RPXLITE) # define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_FADS) /* The FADS series are a mess */ # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index 53c0e4d..d122500 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -365,11 +365,6 @@ static void scc_init (int scc_index) immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | SCC_PSMR_LPB;

-#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - #ifdef CONFIG_RPXLITE *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif @@ -386,8 +381,6 @@ static void scc_init (int scc_index) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ #endif }

diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index 25d63d8..5214c71 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -106,7 +106,7 @@ static void smc_init (int smc_index) ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); #endif

-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +#if defined(CONFIG_RPXLITE) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; #endif

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/rpxsuper/* - Remove include/configs/RPXsuper.h - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

board/rpxsuper/Makefile | 8 - board/rpxsuper/flash.c | 416 ------------------------------------- board/rpxsuper/mii_phy.c | 107 ---------- board/rpxsuper/readme | 30 --- board/rpxsuper/rpxsuper.c | 289 -------------------------- board/rpxsuper/rpxsuper.h | 25 --- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/RPXsuper.h | 501 --------------------------------------------- 9 files changed, 1 insertion(+), 1377 deletions(-) delete mode 100644 board/rpxsuper/Makefile delete mode 100644 board/rpxsuper/flash.c delete mode 100644 board/rpxsuper/mii_phy.c delete mode 100644 board/rpxsuper/readme delete mode 100644 board/rpxsuper/rpxsuper.c delete mode 100644 board/rpxsuper/rpxsuper.h delete mode 100644 include/configs/RPXsuper.h

diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile deleted file mode 100644 index 239b419..0000000 --- a/board/rpxsuper/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rpxsuper.o flash.o mii_phy.o diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c deleted file mode 100644 index 24bcd7c..0000000 --- a/board/rpxsuper/flash.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger mgroeger@sysgo.de - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * Added support for 64bit and AMD 29DL323B - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/io.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define RD_SWP32(x) in_le32((volatile u32*)x) - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* for now, only support the 4 MB Flash SIMM */ - (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, - &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD "); - break; - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("FUJITSU "); - break; - case (SST_MANUFACT & FLASH_VENDMASK): - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_DL323B & FLASH_TYPEMASK): - printf("AM29DL323B (32 MBit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor[2], devid[2]; - ulong base = (ulong)addr; - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[1] = 0xf0f0f0f0; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - - vendor[0] = RD_SWP32(&addr[0]); - vendor[1] = RD_SWP32(&addr[1]); - if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { - info->size = 0; - goto out; - } - - devid[0] = RD_SWP32(&addr[2]); - devid[1] = RD_SWP32(&addr[3]); - - if (devid[0] == AMD_ID_DL323B) { - /* - * we have 2 Banks - * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte - * Bank 2 (48 Sectors): 23-70=64kbyte - */ - info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_DL323B & FLASH_TYPEMASK); - info->sector_count = 71; - info->size = 4 * (8 * 8 + 63 * 64) * 1024; - } - else { - info->size = 0; - goto out; - } - - /* set up sector start address table */ - for (i = 0; i < 8; i++) { - info->start[i] = base + (i * 0x8000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address */ - addr = (volatile unsigned long *)(info->start[i]); - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - base = RD_SWP32(&addr[4]); - base |= RD_SWP32(&addr[5]); - info->protect[i] = base & 0x00010001 ? 1 : 0; - } - addr = (vu_long*)info->start[0]; - -out: - /* reset command */ - addr[0] = 0xf0f0f0f0; - addr[1] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x80808080; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x80808080; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - addr[1] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ( (addr[0] & 0x80808080) != 0x80808080 || - (addr[1] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - addr[1] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if ((dest & 0x00000004) == 0) { - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0xA0A0A0A0; - } - else { - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xA0A0A0A0; - } - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c deleted file mode 100644 index 12e23f4..0000000 --- a/board/rpxsuper/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include <common.h> -#include <mii_phy.h> -#include "rpxsuper.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme deleted file mode 100644 index 21267bd..0000000 --- a/board/rpxsuper/readme +++ /dev/null @@ -1,30 +0,0 @@ -Hi, - -so this is the port to the Embedded Planet RPX Super Board. - -ATTENTION -This code is only tested on the AY-Version, which is an early release with some -hardware bugs. The main problem is that this board uses the default Hard Reset -Configuration Word and not the 4 bytes located at start of FLASH because at -0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be -carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low -byte. - -The icache can only manually be enabled after reset. -The FLASH and main SDRAM is working with icache enabled. -The local SDRAM can only be used as data memory when icache is enabled. -If U-Boot runs in local SDRAM, TFTP does not work. -The functions in mii_phy.c are all working. Call mii_phy_discover() out of -eth_init() and solve the linker error. -I2C, RTC/NVRAM and PCMCIA are not working yet. - -TODO -The 32MB local SDRAM is working but not shown in the startup messages of -U-Boot. If you locate U-Boot or any other program to this area it won't run. -Turning the ichache off does not solve this problem. - -As I won't buy another RPX Super there might be some little work to do for you -getting this U-Boot port running on the final board. - - -frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c deleted file mode 100644 index dc55870..0000000 --- a/board/rpxsuper/rpxsuper.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2001 - * Advent Networks, Inc. http://www.adventnetworks.com - * Jay Monkman jtm@smoothsmoothie.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include "rpxsuper.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ - regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ - return 0; -} - -void -reset_phy(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - regs->bcsr4 = 0xC3; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - printf ("Board: Embedded Planet RPX Super, Revision %d\n", - regs->bcsr0 >> 4); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr; - ulong psdmr, lsdmr, bcr; - long size = 0; - int i; - - psdmr = CONFIG_SYS_PSDMR; - lsdmr = CONFIG_SYS_LSDMR; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - size = CONFIG_SYS_SDRAM0_SIZE; - bcr = immap->im_siu_conf.sc_bcr; - immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE); - memctl->memc_psrt = CONFIG_SYS_PSRT; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - immap->im_siu_conf.sc_bcr = bcr; - -#ifndef CONFIG_SYS_RAMBOOT -/* size += CONFIG_SYS_SDRAM1_SIZE; */ - ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE); - memctl->memc_lsrt = CONFIG_SYS_LSRT; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif - - /* return total ram size */ - return (size * 1024 * 1024); -} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h deleted file mode 100644 index af31060..0000000 --- a/board/rpxsuper/rpxsuper.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __RPX8260_H__ -#define __RPX8260_H__ - -typedef struct tt_rpx_regs -{ - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_rpx_regs; -typedef t_rpx_regs* tp_rpx_regs; - -#endif diff --git a/boards.cfg b/boards.cfg index e0bf130..c9f8036 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1240,4 +1240,3 @@ Orphan arm pxa - - - Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - Orphan powerpc mpc824x - - mousse MOUSSE - - Orphan powerpc mpc8260 - - - rsdproto - - -Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 9915500..125ba80 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +RPXsuper powerpc mpc8260 - 2014-04-04 RPXClassic powerpc mpc8xx - 2014-04-04 RPXlite powerpc mpc8xx - 2014-04-04 genietv powerpc mpc8xx - 2014-04-04 diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h deleted file mode 100644 index f5e0968..0000000 --- a/include/configs/RPXsuper.h +++ /dev/null @@ -1,501 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x80F00000 - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ -/* for the AY-Revision which does not use the HRCW */ -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/* How is switch S2 set? We really only want the MODCK[1-3] bits, so - * only the 3 least significant bits are important. -*/ -#define CONFIG_SYS_SBC_S2 0x04 - -/* What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * 0x2 0x2 33 133 133 - * 0x2 0x4 33 133 200 - * 0x5 0x5 66 133 133 - * 0x5 0x7 66 133 200 - */ -#define CONFIG_SYS_SBC_MODCK_H 0x06 - -#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */ -#undef CONFIG_SYS_SBC_BOOT_LOW - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0x80000000 -#define CONFIG_SYS_FLASH0_SIZE 16 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CONFIG_SYS_FLASH1_BASE 0 -#define CONFIG_SYS_FLASH1_SIZE 0 -#undef CONFIG_SYS_FLASH1_BASE -#undef CONFIG_SYS_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM1_BASE 0x04000000 -#define CONFIG_SYS_SDRAM1_SIZE 32 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0x00000000 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CONFIG_SYS_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on RPX Super ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 08:00:22:50:70:63 - -#define CONFIG_IPADDR 192.168.1.99 -#define CONFIG_SERVERIP 192.168.1.3 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/* Where do the on board registers (CS4) live? */ -#define CONFIG_SYS_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\ - HRCW_DPPC11 |\ - CONFIG_SYS_SBC_HRCW_IMMR |\ - HRCW_MMR00 |\ - HRCW_LBPC11 |\ - HRCW_APPC10 |\ - HRCW_CS10PC00 |\ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000) - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\ - /*HID0_DCE |*/\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, LEDs, switches - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/* Bank 0 - FLASH - * - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_6_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12 |\ - ORxS_IBID) - -#define CONFIG_SYS_PSDMR 0x014DA412 -#define CONFIG_SYS_PSRT 0x79 - - -/* Bank 2 - SDRAM - * - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR 0x0169A512 -#define CONFIG_SYS_LSRT 0x79 - -#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK) - -/* Bank 4 - On board registers - * - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -#endif /* __CONFIG_H */

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/rsdproto/* - Remove include/configs/rsdproto.h - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

board/rsdproto/Makefile | 9 - board/rsdproto/flash.c | 386 ------------------------------------------- board/rsdproto/flash_asm.S | 39 ----- board/rsdproto/rsdproto.c | 361 ---------------------------------------- board/rsdproto/u-boot.lds | 114 ------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/rsdproto.h | 400 --------------------------------------------- 8 files changed, 1 insertion(+), 1310 deletions(-) delete mode 100644 board/rsdproto/Makefile delete mode 100644 board/rsdproto/flash.c delete mode 100644 board/rsdproto/flash_asm.S delete mode 100644 board/rsdproto/rsdproto.c delete mode 100644 board/rsdproto/u-boot.lds delete mode 100644 include/configs/rsdproto.h

diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile deleted file mode 100644 index 9351e94..0000000 --- a/board/rsdproto/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rsdproto.o flash.o -obj-y += flash_asm.o diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c deleted file mode 100644 index 37326d5..0000000 --- a/board/rsdproto/flash.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger mgroeger@sysgo.de - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/* flash hardware ids */ -#define VENDOR_AMD 0x0001 -#define AMD_29DL323C_B 0x2253 - -/* Define this to include autoselect sequence in flash_init(). Does NOT - * work when executing from flash itself, so this should be turned - * on only when debugging the RAM version. - */ -#undef WITH_AUTOSELECT - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if 1 -#define D(x) -#else -#define D(x) printf x -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data); - -/* from flash_asm.S */ -extern void ull_write(unsigned long long volatile *address, - unsigned long long volatile *data); -extern void ull_read(unsigned long long volatile *address, - unsigned long long volatile *data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong addr; - -#ifdef WITH_AUTOSELECT - { - unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; - unsigned long long f_command, vendor, device; - /* Perform Autoselect */ - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0090009000900090ULL; - ull_write(&f_addr[0x555], &f_command); - ull_read(&f_addr[0], &vendor); - vendor &= 0xffff; - ull_read(&f_addr[1], &device); - device &= 0xffff; - f_command = 0x00F000F000F000F0ULL; - ull_write(&f_addr[0x555], &f_command); - if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) - return 0; - } -#endif - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* 1st bank: 8 x 32 KB sectors */ - flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B; - flash_info[0].sector_count = 8; - flash_info[0].size = flash_info[0].sector_count * 32 * 1024; - addr = PHYS_FLASH; - for(i = 0; i < flash_info[0].sector_count; i++) { - flash_info[0].start[i] = addr; - addr += flash_info[0].size / flash_info[0].sector_count; - } - /* 1st bank: 63 x 256 KB sectors */ - flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B; - flash_info[1].sector_count = 63; - flash_info[1].size = flash_info[1].sector_count * 256 * 1024; - for(i = 0; i < flash_info[1].sector_count; i++) { - flash_info[1].start[i] = addr; - addr += flash_info[1].size / flash_info[1].sector_count; - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - - return flash_info[0].size + flash_info[1].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case VENDOR_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_29DL323C_B: - printf ("AM29DL323CB (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start; - unsigned long long volatile *f_addr; - unsigned long long volatile f_command; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0080008000800080ULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - f_addr = - (unsigned long long *)(info->start[sect]); - f_command = 0x0030003000300030ULL; - ull_write(f_addr, &f_command); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) - { /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = - (unsigned long long *)(info->start[l_sect]); - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - printf (" timeout\n"); - return 1; - } - } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - unsigned long cp, wp; - unsigned long long data; - int i, l, rc; - - wp = (addr & ~7); /* get lower long long aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<8 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle long long aligned part - */ - while (cnt >= 8) { - data = 0; - for (i=0; i<8; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return write_ull(info, wp, data); -} - -/*--------------------------------------------------------------------------- -* -* FUNCTION NAME: write_ull -* -* DESCRIPTION: writes 8 bytes to flash -* -* EXTERNAL EFFECT: nothing -* -* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data -* -* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error -*--------------------------------------------------------------------------*/ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data) -{ - static unsigned long long f_command; - static unsigned long long *f_addr; - ulong start; - - /* address muss be 8-aligned! */ - if (address & 0x7) - return ERR_ALIGN; - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x00A000A000A000A0ULL; - ull_write(&f_addr[0x555], &f_command); - - f_addr = (unsigned long long *)address; - f_command = data; - ull_write(f_addr, &f_command); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - { - /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - return ERR_TIMOUT; - } - } while(*((unsigned long long *)address) != data); - - return 0; -} diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S deleted file mode 100644 index 557cac0..0000000 --- a/board/rsdproto/flash_asm.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * -*- mode:c -*- - * - * (C) Copyright 2000 - * Marius Groeger mgroeger@sysgo.de - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * void ull_write(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * void ull_read(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * Uses the floating point unit to read and write 64 bit wide - * data (unsigned long long) on the 60x bus. This is necessary - * because all 4 flash chips use the /WE line from byte lane 0 - * - * IMPORTANT: data should always be 8-aligned, otherwise an exception will - * occur. - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - - .globl ull_write -ull_write: - lfd 0,0(r4) - stfd 0,0(r3) - blr - - .globl ull_read -ull_read: - lfd 0, 0(r3) - stfd 0, 0(r4) - blr diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c deleted file mode 100644 index 1e85c27..0000000 --- a/board/rsdproto/rsdproto.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <i2c.h> -#include <bcd.h> - -/* define to initialise the SDRAM on the local bus */ -#undef INIT_LOCAL_BUS_SDRAM - -/* I2C Bus adresses for PPC & Protocol board */ -#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ -#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ -#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ -#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ -#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ -#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, - /* PA0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, - /* PC0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -struct tm { - unsigned int tm_sec; - unsigned int tm_min; - unsigned int tm_hour; - unsigned int tm_wday; - unsigned int tm_mday; - unsigned int tm_mon; - unsigned int tm_year; -}; - -void read_RS5C372_time (struct tm *timedate) -{ - unsigned char buffer[8]; - - if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { - timedate->tm_sec = bcd2bin (buffer[0]); - timedate->tm_min = bcd2bin (buffer[1]); - timedate->tm_hour = bcd2bin (buffer[2]); - timedate->tm_wday = bcd2bin (buffer[3]); - timedate->tm_mday = bcd2bin (buffer[4]); - timedate->tm_mon = bcd2bin (buffer[5]); - timedate->tm_year = bcd2bin (buffer[6]) + 2000; - } else { - /*printf("i2c error %02x\n", rc); */ - memset (timedate, 0, sizeof (struct tm)); - } -} - -/* ------------------------------------------------------------------------- */ - -int read_LM84_temp (int address) -{ - unsigned char buffer[8]; - /*int rc;*/ - - if (! i2c_read (address, 0, 1, buffer, 1)) { - return (int) buffer[0]; - } else { - /*printf("i2c error %02x\n", rc); */ - return -42; - } -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - struct tm timedate; - unsigned int ppctemp, prottemp; - - puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); - - /* initialise i2c */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - read_RS5C372_time (&timedate); - printf (" Time: %02d:%02d:%02d\n", - timedate.tm_hour, timedate.tm_min, timedate.tm_sec); - printf (" Date: %02d-%02d-%04d\n", - timedate.tm_mday, timedate.tm_mon, timedate.tm_year); - ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); - prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); - printf (" Temp: PPC %d C, Protocol Board %d C\n", - ppctemp, prottemp); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifdef INIT_LOCAL_BUS_SDRAM - volatile uchar *ramaddr8; -#endif - volatile ulong *ramaddr32; - ulong sdmr; - int i; - - /* - * Only initialize SDRAM when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x02; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - /* - * Program local/60x bus Transfer Error Status and Control Regs: - * Disable parity errors - */ - immap->im_siu_conf.sc_tescr1 = 0x00040000; - immap->im_siu_conf.sc_ltescr1 = 0x00040000; - - /* - * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) - * - * The appropriate BRx/ORx registers have already - * been set when we get here (see cpu_init_f). The - * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - memctl->memc_mptpr = 0x2000; - memctl->memc_mar = 0x0200; -#ifdef INIT_LOCAL_BUS_SDRAM - /* initialise local bus ram - * - * (using the PSRMR_ definitions is NOT an error here - * - the LSDMR has the same fields as the PSDMR!) - */ - memctl->memc_lsrt = 0x0b; - memctl->memc_lurt = 0x00; - ramaddr = (uchar *) PHYS_SDRAM_LOCAL; - sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; - *ramaddr = 0xff; - for (i = 0; i < 8; i++) { - memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; - *ramaddr = 0xff; - } - memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; - *ramaddr = 0xff; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM; -#endif - /* initialise 60x bus ram */ - memctl->memc_psrt = 0x0b; - memctl->memc_purt = 0x08; - ramaddr32 = (ulong *) PHYS_SDRAM_60X; - sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - } - memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - } - - /* return the size of the 60x bus ram */ - return PHYS_SDRAM_60X_SIZE; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("misc_init_r\n"); - return (0); -} diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds deleted file mode 100644 index 44bcd19..0000000 --- a/board/rsdproto/u-boot.lds +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8260/start.o (.text) - *(.text) - *(.got1) - /*. = env_offset; */ - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index c9f8036..91ad9ce 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1239,4 +1239,3 @@ Orphan arm arm1136 mx31 freescale - Orphan arm pxa - - - lubbock - (dead address) Kyle Harris kharris@nexus-tech.net Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - Orphan powerpc mpc824x - - mousse MOUSSE - - -Orphan powerpc mpc8260 - - - rsdproto - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 125ba80..adcf163 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +rsdproto powerpc mpc8260 - 2014-04-04 RPXsuper powerpc mpc8260 - 2014-04-04 RPXClassic powerpc mpc8xx - 2014-04-04 RPXlite powerpc mpc8xx - 2014-04-04 diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h deleted file mode 100644 index 0621138..0000000 --- a/include/configs/rsdproto.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen Murray.Jensen@cmst.csiro.au - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Configuation settings for the R&S Protocol Board board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xff000000 -#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds" - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE (0) -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* enable I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x30 - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 50000000 /* in Hz */ - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_KGDB - - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_RSD_BOOT_LOW 1 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5a -#define CONFIG_NETMASK 255.255.0.0 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ -#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ - -#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ -#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ -#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ - -/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ -/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ -#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ - -/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ -/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ -#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 - -#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ -#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ - -#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ - -#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ - -#define CONFIG_SYS_IMMR PHYS_IMMR - -/*----------------------------------------------------------------------- - * Reset Address - * - * In order to reset the CPU, U-Boot jumps to a special address which - * causes a machine check exception. The default address for this is - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when - * testing the monitor in RAM using a JTAG debugger. - * - * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to - * cause a bus error on your hardware. - */ -#define CONFIG_SYS_RESET_ADDRESS 0x20000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CONFIG_SYS_RSD_BOOT_LOW) -# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_RSD_HRCW_IMMR |\ - HRCW_MMR00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - HRCW_MODCK_H0000 |\ - CONFIG_SYS_RSD_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend. - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH -/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMBOOT -#endif -#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ - -/* turn off NVRAM env feature */ -#undef CONFIG_NVRAM_ENV - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0x100c0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ - SIUMCR_CS10PC01 | SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ - SYPCR_SWRI | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0x00000000 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - */ - -#define CONFIG_SYS_PSDMR 0x494D2452 -#define CONFIG_SYS_LSDMR 0x49492552 - -/* Flash */ -#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V) -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ - ORxG_BCTLD | \ - ORxG_SCY_5_CLK) - -/* DPRAM to the PCI BUS on the protocol board */ -#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ - ORxG_ACS_DIV4) - -/* 60x Bus SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) -#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A2 | \ - ORxS_NUMR_13 | \ - ORxS_IBID) - -/* Virtex-FPGA - Register */ -#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) -#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ - ORxG_SCY_1_CLK | \ - ORxG_ACS_DIV2 | \ - ORxG_CSNT ) - -/* local bus SDRAM */ -#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) -#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A4 | \ - ORxS_NUMR_13) - -/* DPRAM to the Sharc-Bus on the protocol board */ -#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ - ORxG_ACS_DIV4) - -#endif /* __CONFIG_H */

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/mousse/* - Remove include/configs/MOUSSE.h - Clean-up defined(CONFIG_MOUSSE) - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

CREDITS | 4 - arch/powerpc/cpu/mpc824x/cpu_init.c | 88 ---- board/mousse/Makefile | 8 - board/mousse/README | 346 -------------- board/mousse/flash.c | 917 ------------------------------------ board/mousse/flash.h | 78 --- board/mousse/m48t59y.c | 308 ------------ board/mousse/m48t59y.h | 41 -- board/mousse/mousse.c | 77 --- board/mousse/mousse.h | 243 ---------- board/mousse/pci.c | 267 ----------- board/mousse/u-boot.lds | 77 --- board/mousse/u-boot.lds.ram | 85 ---- board/mousse/u-boot.lds.rom | 112 ----- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/MOUSSE.h | 320 ------------- 17 files changed, 1 insertion(+), 2972 deletions(-) delete mode 100644 board/mousse/Makefile delete mode 100644 board/mousse/README delete mode 100644 board/mousse/flash.c delete mode 100644 board/mousse/flash.h delete mode 100644 board/mousse/m48t59y.c delete mode 100644 board/mousse/m48t59y.h delete mode 100644 board/mousse/mousse.c delete mode 100644 board/mousse/mousse.h delete mode 100644 board/mousse/pci.c delete mode 100644 board/mousse/u-boot.lds delete mode 100644 board/mousse/u-boot.lds.ram delete mode 100644 board/mousse/u-boot.lds.rom delete mode 100644 include/configs/MOUSSE.h

diff --git a/CREDITS b/CREDITS index 52f289e..3e5fb7b 100644 --- a/CREDITS +++ b/CREDITS @@ -120,10 +120,6 @@ N: Dan A. Dickey E: ddickey@charter.net D: FADS Support

-N: James F. Dougherty -E: jfd@GigabitNetworks.COM -D: Port to the MOUSSE board - N: Mike Dunn E: mikedunn@newsguy.com D: Palmtreo680 board, docg4 nand flash driver diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 47ac18e..68d88e9 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -46,8 +46,6 @@ void cpu_init_f (void) { -/* MOUSSE board is initialized in asm */ -#if !defined(CONFIG_MOUSSE) register unsigned long val; CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ @@ -302,98 +300,12 @@ cpu_init_f (void) CONFIG_READ_WORD(MCCR1, val); CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ __asm__ __volatile__("eieio"); - -#endif /* !CONFIG_MOUSSE */ }

- -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT -struct MPC107_s { - unsigned int iobase; - char desc[120]; -} MPC107Regs[] = { - { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, - { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, - { BMC_BASE + 0x08, "MPC107 Revision" }, - { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, - { BMC_BASE + 0x10, "MPC107 LMBAR" }, - { BMC_BASE + 0x14, "MPC824x PCSR" }, - { BMC_BASE + 0xA8, "MPC824x PICR1" }, - { BMC_BASE + 0xAC, "MPC824x PICR2" }, - { BMC_BASE + 0x46, "MPC824x PACR" }, - { BMC_BASE + 0x310, "MPC824x ITWR" }, - { BMC_BASE + 0x300, "MPC824x OMBAR" }, - { BMC_BASE + 0x308, "MPC824x OTWR" }, - { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, - { BMC_BASE + 0x78, "MPC107 EUMBAR" }, - { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, - { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, - { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, - { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, - { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, - { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, - { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, - { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, -}; -#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - /* * initialize higher level parts of CPU like time base and timers */ int cpu_init_r (void) { -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT - unsigned int tmp = 0, i; -#endif - /* - * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg). - * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can - * be accessed. - */ - -#ifdef CONFIG_MPC8240 /* only on MPC8240 */ - mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL); - /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */ - mpc824x_mpc107_setreg (AMBOR, 0x000000C0); -#endif - - -#ifdef INCLUDE_MPC107_REPORT - /* Check MPC824x PCI Device and Vendor ID */ - while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) { - printf (" MPC107: offset=0x%x, val = 0x%x\n", - BMC_BASE, - tmp); - } - - for (i = 0; i < N_MPC107_Regs; i++) { - printf (" 0x%x/%s = 0x%x\n", - MPC107Regs[i].iobase, - MPC107Regs[i].desc, - mpc824x_mpc107_getreg (MPC107Regs[i].iobase)); - } - - printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L)); - printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U)); - printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L)); - printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U)); - printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L)); - printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U)); - printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L)); - printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U)); - printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L)); - printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U)); - printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L)); - printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U)); - printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L)); - printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U)); - printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L)); - printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U)); -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ return (0); } diff --git a/board/mousse/Makefile b/board/mousse/Makefile deleted file mode 100644 index e2951d5..0000000 --- a/board/mousse/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mousse.o m48t59y.o pci.o flash.o diff --git a/board/mousse/README b/board/mousse/README deleted file mode 100644 index d5dda7a..0000000 --- a/board/mousse/README +++ /dev/null @@ -1,346 +0,0 @@ - -U-Boot for MOUSSE/MPC8240 (KAHLUA) ----------------------------------- -James Dougherty (jfd@broadcom.com), 09/10/01 - -The Broadcom/Vooha Mousse board is a 3U Compact PCI system board -which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard -DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH. -See also: http://www.vooha.com/ - -* NVRAM setenv/printenv/savenv supported. -* Date Command -* Serial Console support -* Network support -* FLASH of kernel images is supported. -* FLASH of U-Boot to onboard and PLCC boot region. -* Kernel command line options from NVRAM is supported. -* IP PNP options supported. - -U-Boot Loading... - - -U-Boot 1.0.5 (Sep 10 2001 - 00:22:25) - -CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B) -Built: Sep 10 2001 at 01:01:50 -MPLD: Revision 127 -Local Bus: 33 MHz -RTC: M48T589 TOD/NVRAM (8176) bytes - Current date/time: 9/10/2001 0:18:52 -DRAM: 64 MB -FLASH: 1.960 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 11 00000008 00000000 01 00 - 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01 - 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03 -In: serial -Out: serial -Err: serial - -Hit any key to stop autoboot: 0 -=> - -I. Root FileSystem/IP Configuration - -bootcmd=tftp 100000 vmlinux.img;bootm -bootdelay=3 -baudrate=9600 -ipaddr=<IP ADDRESS> -netmask=<NETMASK> -hostname=<NAME> -serverip=<NFS SERVER IP ADDRESS> -ethaddr=00:00:10:20:30:44 -nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs -gateway=<IP ADDRESS> -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -NVRAM environment variables. - -use the command: - -setenv <attribute> <value> - -type "saveenv" to write to NVRAM. - - -II. To boot from a hard drive: - -setenv root /dev/hda1 - - -III. IP options which configure the network: - -ipaddr=<IP ADDRESS OF MACHINE> -netmask=<NETMASK> -hostname=mousse -ethaddr=00:00:10:20:30:44 -gateway=<IP ADDRESS OF GATEWAY/ROUTER> - - -IV. IP Options which configure NFS Root/Boot Support - -root=/dev/nfs -serverip=<NFS SERVER IP ADDRESS> -nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs - -V. U-Boot Image Support - -The U-Boot boot loader assumes that after you build -your kernel (vmlinux), you will create a U-Boot image -using the following commands or script: - -#!/bin/csh -/bin/touch vmlinux.img -/bin/rm vmlinux.img -set path=($TOOLBASE/bin $path) -set path=($U_BOOT/tools $path) -powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin -gzip -vf vmlinux.bin -mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img -ls -l vmlinux.img - - -VI. ONBOARD FLASH Support - -FLASH support is provided for the onboard FLASH chip Bootrom area. -U-Boot is loaded into either the ROM boot region of the FLASH chip, -after first being boot-strapped from a pre-progammed AMD29F040 PLCC -bootrom. The PLCC needs to be programmed with a ROM burner using -AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record) -images. - -The PLCC overlays this same region of flash as the onboard FLASH, -the jumper J100 is a chip-select for which flash chip you want to -progam. When jumper J100 is connected to pins 2-3, you boot from -PLCC FLASH. - -To bringup a system, simply flash a flash an AMD29F040 PLCC -bootrom, and put this in the PLCC socket. Move jumper J100 to -pins 2-3 and boot from the PLCC. - - -Now, while the system is running, move Jumper J100 to -pins 1-2 and follow the procedure below to FLASH a bootrom -(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB): - -tftp 100000 u-boot.bin -protect off FFF00000 FFF7FFFF -erase FFF00000 FFF7FFFF -cp.b 100000 FFF00000 ${filesize}\ - - -Here is an example: - -=>tftp 100000 u-boot.bin -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 123220 (1e154 hex) -eth_halt -=>protect off FFF00000 FFF7FFFF -Un-Protected 8 sectors -=>erase FFF00000 FFF7FFFF -Erase Flash from 0xfff00000 to 0xfff7ffff -Erase FLASH[PLCC_BOOT] -8 sectors:........ done -Erased 8 sectors -=>cp.b 100000 FFF00000 1e154 -Copy to Flash... FLASH[PLCC_BOOT]:..done -=> - - -B. FLASH RAMDISK REGION - -FLASH support is provided for an Onboard 512K RAMDISK region. - -TThe following commands will FLASH a bootrom (u-boot.bin) image -into the onboard FLASH region (AMD29LV160DB 2MB FLASH): - -tftp 100000 u-boot.bin -protect off FFF80000 FFFFFFFF -erase FFF80000 FFFFFFFF -cp.b 100000 FFF80000 ${filesize}\ - - -C. FLASH KERNEL REGION (960KB) - -FLASH support is provided for the 960KB onboard FLASH1 segment. -This allows flashing of kernel images which U-Boot can load -and run (standalone) from the onboard FLASH chip. It also assumes - -The following commands will FLASH a kernel image to 0xffe10000 - -tftp 100000 vmlinux.img -protect off FFE10000 FFEFFFFF -erase FFE10000 FFEFFFFF -cp.b 100000 FFE10000 ${filesize}\ -reset - -Here is an example: - - -=>tftp 100000 vmlinux.img -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -TFTP from server 209.128.93.133; our IP address is 209.128.93.138 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ##################################################################################################################################################### -done -Bytes transferred = 760231 (b99a7 hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b99a7 -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=> - - -When finished, use the command: - -bootm ffe10000 - -to start the kernel. - -Finally, to make this the default boot command, use -the following commands: - -setenv bootcmd bootm ffe10000 -savenv - -to make it automatically boot the kernel from FLASH. - - -To go back to development mode (NFS boot) - -setenv bootcmd tftp 100000 vmlinux.img;bootm -savenv - - -=>tftp 100000 vmlinux.img -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: #################################################################################################################################################### -done -Bytes transferred = 752717 (b7c4d hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b7c4d -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=>bootm ffe10000 -## Booting image at ffe10000 ... - Image Name: vmlinux.bin.gz - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 752653 Bytes = 735 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Total memory = 64MB; using 0kB for hash table (at 00000000) -Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001 -cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f -Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com) -IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44> -NOTICE: mounting root file system via NFS -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -time_init: decrementer frequency = 16.665914 MHz -time_init: MPC8240 PCI Bus frequency = 33.331828 MHz -Calibrating delay loop... 133.12 BogoMIPS -Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem) -Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd v1.8 -pty: 256 Unix98 ptys configured -block: queued sectors max/low 41394kB/13798kB, 128 slots per queue -Uniform Multi-Platform E-IDE driver Revision: 6.31 -ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -PDC20262: IDE controller on PCI bus 00 dev 70 -PDC20262: chipset revision 1 -PDC20262: not 100% native mode: will probe irqs later -PDC20262: ROM enabled at 0x000d0000 -PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. -PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE -PDC20262: irq=3 dev->irq=3 - ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio -hda: WDC WD300AB-00BVA0, ATA DISK drive -hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive -ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3 -ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3 -hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66) -hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache -Uniform CD-ROM driver Revision: 3.12 -Partition check: - /dev/ide/host0/bus0/target0/lun0: p1 p2 -hd: unable to get major 3 for hard disk -udf: registering filesystem -loop: loaded (max 8 devices) -Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -ttyS00 at 0xffe08080 (irq = 4) is a ST16650 -Linux Tulip driver version 0.9.13a (January 20, 2001) -eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1. -eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1. -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au) -devfs: boot_options: 0x0 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 88k init 4k openfirmware -eth0: Setting full-duplex based on MII#0 link partner capability of 45e1. -INIT: version 2.78 booting -INIT: Entering runlevel: 2 - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse login: root -Password: -PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Sep 6 00:16:51 2001 on console - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse# diff --git a/board/mousse/flash.c b/board/mousse/flash.c deleted file mode 100644 index acedcb1..0000000 --- a/board/mousse/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * Flash Routines for MOUSSE onboard AMD29LV106DB devices - * - * (C) Copyright 2000 - * Marius Groeger mgroeger@sysgo.de - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <malloc.h> -#include "mousse.h" -#include "flash.h" - -int flashLibDebug = 0; -int flashLibInited = 0; - -#define OK 0 -#define ERROR -1 -#define STATUS int -#define PRINTF if (flashLibDebug) printf -#if 0 -#define PRIVATE static -#else -#define PRIVATE -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define SLEEP_DELAY 166 -#define FLASH_SECTOR_SIZE (64*1024) -/*********************************************************************** - * - * Virtual Flash Devices on Mousse board - * - * These must be kept in sync with the definitions in flashLib.h. - * - ***********************************************************************/ - -PRIVATE flash_dev_t flashDev[] = { - /* Bank 0 sector SA0 (16 kB) */ - { "SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA1 (8 kB) */ - { "SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA2 (8 kB) */ - { "SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA3 is occluded by Mousse I/O devices */ - /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB) */ - { "KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */ - /* This is where the Kahlua boot vector and boot ROM code resides. */ - { "BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA27-SA34 (512 kB) */ - { "RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, -}; - -int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0])); - -#define DEV(no) (&flashDev[no]) -#define DEV_NO(dev) ((dev) - flashDev) - -/*********************************************************************** - * - * Private Flash Routines - * - ***********************************************************************/ - -/* - * The convention is: - * - * "addr" is always the PROM raw address, which is the address of an - * 8-bit quantity for flash 0 and 16-bit quantity for flash 1. - * - * "pos" is always a logical byte position from the PROM beginning. - */ - -#define FLASH0_ADDR(dev, addr) \ - ((unsigned char *) ((dev)->base + (addr))) - -#define FLASH0_WRITE(dev, addr, value) \ - (*FLASH0_ADDR(dev, addr) = (value)) - -#define FLASH0_READ(dev, addr) \ - (*FLASH0_ADDR(dev, addr)) - -PRIVATE int flashCheck (flash_dev_t * dev) -{ - if (!flashLibInited) { - printf ("flashCheck: flashLib not initialized\n"); - return ERROR; - } - - if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) { - printf ("flashCheck: Bad dev parameter\n"); - return ERROR; - } - - if (!dev->found) { - printf ("flashCheck: Device %d not available\n", DEV_NO (dev)); - return ERROR; - } - - return OK; -} - -PRIVATE void flashReset (flash_dev_t * dev) -{ - PRINTF ("flashReset: dev=%d\n", DEV_NO (dev)); - - if (dev->bank == FLASH0_BANK) { - FLASH0_WRITE (dev, 0x555, 0xaa); - FLASH0_WRITE (dev, 0xaaa, 0x55); - FLASH0_WRITE (dev, 0x555, 0xf0); - } - - udelay (SLEEP_DELAY); - - PRINTF ("flashReset: done\n"); -} - -PRIVATE int flashProbe (flash_dev_t * dev) -{ - int rv, deviceID, vendorID; - - PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev)); - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto DONE; - } - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x90); - - udelay (SLEEP_DELAY); - - vendorID = FLASH0_READ (dev, 0); - deviceID = FLASH0_READ (dev, 2); - - FLASH0_WRITE (dev, 0, 0xf0); - - PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID); - - if (vendorID == dev->vendorID && deviceID == dev->deviceID) - rv = OK; - else - rv = ERROR; - - DONE: - PRINTF ("flashProbe: rv=%d\n", rv); - - return rv; -} - -PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase) -{ - int rv = ERROR; - int i, data; - int polls; - -#if 0 - PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n", - DEV_NO (dev), addr, expect, erase); -#endif - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto done; - } - - if (erase) - polls = FLASH_ERASE_SECTOR_TIMEOUT; /* Ticks */ - else - polls = FLASH_PROGRAM_POLLS; /* Loops */ - - for (i = 0; i < polls; i++) { - if (erase) - udelay (SLEEP_DELAY); - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - if (data & 0x20) { - /* - * If the 0x20 bit has come on, it could actually be because - * the operation succeeded, so check the done bit again. - */ - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n", - DEV_NO (dev), addr); - - flashReset (dev); - rv = ERROR; - goto done; - } - } - - printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n", - erase ? "erasing sector" : "programming byte", - DEV_NO (dev), addr); - - done: - -#if 0 - PRINTF ("flashWait: rv=%d\n", rv); -#endif - - return rv; -} - -/*********************************************************************** - * - * Public Flash Routines - * - ***********************************************************************/ - -STATUS flashLibInit (void) -{ - int i; - - PRINTF ("flashLibInit: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - /* - * For bank 1, probe both without and with byte swappage, - * so that this module works on both old and new Mousse boards. - */ - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - dev->swap = 0; - - if (dev->found) { - PRINTF ("\n FLASH %s[%d]: iobase=0x%x - %d sectors %d KB", - flashDev[i].name, i, flashDev[i].base, - flashDev[i].sectors, - (flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024); - - } - } - - flashLibInited = 1; - - PRINTF ("flashLibInit: done\n"); - - return OK; -} - -STATUS flashEraseSector (flash_dev_t * dev, int sector) -{ - int pos, addr; - - PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (sector < 0 || sector >= dev->sectors) { - printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector); - return ERROR; - } - - pos = FLASH_SECTOR_POS (dev, sector); - - if (dev->bank != FLASH0_BANK) { - return ERROR; - } - - addr = pos; - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x80); - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, addr, 0x30); - - return flashWait (dev, addr, 0xff, 1); -} - -/* - * Note: it takes about as long to flash all sectors together with Chip - * Erase as it does to flash them one at a time (about 30 seconds for 2 - * MB). Also since we want to be able to treat subsets of sectors as if - * they were complete devices, we don't use Chip Erase. - */ - -STATUS flashErase (flash_dev_t * dev) -{ - int sector; - - PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors); - - if (flashCheck (dev) == ERROR) - return ERROR; - - for (sector = 0; sector < dev->sectors; sector++) { - if (flashEraseSector (dev, sector) == ERROR) - return ERROR; - } - return OK; -} - -/* - * Read and write bytes - */ - -STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashRead: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n", - (int) buf, (int) FLASH0_ADDR (dev, pos), len); - - memcpy (buf, FLASH0_ADDR (dev, addr), words); - - } - PRINTF ("flashRead: rv=OK\n"); - - return OK; -} - -STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWrite: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - unsigned char tmp; - - addr = pos; - words = len; - - while (words--) { - tmp = *buf; - if (~FLASH0_READ (dev, addr) & tmp) { - printf ("flashWrite: Attempt to program 0 to 1 " - "(dev: %d, addr: 0x%x, data: 0x%x)\n", - DEV_NO (dev), addr, tmp); - return ERROR; - } - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0xa0); - FLASH0_WRITE (dev, addr, tmp); - if (flashWait (dev, addr, tmp, 0) < 0) - return ERROR; - buf++; - addr++; - } - } - - PRINTF ("flashWrite: rv=OK\n"); - - return OK; -} - -/* - * flashWritable returns true if a range contains all F's. - */ - -STATUS flashWritable (flash_dev_t * dev, int pos, int len) -{ - int addr, words; - int rv = ERROR; - - PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n", - DEV_NO (dev), pos, len); - - if (flashCheck (dev) == ERROR) - goto done; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWritable: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - goto done; - } - - if (len == 0) { - rv = 1; - goto done; - } - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - while (words--) { - if (FLASH0_READ (dev, addr) != 0xff) { - rv = 0; - goto done; - } - addr++; - } - } - - rv = 1; - - done: - PRINTF ("flashWrite: rv=%d\n", rv); - return rv; -} - - -/* - * NOTE: the below code cannot run from FLASH!!! - */ -/*********************************************************************** - * - * Flash Diagnostics - * - ***********************************************************************/ - -STATUS flashDiag (flash_dev_t * dev) -{ - unsigned int *buf = 0; - int i, len, sector; - int rv = ERROR; - - if (flashCheck (dev) == ERROR) - return ERROR; - - printf ("flashDiag: Testing device %d, " - "base: 0x%x, %d sectors @ %d kB = %d kB\n", - DEV_NO (dev), dev->base, - dev->sectors, - 1 << (dev->lgSectorSize - 10), - dev->sectors << (dev->lgSectorSize - 10)); - - len = 1 << dev->lgSectorSize; - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Erase failed\n"); - goto done; - } - printf ("%d bytes requested ...\n", len); - buf = malloc (len); - printf ("allocated %d bytes ...\n", len); - if (buf == 0) { - printf ("flashDiag: Out of memory\n"); - goto done; - } - - /* - * Write unique counting pattern to each sector - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Write sector %d\n", sector); - - for (i = 0; i < len / 4; i++) - buf[i] = sector << 24 | i; - - if (flashWrite (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Write failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - } - - /* - * Verify - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Verify sector %d\n", sector); - - if (flashRead (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Read failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - - for (i = 0; i < len / 4; i++) { - if (buf[i] != (sector << 24 | i)) { - printf ("flashDiag: Verify error " - "(dev: %d, sector: %d, offset: 0x%x)\n", - DEV_NO (dev), sector, i); - printf ("flashDiag: Expected 0x%08x, got 0x%08x\n", - sector << 24 | i, buf[i]); - - goto done; - } - } - } - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Final erase failed\n"); - goto done; - } - - rv = OK; - - done: - if (buf) - free (buf); - - if (rv == OK) - printf ("flashDiag: Device %d passed\n", DEV_NO (dev)); - else - printf ("flashDiag: Device %d failed\n", DEV_NO (dev)); - - return rv; -} - -STATUS flashDiagAll (void) -{ - int i; - int rv = OK; - - PRINTF ("flashDiagAll: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && flashDiag (dev) == ERROR) - rv = ERROR; - } - - if (rv == OK) - printf ("flashDiagAll: Passed\n"); - else - printf ("flashDiagAll: Failed because of earlier errors\n"); - - return OK; -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - flash_dev_t *dev = NULL; - - flashLibInit (); - - /* - * Provide info for FLASH (up to 960K) of Kernel Image data. - */ - dev = FLASH_DEV_BANK0_LOW; - flash_info[FLASH_BANK_KERNEL].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors; - flash_info[FLASH_BANK_KERNEL].size = - flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_KERNEL].size; - - /* - * Provide info for 512K PLCC FLASH ROM (U-Boot) - */ - dev = FLASH_DEV_BANK0_BOOT; - flash_info[FLASH_BANK_BOOT].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors; - flash_info[FLASH_BANK_BOOT].size = - flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_BOOT].size; - - - /* - * Provide info for 512K FLASH0 segment (U-Boot) - */ - dev = FLASH_DEV_BANK0_HIGH; - flash_info[FLASH_BANK_AUX].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_AUX].sector_count = dev->sectors; - flash_info[FLASH_BANK_AUX].size = - flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_AUX].size; - - - return size; -} - -/* - * Get flash device from U-Boot flash info. - */ -flash_dev_t *getFlashDevFromInfo (flash_info_t * info) -{ - int i; - - if (!info) - return NULL; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && (dev->base == info->start[0])) - return dev; - } - printf ("ERROR: notice, no FLASH mapped at address 0x%x\n", - (unsigned int) info->start[0]); - return NULL; -} - -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - int i; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found) { - if (dev->base == (unsigned int) addr) { - info->flash_id = (dev->vendorID << 16) | dev->deviceID; - info->sector_count = dev->sectors; - info->size = info->sector_count * FLASH_SECTOR_SIZE; - return dev->sectors * FLASH_SECTOR_SIZE; - } - } - } - return 0; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - unsigned int chip; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - chip = (unsigned int) info->flash_id & 0x000000ff; - - switch (chip) { - - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - - case AMD_ID_LV160B: - case FLASH_AM160LV: - case 0x49: - printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n"); - break; - - default: - printf ("Unknown Chip Type:0x%x\n", chip); - break; - } - - printf (" Size: %ld bytes in %d Sectors\n", - info->size, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE, - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -/* - * Erase a range of flash sectors. - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - flash_dev_t *dev = NULL; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - dev = getFlashDevFromInfo (info); - if (dev) { - printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - printf ("."); - if (ERROR == flashEraseSector (dev, sect)) { - printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); - return 1; - } - } - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - - flash_dev_t *dev = getFlashDevFromInfo (info); - int addr = dest - info->start[0]; - - if (!dev) - return 1; - - if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) { - printf ("ERROR: could not write to addr=0x%x, data=0x%x\n", - (unsigned int) addr, (unsigned) data); - return 1; - } - - if ((addr % FLASH_SECTOR_SIZE) == 0) - printf ("."); - - - PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n", - (unsigned) info->start[0], - (unsigned) dest, - (unsigned) (dest - info->start[0]), (unsigned) data); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - flash_dev_t *dev = getFlashDevFromInfo (info); - - if (dev) { - printf ("FLASH[%s]:", dev->name); - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - } - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mousse/flash.h b/board/mousse/flash.h deleted file mode 100644 index b7e4619..0000000 --- a/board/mousse/flash.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef FLASH_LIB_H -#define FLASH_LIB_H - -#include <common.h> - -/* PIO operations max */ -#define FLASH_PROGRAM_POLLS 100000 - -/* 10 Seconds default */ -#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ ) - -/* Flash device info structure */ -typedef struct flash_dev_s { - char name[24]; /* Bank Name */ - int bank; /* Bank 0 or 1 */ - unsigned int base; /* Base address */ - int sectors; /* Sector count */ - int lgSectorSize; /* Log2(usable bytes/sector) */ - int vendorID; /* Expected vendor ID */ - int deviceID; /* Expected device ID */ - int found; /* Set if found by flashLibInit */ - int swap; /* Set for bank 1 if byte swap req'd */ -} flash_dev_t; - -#define FLASH_MAX_POS(dev) \ - ((dev)->sectors << (dev)->lgSectorSize) - -#define FLASH_SECTOR_POS(dev, sector) \ - ((sector) << (dev)->lgSectorSize) - -/* AMD 29F040 */ -#define FLASH0_BANK 0 -#define FLASH0_VENDOR_ID 0x01 -#define FLASH0_DEVICE_ID 0x49 - -/* AMD29LV160DB */ -#define FLASH1_BANK 1 -#define FLASH1_VENDOR_ID 0x0001 -#define FLASH1_DEVICE_ID 0x2249 - -extern flash_dev_t flashDev[]; -extern int flashDevCount; - -/* - * Device pointers - * - * These must be kept in sync with the table in flashLib.c. - */ -#define FLASH_DEV_BANK0_SA0 (&flashDev[0]) -#define FLASH_DEV_BANK0_SA1 (&flashDev[1]) -#define FLASH_DEV_BANK0_SA2 (&flashDev[2]) -#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */ -#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */ -#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */ - -unsigned long flash_init(void); -int flashEraseSector(flash_dev_t *dev, int sector); -int flashErase(flash_dev_t *dev); -int flashRead(flash_dev_t *dev, int pos, char *buf, int len); -int flashWrite(flash_dev_t *dev, int pos, char *buf, int len); -int flashWritable(flash_dev_t *dev, int pos, int len); -int flashDiag(flash_dev_t *dev); -int flashDiagAll(void); - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -void flash_print_info (flash_info_t *info); -int flash_erase (flash_info_t *info, int s_first, int s_last); -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); - -/* - * Flash info indices. - */ -#define FLASH_BANK_KERNEL 0 -#define FLASH_BANK_BOOT 1 -#define FLASH_BANK_AUX 2 -#define FIRST_SECTOR 0 - -#endif /* !FLASH_LIB_H */ diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c deleted file mode 100644 index 9a70dbe..0000000 --- a/board/mousse/m48t59y.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include <common.h> -#include <rtc.h> -#include "mousse.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -int -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h deleted file mode 100644 index 2c7c092..0000000 --- a/board/mousse/m48t59y.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c deleted file mode 100644 index e1724e6..0000000 --- a/board/mousse/mousse.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * MOUSSE Board Support - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty, jfd@cs.stanford.edu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <netdev.h> -#include <asm/processor.h> -#include <timestamp.h> - -#include "mousse.h" -#include "m48t59y.h" -#include <pci.h> - - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return CONFIG_SYS_RAM_SIZE; -} - - -void get_tod (void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get (&year, &month, &day, &hour, &minute, &second); - - printf (" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ - m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */ - printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE); - get_tod (); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h deleted file mode 100644 index ce8a054..0000000 --- a/board/mousse/mousse.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MOUSSE_H -#define __MOUSSE_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -/* PORTX Device Addresses for Mousse */ - -#define PORTX_DEV_BASE 0xff000000 -#define PORTX_DEV_SIZE 0x01000000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000) -#define PLD_REG(off) (*(volatile unsigned char *) \ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f -#define PLD_REVID_B2 0x01 - -/* MPLD */ -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -/* SGS M48T59Y */ -#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000) -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) - -/* NS16552 SIO */ -#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80)) -#define N_SIO_CHANNELS 2 -#define N_COM_PORTS N_SIO_CHANNELS - -/* - * On-board Dec21143 PCI Ethernet - * Note: The PCI MBAR chosen here was used from MPC8240UM which states - * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS] - * is set, then PCI memory maps 1-1 with this address range in the - * correct byte order. - */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - -/* - * Flash Memory Layout - * - * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB - * sector SA3 is obscured by the 32 kB serial/TOD access space, and - * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC - * containing the fixed boot ROM. (If the 512 kB PLCC is - * deconfigured by jumper, this window to Flash Bank 0 becomes - * visible, but it still contains the fixed boot code and should be - * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8 - * kB), and SA2 (8 kB) are currently unused. - * - * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully - * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore - * 16-bit words only exist at addresses that are multiples of 8. All - * PROM data and control addresses must be multiplied by 8. - * - * See flashMap.c for description of flash filesystem layout. - */ - -/* - * FLASH memory address space: 8-bit wide FLASH memory spaces. - */ -#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */ -#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */ -#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */ - -#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */ -#define FLASH0_SEG1_END 0xffefffff /* 960 kB */ -#define FLASH0_SEG1_SIZE 0x000f0000 - -#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */ -#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */ -#define FLASH0_SEG2_SIZE 0x00080000 - -#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */ -#define FLASH0_SEG3_END 0xffffffff -#define FLASH0_SEG3_SIZE 0x00080000 - -/* Where Kahlua starts */ -#define FLASH_RESET_VECT 0xfff00100 - -/* - * CHRP / PREP (MAP A/B) definitions. - */ - -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -/* MPC107 (MPC8240 internal EUMBBAR mapped) */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */ - -/* - * Mousse PCI IDSEL Assignments (Device Number) - */ -#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */ -#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */ -#define MOUSSE_IDSEL_82371 15 /* That other thing */ -#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */ -#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */ -#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */ -#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */ -#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */ - -/* - * Mousse Interrupt Mapping: - * - * IRQ1 Enet (intA|intB|intC|intD) - * IRQ2 CPCI intA (See below) - * IRQ3 Local PCI slot intA|intB|intC|intD - * IRQ4 COM1 Serial port (Actually higher addressed port on duart) - * - * PCI Interrupt Mapping in CPCI chassis: - * - * | CPCI Slot - * | 1 (CPU) 2 3 4 5 6 - * -----------+--------+-------+-------+-------+-------+-------+ - * intA | X X X - * intB | X X X - * intC | X X X - * intD | X X X - */ - - -#define EPIC_VECTOR_EXT0 0 -#define EPIC_VECTOR_EXT1 1 -#define EPIC_VECTOR_EXT2 2 -#define EPIC_VECTOR_EXT3 3 -#define EPIC_VECTOR_EXT4 4 -#define EPIC_VECTOR_TM0 16 -#define EPIC_VECTOR_TM1 17 -#define EPIC_VECTOR_TM2 18 -#define EPIC_VECTOR_TM3 19 -#define EPIC_VECTOR_I2C 20 -#define EPIC_VECTOR_DMA0 21 -#define EPIC_VECTOR_DMA1 22 -#define EPIC_VECTOR_I2O 23 - - -#define INT_VEC_IRQ0 0 -#define INT_NUM_IRQ0 INT_VEC_IRQ0 -#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */ -#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */ -#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */ -#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */ - -/* Onboard DEC 21143 Ethernet */ -#define PCI_ENET_MEMADDR 0x80000000 -#define PCI_ENET_IOADDR 0x80000000 - -/* Some other PCI device */ -#define PCI_SLOT_MEMADDR 0x81000000 -#define PCI_SLOT_IOADDR 0x81000000 - -/* Promise ATA66 PCI Device (ATA controller) */ -#define PROMISE_MBAR0 0xa0000000 -#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000) -#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000) -#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000) -#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000) -#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) - -/* ATA/66 Controller offsets */ -#define CONFIG_SYS_ATA_BASE_ADDR PROMISE_MBAR0 -#define CONFIG_SYS_IDE_MAXBUS 2 /* ide0/ide1 */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 2 drives per controller */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x3000 -/* - * Definitions for accessing IDE controller registers - */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET (0x1000) - -/* - * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS - * are defined in config.h and Makefile. - * All definitions for these constants must be identical. - */ -#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */ -#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */ -#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */ -#define ROM_SIZE 0x00080000 /* 512KB ROM space */ -#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */ -#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */ - -/* - * NVRAM configuration - * NVRAM is implemented via the SGS Thomson M48T59Y - * 64Kbit (8Kbx8) Timekeeper SRAM. - * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information. - */ - -#define NV_RAM_ADRS TOD_NVRAM_BASE -#define NV_RAM_INTRVL 1 -#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT() -#define NV_RAM_WR_DSBL SYS_TOD_PROTECT() - -#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */ -#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */ -#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/ -#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */ -#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */ -#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */ -#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */ -#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */ -#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */ -#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */ -#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */ -#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/ -#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */ -#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1) -#define NV_RAM_SIZE 8176 /* NVRAM End */ - -#endif /* __MOUSSE_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c deleted file mode 100644 index a64144b..0000000 --- a/board/mousse/pci.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge - */ -#include <common.h> -#include <mpc824x.h> -#include <pci.h> - -#include "mousse.h" - -/* - * Promise ATA/66 support. - */ -#define XFER_PIO_4 0x0C /* 0000|1100 */ -#define XFER_PIO_3 0x0B /* 0000|1011 */ -#define XFER_PIO_2 0x0A /* 0000|1010 */ -#define XFER_PIO_1 0x09 /* 0000|1001 */ -#define XFER_PIO_0 0x08 /* 0000|1000 */ -#define XFER_PIO_SLOW 0x00 /* 0000|0000 */ - -/* Promise Regs */ -#define REG_A 0x01 -#define REG_B 0x02 -#define REG_C 0x04 -#define REG_D 0x08 - -void -pdc202xx_decode_registers (unsigned char registers, unsigned char value) -{ - unsigned char bit = 0, bit1 = 0, bit2 = 0; - switch(registers) { - case REG_A: - bit2 = 0; - printf(" A Register "); - if (value & 0x80) printf("SYNC_IN "); - if (value & 0x40) printf("ERRDY_EN "); - if (value & 0x20) printf("IORDY_EN "); - if (value & 0x10) printf("PREFETCH_EN "); - if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; } - printf("PIO(A) = %d ", bit2); - break; - case REG_B: - bit1 = 0;bit2 = 0; - printf(" B Register "); - if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; } - if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; } - if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; } - printf("DMA(B) = %d ", bit1 >> 5); - if (value & 0x10) printf("PIO_FORCED/PB4 "); - if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; } - printf("PIO(B) = %d ", bit2); - break; - case REG_C: - bit2 = 0; - printf(" C Register "); - if (value & 0x80) printf("DMARQp "); - if (value & 0x40) printf("IORDYp "); - if (value & 0x20) printf("DMAR_EN "); - if (value & 0x10) printf("DMAW_EN "); - - if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; } - printf("DMA(C) = %d ", bit2); - break; - case REG_D: - printf(" D Register "); - break; - default: - return; - } - printf("\n %s ", (registers & REG_D) ? "DP" : - (registers & REG_C) ? "CP" : - (registers & REG_B) ? "BP" : - (registers & REG_A) ? "AP" : "ERROR"); - for (bit=128;bit>0;bit/=2) - printf("%s", (value & bit) ? "1" : "0"); - printf("\n"); -} - -/* - * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. - */ -int -pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) -{ - unsigned short drive_conf; - int err = 0; - unsigned char drive_pci, AP, BP, CP, DP; - unsigned char TA = 0, TB = 0; - - switch (drive) { - case 0: drive_pci = 0x60; break; - case 1: drive_pci = 0x64; break; - case 2: drive_pci = 0x68; break; - case 3: drive_pci = 0x6c; break; - default: return -1; - } - - pci_read_config_word(dev, drive_pci, &drive_conf); - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - if ((AP & 0x0F) || (BP & 0x07)) { - /* clear PIO modes of lower 8421 bits of A Register */ - pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); - pci_read_config_byte(dev, (drive_pci), &AP); - - /* clear PIO modes of lower 421 bits of B Register */ - pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - } - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - - switch(speed) { - case XFER_PIO_4: TA = 0x01; TB = 0x04; break; - case XFER_PIO_3: TA = 0x02; TB = 0x06; break; - case XFER_PIO_2: TA = 0x03; TB = 0x08; break; - case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; - case XFER_PIO_0: - default: TA = 0x09; TB = 0x13; break; - } - - pci_write_config_byte(dev, (drive_pci), AP|TA); - pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - -#ifdef PDC202XX_DEBUG - pdc202xx_decode_registers(REG_A, AP); - pdc202xx_decode_registers(REG_B, BP); - pdc202xx_decode_registers(REG_C, CP); - pdc202xx_decode_registers(REG_D, DP); -#endif - return err; -} -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned int line; - - switch(PCI_DEV(dev)) { - case 0x0d: - line = 0x00000101; - break; - - case 0x0e: - default: - line = 0x00000303; - break; - } - - pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); -} - -void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned short vendorId; - unsigned int mbar0, cmd; - int bar, a; - - pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); - - if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ - /* PDC 202xx card is handled differently, it is a bootable - * device and needs all 5 MBAR's configured - */ - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d] = %dbytes\n", bar, - ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); -#endif - } - - /* Program all BAR's */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); - - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); -#endif - } - - /* Enable ROM Expansion base */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); - - /* Io enable, Memory enable, master enable */ - pci_read_config_dword(dev, PCI_COMMAND, &cmd); - cmd &= ~0xffff0000; - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config_dword(dev, PCI_COMMAND, cmd); - - /* Breath some life into the controller */ - for( a = 0; a < 4; a++) - pdc202xx_tune_chipset(dev, a, XFER_PIO_0); - } -} - -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, - pci_mousse_setup_pdc202xx }, -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, - pci_cfgfunc_config_device, {PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, - PCI_SLOT_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, -#endif - { } -}; - -struct pci_controller hose = { - config_table: pci_sandpoint_config_table, - fixup_irq: pci_mousse_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds deleted file mode 100644 index f49161c..0000000 --- a/board/mousse/u-boot.lds +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram deleted file mode 100644 index c028131..0000000 --- a/board/mousse/u-boot.lds.ram +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfff00000 , LENGTH = 512K -} - -SECTIONS -{ - _f_init = .; - PROVIDE(_f_init = .); - _f_init_rom = .; - PROVIDE(_f_init_rom = .); - - .init : { - arch/powerpc/cpu/mpc824x/start.o (.text) - *(.init) - } > ram - _init_size = SIZEOF(.init); - PROVIDE(_init_size = SIZEOF(.init)); - - ENTRY(_start) - -/* _ftext = .; - _ftext_rom = .; - _text_size = SIZEOF(.text); - */ - .text : { - *(.text) - *(.got1) - } > ram - .rodata : { *(.rodata) } > ram - .dtors : { *(.dtors) } > ram - .data : { *(.data) } > ram - .sdata : { *(.sdata) } > ram - .sdata2 : { *(.sdata2) - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .sbss : { *(.sbss) } > ram - .sbss2 : { *(.sbss2) } > ram - .bss : { *(.bss) } > ram - .debug : { *(.debug) } > ram - .line : { *(.line) } > ram - .symtab : { *(.symtab) } > ram - .shrstrtab : { *(.shstrtab) } > ram - .strtab : { *(.strtab) } > ram - /* .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - */ - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } > ram - __stop___ex_table = .; - - - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } > ram - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom deleted file mode 100644 index f162ae3..0000000 --- a/board/mousse/u-boot.lds.rom +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text) - common/board.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o (.text) - - *(.text) - - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 91ad9ce..76dfef9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1238,4 +1238,3 @@ Orphan arm arm1136 mx31 - imx31_phycore Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de Orphan arm pxa - - - lubbock - (dead address) Kyle Harris kharris@nexus-tech.net Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - -Orphan powerpc mpc824x - - mousse MOUSSE - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index adcf163..0e4d329 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MOUSSE powerpc mpc824x - 2014-04-04 rsdproto powerpc mpc8260 - 2014-04-04 RPXsuper powerpc mpc8260 - 2014-04-04 RPXClassic powerpc mpc8xx - 2014-04-04 diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h deleted file mode 100644 index e84d12f..0000000 --- a/include/configs/MOUSSE.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James F. Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the MOUSSE board. - * See also: http://www.vooha.com/ - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8240 1 -#define CONFIG_MOUSSE 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds" - -#define CONFIG_SYS_ADDR_MAP_B 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#if 1 -#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootm ffe10000" -#endif -#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" -#define CONFIG_BOOTDELAY 3 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE - - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETH_ADDR "00:10:18:10:00:06" - -#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ - -#include "../board/mousse/mousse.h" - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#endif - -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */ -#endif -#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024)) -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/ -#define FLASH_BASE0_SIZE 0x80000 /* 512K */ -#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB - 1MB - 64K FLASH0 SEG =960K - (size=0xf0000)*/ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 18432000 - -#define CONFIG_SYS_NS16550_COM1 0xFFE08080 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 - -#define CONFIG_SYS_ETH_DEV_FN 0x00 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 8 -#define CONFIG_SYS_ROMFAL 8 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 0x79 - -#ifdef INCLUDE_ECC -#define USE_ECC 1 -#else /* INCLUDE_ECC */ -#define USE_ECC 0 -#endif /* INCLUDE_ECC */ - - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC) - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ -#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */ - - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0x7f - - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory - see 8240 book for details*/ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* IBAT/DBAT Configuration */ -/* Ram: 64MB, starts at address-0, r/w instruction/data */ -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L - -/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */ -#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP) -#if 0 -#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\ - BATL_WRITETHROUGH | BATL_CACHEINHIBIT) -#else -#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) -#endif -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L - -/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L - -/* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L - - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/ -#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR -#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -/* Localizations */ -#if 0 -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 172.16.40.113 -#define CONFIG_SERVERIP 172.16.40.111 -#else -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 209.128.93.138 -#define CONFIG_SERVERIP 209.128.93.133 -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#endif /* __CONFIG_H */

Enough time has passed since this board was moved to Orphan. Remove.

- Remove include/configs/EVB64260.h - Remove the entry from boards.cfg

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

boards.cfg | 1 - include/configs/EVB64260.h | 406 --------------------------------------------- 2 files changed, 407 deletions(-) delete mode 100644 include/configs/EVB64260.h

diff --git a/boards.cfg b/boards.cfg index 76dfef9..56aca7f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1237,4 +1237,3 @@ Orphan powerpc ppc4xx - sandburst metrobox Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de Orphan arm pxa - - - lubbock - (dead address) Kyle Harris kharris@nexus-tech.net -Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h deleted file mode 100644 index 8ec75d9..0000000 --- a/include/configs/EVB64260.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber huber@mclx.com, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define CONFIG_SYS_LDSCRIPT "board/evb64260/u-boot.lds" - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#ifndef CONFIG_EVB64260_750CX -#define CONFIG_SYS_BOARD_NAME "EVB64260" -#else -#define CONFIG_SYS_BOARD_NAME "EVB64260-750CX" -#endif - -#define CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none; && " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ -#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_EVB64260_750CX -#define CONFIG_750CX -#define CONFIG_SYS_BROKEN_CL2 -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 -#define CONFIG_SYS_DEV_BASE 0xfc000000 - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -#define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ - -#define CONFIG_SYS_DEV0_PAR 0x20205093 -#define CONFIG_SYS_DEV1_PAR 0xcfcfffff -#define CONFIG_SYS_DEV2_PAR 0xc0059bd4 -#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c -#define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 - -#define CONFIG_SYS_NS16550_REG_SIZE -4 - -#define CONFIG_SYS_NS16550_CLK 3686400 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20) - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/lubbock/* - Remove include/configs/lubbock.h - Cleanup defined(CONFIG_LUBBOCK) - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

board/lubbock/Makefile | 8 - board/lubbock/flash.c | 412 ---------------------------------------------- board/lubbock/lubbock.c | 81 --------- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/net/lan91c96.h | 6 - include/configs/lubbock.h | 236 -------------------------- 7 files changed, 1 insertion(+), 744 deletions(-) delete mode 100644 board/lubbock/Makefile delete mode 100644 board/lubbock/flash.c delete mode 100644 board/lubbock/lubbock.c delete mode 100644 include/configs/lubbock.h

diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile deleted file mode 100644 index 8aa513a..0000000 --- a/board/lubbock/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lubbock.o flash.o diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c deleted file mode 100644 index f6bb22c..0000000 --- a/board/lubbock/flash.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c deleted file mode 100644 index 0daff9a..0000000 --- a/board/lubbock/lubbock.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa.h> -#include <asm/arch/pxa-regs.h> -#include <asm/arch/regs-mmc.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Configure GPIO6 and GPIO8 as OUT, AF1. */ - setbits_le32(GPDR0, (1 << 6) | (1 << 8)); - clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16)); - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 56aca7f..659b16b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1236,4 +1236,3 @@ Orphan powerpc ppc4xx - sandburst metrobox # The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de -Orphan arm pxa - - - lubbock - (dead address) Kyle Harris kharris@nexus-tech.net diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0e4d329..15c39e7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +lubbock arm pxa - 2014-04-04 Kyle Harris kharris@nexus-tech.net MOUSSE powerpc mpc824x - 2014-04-04 rsdproto powerpc mpc8260 - 2014-04-04 RPXsuper powerpc mpc8260 - 2014-04-04 diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 2f0d640..3e914ce 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -58,13 +58,7 @@ typedef unsigned long int dword;

#ifdef CONFIG_CPU_PXA25X

-#ifdef CONFIG_LUBBOCK -#define SMC_IO_SHIFT 2 -#undef USE_32_BIT - -#else #define SMC_IO_SHIFT 0 -#endif

#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))

diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h deleted file mode 100644 index 4ffe165..0000000 --- a/include/configs/lubbock.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * Configuation settings for the LUBBOCK board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ -#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ -#define CONFIG_LCD 1 -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_SHARP_LM8V31 -#endif -#define CONFIG_MMC -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x0C000000 - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_FAT - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -#define FPGA_REGS_BASE_PHYSICAL 0x08000000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00008000 -#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 -#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x0060A800 -#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 -#define CONFIG_SYS_GPDR2_VAL 0x0001C000 -#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 -#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 -#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x23F223F2 -#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 -#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 -#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 -#define CONFIG_SYS_MDREFR_VAL 0x00018018 -#define CONFIG_SYS_MDMRS_VAL 0x00000000 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) - - -/* - * FPGA Offsets - */ -#define WHOAMI_OFFSET 0x00 -#define HEXLED_OFFSET 0x10 -#define BLANKLED_OFFSET 0x40 -#define DISCRETELED_OFFSET 0x40 -#define CNFG_SWITCHES_OFFSET 0x50 -#define USER_SWITCHES_OFFSET 0x60 -#define MISC_WR_OFFSET 0x80 -#define MISC_RD_OFFSET 0x90 -#define INT_MASK_OFFSET 0xC0 -#define INT_CLEAR_OFFSET 0xD0 -#define GP_OFFSET 0x100 - -#endif /* __CONFIG_H */

Enough time has passed since this board was moved to Orphan. Remove.

- Remove board/freescale/mx31ads/* - Remove include/configs/mx31ads.h - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

board/freescale/mx31ads/Makefile | 8 - board/freescale/mx31ads/lowlevel_init.S | 268 -------------------------------- board/freescale/mx31ads/mx31ads.c | 114 -------------- board/freescale/mx31ads/u-boot.lds | 107 ------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/mx31ads.h | 189 ---------------------- 7 files changed, 1 insertion(+), 687 deletions(-) delete mode 100644 board/freescale/mx31ads/Makefile delete mode 100644 board/freescale/mx31ads/lowlevel_init.S delete mode 100644 board/freescale/mx31ads/mx31ads.c delete mode 100644 board/freescale/mx31ads/u-boot.lds delete mode 100644 include/configs/mx31ads.h

diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile deleted file mode 100644 index 5e1440d..0000000 --- a/board/freescale/mx31ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2008, Guennadi Liakhovetski lg@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mx31ads.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S deleted file mode 100644 index fcb5549..0000000 --- a/board/freescale/mx31ads/lowlevel_init.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski lg@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/imx-regs.h> - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -/* RedBoot: AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =0x43F00000 - ldr r1, =0x77777777 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =0x53F00000 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =0x43F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] - - ldr r0, =0x53F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] -.endm /* init_aips */ - -/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =0x43F04000 - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =0x00302154 - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =0x10 - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =0x0 - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ -.endm /* init_max */ - -/* RedBoot: M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =0xB8003000 - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =0x00000040 - str r0, [r1] /* M3IF control reg */ -.endm /* init_m3if */ - -/* RedBoot: To support 133MHz DDR */ -.macro init_drive_strength - /* - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits - * in SW_PAD_CTL registers - */ - - /* SDCLK */ - ldr r1, =0x43FAC200 - ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) - str r0, [r1, #0x6C] - - /* CAS */ - ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x70] - - /* RAS */ - ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) - str r0, [r1, #0x74] - - /* CS2 (CSD0) */ - ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x7C] - - /* DQM3 */ - ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x84] - - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ -pad_loop: - ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) - str r0, [r1, #0x88] - add r1, r1, #4 - subs r2, r2, #0x1 - bne pad_loop -.endm /* init_drive_strength */ - -/* CPLD on CS4 setup */ -.macro init_cs4 - ldr r0, =WEIM_BASE - ldr r1, =0x0000D843 - str r1, [r0, #0x40] - ldr r1, =0x22252521 - str r1, [r0, #0x44] - ldr r1, =0x22220A00 - str r1, [r0, #0x48] -.endm /* init_cs4 */ - -.globl lowlevel_init -lowlevel_init: - - /* Redboot initializes very early AIPS, what for? - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF */ - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - - init_aips - - init_max - - init_m3if - - init_drive_strength - - init_cs4 - - /* Image Processing Unit: */ - /* Too early to switch display on? */ - REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ - /* Clock Control Module: */ - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ - - /* PBC CPLD on CS4 */ - mov r1, #CS4_BASE - ldrh r1, [r1, #0x2] - /* Is 27MHz switch set? */ - ands r1, r1, #0x10 - - /* 532-133-66.5 */ - ldr r0, =CCM_BASE - ldr r1, =0xFF871D58 - /* PDR0 */ - str r1, [r0, #0x4] - ldreq r1, MPCTL_PARAM_532 - ldrne r1, MPCTL_PARAM_532_27 - /* MPCTL */ - str r1, [r0, #0x10] - - /* Set UPLL=240MHz, USB=60MHz */ - ldr r1, =0x49FCFE7F - /* PDR1 */ - str r1, [r0, #0x8] - ldreq r1, UPCTL_PARAM_240 - ldrne r1, UPCTL_PARAM_240_27 - /* UPCTL */ - str r1, [r0, #0x14] - /* default CLKO to 1/8 of the ARM core */ - mov r1, #0x000002C0 - add r1, r1, #0x00000006 - /* COSR */ - str r1, [r0, #0x1c] - - /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ - - /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ -/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ - /* Default: 1, 4, 12, 1 */ - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr - -MPCTL_PARAM_532: - .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) -MPCTL_PARAM_532_27: - .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) -UPCTL_PARAM_240: - .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) -UPCTL_PARAM_240_27: - .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c deleted file mode 100644 index ad89cb0..0000000 --- a/board/freescale/mx31ads/mx31ads.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski lg@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - int i; - - /* CS0: Nor Flash */ - /* - * CS0L and CS0A values are from the RedBoot sources by Freescale - * and are also equal to those used by Sascha Hauer for the Phytec - * i.MX31 board. CS0U is just a slightly optimized hardware default: - * the only non-zero field "Wait State Control" is set to half the - * default value. - */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* SPI2 */ - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); - - /* start SPI2 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); - - /* PBC setup */ - /* Enable UART transceivers also reset the Ethernet/external UART */ - readw(CS4_BASE + 4); - - writew(0x8023, CS4_BASE + 4); - - /* RedBoot also has an empty loop with 100000 iterations here - - * clock doesn't run yet */ - for (i = 0; i < 100000; i++) - ; - - /* Clear the reset, toggle the LEDs */ - writew(0xDF, CS4_BASE + 6); - - /* clock still doesn't run */ - for (i = 0; i < 100000; i++) - ; - - /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX31ADS\n"); - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds deleted file mode 100644 index 6da1d4b..0000000 --- a/board/freescale/mx31ads/u-boot.lds +++ /dev/null @@ -1,107 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/built-in.o (.text*) - arch/arm/lib/built-in.o (.text*) - net/built-in.o (.text*) - drivers/mtd/built-in.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o(.text*) - - *(.text*) - } - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/boards.cfg b/boards.cfg index 659b16b..41a48a6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1235,4 +1235,3 @@ Orphan powerpc ppc4xx - sandburst karef Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer travis.sawyer@sandburst.com # The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de -Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 15c39e7..b8fc1eb 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +mx31ads arm arm1136 - 2014-04-04 Guennadi Liakhovetski g.liakhovetski@gmx.de lubbock arm pxa - 2014-04-04 Kyle Harris kharris@nexus-tech.net MOUSSE powerpc mpc824x - 2014-04-04 rsdproto powerpc mpc8260 - 2014-04-04 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h deleted file mode 100644 index 51b1a14..0000000 --- a/include/configs/mx31ads.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski lg@denx.de - * - * Configuration settings for the MX31ADS Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0xA0000000 - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS - -/* - * Disabled for now due to build problems under Debian and a significant increase - * in the final file size: 144260 vs. 109536 Bytes. - */ -#if 0 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 -#endif - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_HARD_SPI 1 -#define CONFIG_MXC_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_MXC_GPIO - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot_addr=0xa0000000\0" \ - "uboot=mx31ads/u-boot.bin\0" \ - "kernel=mx31ads/uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_nfs; " \ - "tftpboot ${loadaddr} ${kernel}; bootm\0" \ - "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ - "protect off ${uboot_addr} 0xa003ffff; " \ - "erase ${uboot_addr} 0xa003ffff; " \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ - "setenv filesize; saveenv\0" - -#define CONFIG_CS8900 -#define CONFIG_CS8900_BASE 0xb4020300 -#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ - -/* - * The MX31ADS board seems to have a hardware "peculiarity" confirmed under - * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A - * controller inverted. The controller is capable of detecting and correcting - * this, but it needs 4 network packets for that. Which means, at startup, you - * will not receive answers to the first 4 packest, unless there have been some - * broadcasts on the network, or your board is on a hub. Reducing the ARP - * timeout from default 5 seconds to 200ms we speed up the initial TFTP - * transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING 1 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* - * JFFS2 partitions - */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" - -#endif /* __CONFIG_H */