Hi,Jeff,

I'm not sure what reset vector is. I am assuming that you are talking about CFG_RESET_ADDRESS, which I have set to 0x80000000. I'm not sure exactly what to set that to, since some board configuration files tell you to set it to a known invalid address, and then some have it set to flash base plus 0x100.

To my knowledge,reset vector is decided by Hardware Circuit of Power-on.In PowerPC,only two reset vectors are possible.One is 0x00000100,another 0xFFF00100.So we should program U-Boot code to the beginning of FLASH base address or 0xFFF00000 accordingly and U-Boot adds the 0ffset 0x100 inside.I guess your reset vector is 0x00000100.Your code at 0xFFF80000 is OK.It's not necessary to set CFG_RESET_ADDRESS.At lease,I didn't touch it.Reset vector is critical to boot a board.When power-on or hard reset,PC points at reset vector and run automatically.

Also, the speed of the flash I am using is a 70ns flash device.

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CPU: MPC855T FLASH: AMD AM29LV040B (512kB 8-bit on CS0) SDRAM: Micron MT48LC4M32 (16MB 32-bit on CS2) NVRAM: Simtek STK14C88 (32kB 8-bit on CS4)

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had the same effect. Or, could this be an issue with my BR0 and OR0 settings?

I guess so.

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Here are my BRx, ORx settings: #define FLASH_BASE_PRELIM 0xFFF80000 #define CFG_PRELIM_OR_AM 0xFFFF0000 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX | OR_EHTR)

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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | (BR_PS_8 & BR_PS_MSK) | BR_V)

I think your problems are likely with BR0 and OR0 settings.Assuming bus clock(not system clock) is 50MHz,the settings of OR0/BR0 are following:

SCY=70/20=3.5; Choose 4 for SCY; TRLX=0,SAM=0

#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_EHTR) or try #define CFG_OR_TIMING_FLASH (OR_BI | OR_SCY_4_CLK)

In addtional,pls change CFG_PRELIM_OR_AM as FLASH_BASE_PRELIM in CFG_OR0_PRELIM SETTING:

#define CFG_OR0_PRELIM (FLASH_BASE_PRELIM | CFG_OR_TIMING_FLASH)

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#define SDRAM_BASE_PRELIM 0x00000000 #define SDRAM_MAX_SIZE 0x01000000

#define CFG_OR_TIMING_SDRAM (OR_G5LA | OR_G5LS) #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )

You'd better change CFG_PRELIM_OR_AM as 0xFF000000 rather than 0xFFFF0000 as above.16MB's OR_PRELIM prefix is 0xFE000000.

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#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM BR_BA_MSK) | BR_MS_UPMA | BR_V ) #define CFG_NVRAM_BASE 0xFA000000 #define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR4_PRELIM ((CFG_NVRAM_BASE & BR_BA_MSK) | (BR_PS_8 & BR_PS_MSK) | BR_V | OR_EHTR)

If NVRAM isn't for other purpose,pls consider putting ENV in NVRAM.I am a little worry about your FLASH size.ENV will take up one sector of flash for backup if you define CFG_ENV_IN_FLASH.There isn't enough space of FLASH for you to use for application.Oop,maybe I say too much.Stop here!

Best regards,

Sam Song

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