[U-Boot] patch - arm - define SYS_CACHELINE_SIZE for mx5
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe chris.kuethe@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Matthew Starr mstarr@hedonline.com Cc: Andrej Rosano andrej@inversepath.com Cc: Stefano Babic sbabic@denx.de Cc: Chris Kuethe chris.kuethe@gmail.com Cc: Fabio Estevam festevam@gmail.com Cc: Marek Vasut marex@denx.de
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000
On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe chris.kuethe@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Matthew Starr mstarr@hedonline.com Cc: Andrej Rosano andrej@inversepath.com Cc: Stefano Babic sbabic@denx.de Cc: Chris Kuethe chris.kuethe@gmail.com Cc: Fabio Estevam festevam@gmail.com Cc: Marek Vasut marex@denx.de
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
This is correct for Cortex A8:
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Bump... can this be merged?
On Tue, Jun 2, 2015 at 4:42 PM, Fabio Estevam festevam@gmail.com wrote:
On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe chris.kuethe@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Matthew Starr mstarr@hedonline.com Cc: Andrej Rosano andrej@inversepath.com Cc: Stefano Babic sbabic@denx.de Cc: Chris Kuethe chris.kuethe@gmail.com Cc: Fabio Estevam festevam@gmail.com Cc: Marek Vasut marex@denx.de
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
This is correct for Cortex A8:
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Adding the i.MX maintaner, Stefano Babic.
Regards,
Fabio Estevam
On Mon, Jun 8, 2015 at 6:55 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
Bump... can this be merged?
On Tue, Jun 2, 2015 at 4:42 PM, Fabio Estevam festevam@gmail.com wrote:
On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe chris.kuethe@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Matthew Starr mstarr@hedonline.com Cc: Andrej Rosano andrej@inversepath.com Cc: Stefano Babic sbabic@denx.de Cc: Chris Kuethe chris.kuethe@gmail.com Cc: Fabio Estevam festevam@gmail.com Cc: Marek Vasut marex@denx.de
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
This is correct for Cortex A8:
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
-- GDB has a 'break' feature; why doesn't it have 'fix' too?
Hi Fabio, Chris,
On 09/06/2015 00:00, Fabio Estevam wrote:
Adding the i.MX maintaner, Stefano Babic.
Thanks - it was missed in my last Pr.
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Regards,
Fabio Estevam
On Mon, Jun 8, 2015 at 6:55 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
Bump... can this be merged?
On Tue, Jun 2, 2015 at 4:42 PM, Fabio Estevam festevam@gmail.com wrote:
On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe chris.kuethe@gmail.com wrote:
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe chris.kuethe@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Matthew Starr mstarr@hedonline.com Cc: Andrej Rosano andrej@inversepath.com Cc: Stefano Babic sbabic@denx.de Cc: Chris Kuethe chris.kuethe@gmail.com Cc: Fabio Estevam festevam@gmail.com Cc: Marek Vasut marex@denx.de
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
This is correct for Cortex A8:
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
-- GDB has a 'break' feature; why doesn't it have 'fix' too?
participants (3)
-
Chris Kuethe -
Fabio Estevam -
Stefano Babic