[U-Boot] [PATCH v3] Tegra: DT: add device tree binding doc for QSPI
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
Signed-off-by: Tom Warren twarren@nvidia.com --- Changes in v2: - based it more on kernel's nvidia,tegra114-spi.txt binding - changes based on prelim review by swarren@nvidia.com Changes in v3: - renamed to 'nvidia,tegra210-qspi.txt' to match kernel bindings - more changes based on review from swarren@nvidia.com
Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt new file mode 100644 index 0000000..fe1558f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt @@ -0,0 +1,42 @@ +NVIDIA Tegra QSPI controller. + +Required properties: +- compatible : for Tegra210, must contain "nvidia,tegra210-qspi". +- reg: Should contain QSPI registers location and length. +- interrupts: Should contain QSPI interrupt. +- clock-names : Must include the following entries: + - qspi +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the following entries: + - qspi +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + +Optional properties: +- dmas : Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names : Must include the following entries: + - rx + - tx + +Recommended properties: +- spi-max-frequency: Definition as per spi-bus.txt + +Example: + +spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = <0 10 0x04>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 211>; + clock-names = "qspi"; + resets = <&tegra_car 211>; + reset-names = "qspi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; +};
On 10/26/2015 02:34 PM, Tom Warren wrote:
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
+- clock-names : Must include the following entries:
- qspi
+- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
- qspi
+- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
+Optional properties: +- dmas : Must contain an entry for each entry in clock-names.
- See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
- rx
- tx
Eventually, we should have a property that describes the SPI bus width (x1, x2, x4 I assume). However, we can assume that unless otherwise specified, the width is x1, and add a property to specify the width later as/when we need it if you want.
Stephen,
-----Original Message----- From: Stephen Warren [mailto:swarren@wwwdotorg.org] Sent: Monday, October 26, 2015 2:04 PM To: Tom Warren TWarren@nvidia.com Cc: u-boot@lists.denx.de; Stephen Warren swarren@nvidia.com; tomcwarren3959@gmail.com; jteki@openedev.com; robh+dt@kernel.org; pawel.moll@arm.com; mark.rutland@arm.com; ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Thierry Reding treding@nvidia.com; linux- tegra@vger.kernel.org; Alex Courbot acourbot@nvidia.com; linux-arm- kernel@lists.infradead.org Subject: Re: [PATCH v3] Tegra: DT: add device tree binding doc for QSPI
On 10/26/2015 02:34 PM, Tom Warren wrote:
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
+- clock-names : Must include the following entries:
- qspi
+- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
- qspi
+- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
OK. I assume 'clock-names', then 'clocks' since 'clocks' references clock-names.
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
I thought I had it, but may have dropped it. What exactly is the URL of the devicetree mailing list? devicetree-discuss@lists.ozlabs.org? or devicetree@vger.kernel.org?
+Optional properties: +- dmas : Must contain an entry for each entry in clock-names.
- See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
- rx
- tx
Eventually, we should have a property that describes the SPI bus width (x1, x2, x4 I assume). However, we can assume that unless otherwise specified, the width is x1, and add a property to specify the width later as/when we need it if you want.
Tom -- nvpublic
On 10/26/2015 03:36 PM, Tom Warren wrote:
Stephen Warren wrote at Monday, October 26, 2015 2:04 PM:
On 10/26/2015 02:34 PM, Tom Warren wrote:
This patch adds the device tree binding doc for the Tegra QSPI controller on Tegra210.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra210-qspi.txt
+- clock-names : Must include the following entries:
- qspi
+- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
- qspi
+- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
Let's keep clocks and clock-names next to each-other in the doc. I don't know why they aren't in the eixsting Tegra SPI doc.
OK. I assume 'clock-names', then 'clocks' since 'clocks' references clock-names.
That sounds correct.
With this issue fixed, this patch looks good to me.
Note: I don't see the devicetree mailing list in the CC list. You should probably replace the U-Boot mailing list with it.
I thought I had it, but may have dropped it. What exactly is the URL of the devicetree mailing list? devicetree-discuss@lists.ozlabs.org? or devicetree@vger.kernel.org?
devicetree@vger.kernel.org
(See the "OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" in "MAINTAINERS", or the output of ./scripts/get_maintainers.pl)
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