--- The patch is to be done, It is only giving the context why move the definition of fsl_law from .c to .h.

Makefile | 13 +- board/freescale/mpc8572ds/config.mk | 5 + board/freescale/mpc8572ds/nand_boot.c | 75 ++++ board/freescale/mpc8572ds/u-boot-nand.lds | 140 ++++++++ cpu/mpc85xx/nand_init.c | 102 ++++++ cpu/mpc85xx/nand_start.S | 469 +++++++++++++++++++++++++ cpu/mpc85xx/start.S | 3 + drivers/misc/fsl_law.c | 9 +- include/asm-ppc/fsl_law.h | 2 + include/configs/MPC8572DS.h | 64 ++++- nand_spl/board/freescale/mpc8572ds/Makefile | 110 ++++++ nand_spl/board/freescale/mpc8572ds/u-boot.lds | 56 +++ 12 files changed, 1040 insertions(+), 8 deletions(-) create mode 100644 board/freescale/mpc8572ds/nand_boot.c create mode 100644 board/freescale/mpc8572ds/u-boot-nand.lds create mode 100644 cpu/mpc85xx/nand_init.c create mode 100644 cpu/mpc85xx/nand_start.S create mode 100644 nand_spl/board/freescale/mpc8572ds/Makefile create mode 100644 nand_spl/board/freescale/mpc8572ds/u-boot.lds

diff --git a/Makefile b/Makefile index d6abb4d..7af02f8 100644 --- a/Makefile +++ b/Makefile @@ -2364,8 +2364,17 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale

-MPC8572DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale +MPC8572DS_config \ +MPC8572DS_NAND_config: unconfig + @if [ "$(findstring _NAND_,$@)" ] ; then \ + $(XECHO) -n "...NAND..." ; \ + echo "TEXT_BASE = 0x01001000" > $(obj)board/freescale/mpc8572ds/config.tmp ; \ + echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale + @if [ "$(findstring _NAND_,$@)" ] ; then \ + echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \ + fi ;

PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 5b32186..a5bfcae 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -23,6 +23,11 @@ # # mpc8572ds board # + +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/mpc8572ds/nand_boot.c b/board/freescale/mpc8572ds/nand_boot.c new file mode 100644 index 0000000..1fb0acd --- /dev/null +++ b/board/freescale/mpc8572ds/nand_boot.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/io.h> + +unsigned long get_bus_clk(void); +void tlb_set(u32 mas0, u32 mas1, u32 mas2, u32 mas3); +phys_size_t fixed_sdram (void); + +DECLARE_GLOBAL_DATA_PTR; + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c); +} + +void board_init_f(ulong bootflag) +{ + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + u32 mas0, mas1, mas2, mas3; + + /* init serial port */ + NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), + get_bus_clk() / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + + /* set TLB1[8] for DDR mapping */ + mas0 = FSL_BOOKE_MAS0(1, 8, 0); + mas1 = FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G); + mas2 = FSL_BOOKE_MAS2(0, 0); + mas3 = FSL_BOOKE_MAS3(0, 0, MAS3_SX | MAS3_SW | MAS3_SR); + tlb_set(mas0, mas1, mas2, mas3); + + /* set LAW0 for DDR access */ + out_be32(&ecm->lawbar0, 0); + out_be32(&ecm->lawar0, LAWAR_EN | (LAW_TRGT_IF_DDR << 20) + | LAW_SIZE_512M); + /* init DDR memory controller */ + fixed_sdram(); + + /* relocate the first bootstrap */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} diff --git a/board/freescale/mpc8572ds/u-boot-nand.lds b/board/freescale/mpc8572ds/u-boot-nand.lds new file mode 100644 index 0000000..165a956 --- /dev/null +++ b/board/freescale/mpc8572ds/u-boot-nand.lds @@ -0,0 +1,140 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc85xx/nand_init.c b/cpu/mpc85xx/nand_init.c new file mode 100644 index 0000000..5bcf224 --- /dev/null +++ b/cpu/mpc85xx/nand_init.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc85xx.h> +#include <asm/fsl_law.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void cpu_early_init_f(void) +{ + int i; + + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + /* clear initial global data */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; +} + +void cpu_init_f(void) +{ + + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + uint sys_clk, plat_ratio, bus_clk; + + sys_clk = CONFIG_SYS_CLK_FREQ; + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + gd->bus_clk = bus_clk; + + /* + * setup LAW1 for the NAND access. + * The 85xx has one default 8MB boot window(0xff800000-0xffffffff) + * we are using the default boot window to run the code, so + * the CONFIG_SYS_NAND_BASE must be between 0xff800000-0xffffffff. + * otherwise, it will broken. + */ + out_be32(&ecm->lawbar1, (CONFIG_SYS_NAND_BASE >> 12) & 0xfffff); + out_be32(&ecm->lawar1, LAWAR_EN | (LAW_TRGT_IF_LBC << 20) + | LAW_SIZE_256K); +#ifdef CONFIG_MPC8572 + /* + * For 8572, the reset value of LCRR = 0x80000008 at NOR boot, + * however, the reset LCRR = 0x80000004 at NAND boot, + * make the NAND boot case same as NOR boot at here. + */ + out_be32(&lbc->lcrr, 0x80000008); + asm volatile("isync"); +#endif + /* + * update BR0/OR0 from default to desired value. after update them, + * we must use the BR0[BA] to access the NAND flash. + */ +#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif +} + +/* + * get ccb bus clock frquency + */ +unsigned long get_bus_clk(void) +{ + return gd->bus_clk; +} + +/* + * get timebase clock frequency + */ +unsigned long get_tbclk(void) +{ + return (gd->bus_clk + 4UL) / 8UL; +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/cpu/mpc85xx/nand_start.S b/cpu/mpc85xx/nand_start.S new file mode 100644 index 0000000..8de1b66 --- /dev/null +++ b/cpu/mpc85xx/nand_start.S @@ -0,0 +1,469 @@ +/* + * Copyright (C) 2004, 2007-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2003 Motorola,Inc. + * + * nand_start.S is the start.S of the first stage bootstrap in + * NAND boot case. + * It set up the minimum cache, stack, CCSR, TLB and LAW entries for + * itself and the second stage u-boot. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot Startup Code for Freescale 85xx PowerPC based Embedded Boards + * + * The processor starts at 0xfffffffc and the code is first executed in the + * last 4K page(0xfffff000-0xffffffff) in flash/rom. + * + */ + +#include <config.h> +#include <mpc85xx.h> +#include <version.h> + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(__bss_start) + GOT_ENTRY(_end) + END_GOT + +/* + * e500 Startup -- after reset only the last 4KB of the effective + * address space is mapped in the MMU L2 TLB1 Entry0. we put the + * first stage boot code at THIS LAST page and basically does six + * things: clear some registers, update CCSRBAR, set up stack, TLB + * entries, LAW and random memory for the second stage boot code. + */ + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .align 4 + .globl _start_e500 +/* + * We come from the relative jump instruction (b _start_e500) at + * 0xfffffffc, so we run at 0xfffffxxx, the default TLB1[0] 4K + * page space after core reset. + */ +_start_e500: + +/* clear registers, min e500 init */ + + /* clear machine status register */ + li r0,0 + mtmsr r0 + isync + + /* clear HID1, enable TB */ + mtspr HID1, r0 + lis r0,HID0_EMCP@h /* Enable machine check */ + ori r0,r0,HID0_TBEN@l /* Enable Timebase */ + mtspr HID0,r0 + + /* L1 cache invalidate */ + li r0,2 + mtspr L1CSR0,r0 /* invalidate d-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ + + mfspr r1,DBSR + mtspr DBSR,r1 /* clear all valid bits */ + + /* enable L1 cache */ + lis r0,L1CSR0_CPE@H /* enable parity */ + ori r0,r0,L1CSR0_DCE + mtspr L1CSR0,r0 /* enable L1 Dcache */ + isync + mtspr L1CSR1,r0 /* enable L1 Icache */ + isync + msync + + /* clear and set up some registers */ + li r0,0x0000 + lis r1,0xffff + mtspr DEC,r0 /* prevent dec exceptions */ + mttbl r0 /* prevent fit & wdt exceptions */ + mttbu r0 + mtspr TSR,r1 /* clear all timer exception status */ + mtspr TCR,r0 /* disable all */ + mtspr ESR,r0 /* clear exception syndrome register */ + mtspr MCSR,r0 /* machine check syndrome register */ + mtxer r0 /* clear integer exception register */ + +/* create TLB1[15] 4K AS=0 mapping for the CCSRBAR_DEFAULT */ + lis r3,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r3,r3,FSL_BOOKE_MAS0(1, 15, 0)@l + + /* valid, IPROT, TID=0, AS=0, TSIZE=4K */ + lis r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4K)@h + ori r4,r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4K)@l + + /* EPN=CCSRBAR_DEFAULT, *I*G* */ + lis r5,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))@h + ori r5,r5,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))@l + + /* RPN=CCSRBAR_DEFAULT */ + lis r6,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r6,r6,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + bl tlb_set + +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) + /* Special sequence needed to update CCSRBAR itself */ + lis r4,CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r4,r4,CONFIG_SYS_CCSRBAR_DEFAULT@l + + lis r5,CONFIG_SYS_CCSRBAR@h + ori r5,r5,CONFIG_SYS_CCSRBAR@l + srwi r6,r5,12 + stw r6,0(r4) + isync + + lis r5, 0xffff + ori r5,r5, 0xf000 + lwz r5,0(r5) + isync +#endif + +/* create TLB0 mapping to the boot window */ + lis r3,FSL_BOOKE_MAS0(0, 0, 0)@h + ori r3,r3,FSL_BOOKE_MAS0(0, 0, 0)@l + + /* valid, IPROT=n/a, TID=0, AS=1, TSIZE=4K */ + lis r4,FSL_BOOKE_MAS1(1, 0, 0, 1, BOOKE_PAGESZ_4K)@h + ori r4,r4,FSL_BOOKE_MAS1(1, 0, 0, 1, BOOKE_PAGESZ_4K)@l + + /* EPN=TEXT_BASE & 0xfffff000, *I*G* */ + lis r5,FSL_BOOKE_MAS2(TEXT_BASE & 0xfffff000, (MAS2_I|MAS2_G))@h + ori r5,r5,FSL_BOOKE_MAS2(TEXT_BASE & 0xfffff000, (MAS2_I|MAS2_G))@l + + /* RPN=0xfffffxxx */ + lis r6,FSL_BOOKE_MAS3(0xfffff000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r6,r6,FSL_BOOKE_MAS3(0xfffff000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + bl tlb_set + + lis r3,(MSR_IS|MSR_DS)@h + ori r3,r3,(MSR_IS|MSR_DS)@l + lis r4,switch_to_as1@h + ori r4,r4,switch_to_as1@l + + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi + +switch_to_as1: + +/* + * we run at TEXT_BASE (eg: 0xfff00xxx), the TLB0 4K AS=1 page space. + */ + +/* overwrite the default 4K AS=0 TLB1[0], we set it for SYS_CCSRBAR with 1M */ + lis r3,FSL_BOOKE_MAS0(1, 0, 0)@h + ori r3,r3,FSL_BOOKE_MAS0(1, 0, 0)@l + + /* valid, IPROT, TID=0, AS=0, TSIZE=1M */ + lis r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h + ori r4,r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l + + /* EPN=SYS_CCSRBAR, *I*G* */ + lis r5,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h + ori r5,r5,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l + + /* RPN=SYS_CCSRBAR */ + lis r6,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r6,r6,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + bl tlb_set + +/* overwrite CCSRBAR_DEFAULT 4K TLB1[15], we set it for boot window with 256K */ + lis r3,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r3,r3,FSL_BOOKE_MAS0(1, 15, 0)@l + + /* valid, IPROT, TID=0, AS=0, TSIZE=256K */ + lis r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h + ori r4,r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l + + /* EPN=TEXT_BASE align to 256K, *I*G* */ + lis r5,FSL_BOOKE_MAS2(TEXT_BASE & 0xfffc0000, (MAS2_I|MAS2_G))@h + ori r5,r5,FSL_BOOKE_MAS2(TEXT_BASE & 0xfffc0000, (MAS2_I|MAS2_G))@l + + /* RPN=TEXT_BASE & 0xfffc0000 + * The 85xx has one default 8MB boot LAW 0xff800000->0xffffffff, + * we will create the new boot LAW (base=NAND_BASE, size=256K) for NAND + * to override the default boot LAW in nand_init.c. we assume + * TEXT_BASE = NAND_BASE, so there is one limitation: + * The CONFIG_NAND_BASE *MUST* be in the 0xff800000->0xffffffff. + */ + lis r6,FSL_BOOKE_MAS3(TEXT_BASE & 0xfffc0000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r6,r6,FSL_BOOKE_MAS3(TEXT_BASE & 0xfffc0000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + bl tlb_set + +/* + * switch running space from TEXT_BASE (eg: 0xfff00xxx) TLB0 4K AS=1 + * page space to TEXT_BASE TLB1[15] AS=0 256K page space. + */ + lis r3,switch_to_as0@h + ori r3,r3,switch_to_as0@l + li r4,0 + + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + rfi + +switch_to_as0: + +/* don't need AS=1 mapping any more, invalidate the TLB0 */ + li r0,4 + mtspr SPRN_MMUCSR0, r0 + +/* make the CCSRBAR updated */ + lis r3,CONFIG_SYS_CCSRBAR@h + lwz r4,CONFIG_SYS_CCSRBAR@l(r3) + isync + +/* create TLB1[14] mapping to the stack */ + lis r3,FSL_BOOKE_MAS0(1, 14, 0)@h + ori r3,r3,FSL_BOOKE_MAS0(1, 14, 0)@l + + /* valid, IPROT, TID=0, AS=0, TSIZE=16K */ + lis r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)@h + ori r4,r4,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)@l + + lis r5,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h + ori r5,r5,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l + + lis r6,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r6,r6,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + bl tlb_set + +/* L1 data cache is used for initial RAM */ + + /* allocate Initial RAM in data cache */ + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + mfspr r4,L1CFG0 + andi. r4,r4,0x1ff + /* The initial RAM size is half of data cache + * r4=cache size * 1024 / (2 * L1 line size) + */ + slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) + mtctr r4 + li r0,0 +1: + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE + bdnz 1b + +/* Setup the stack in L1 dcache */ + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l + + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0,RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + +/* + * We run at AS=0 space, leave three TLB entries: + * TLB1[0] - 1M CCSRBAR, TLB1[15] - 256K boot window + * TLB1[14] - 16K stack on L1 cache. + */ + GET_GOT /* Initialize GOT access */ + + bl cpu_early_init_f + bl cpu_init_f + bl board_init_f + + .global tlb_set +tlb_set: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 + isync + msync + tlbwe + blr + +/* + * void relocate_code (addr_sp, gd, dest) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1,r3 /* set new stack pointer */ + mr r9,r4 /* save copy of global data pointer */ + mr r10,r5 /* save copy of destination address */ + + mr r3,r5 /* destination address */ + lis r4,CONFIG_SYS_MONITOR_BASE@h /* source address */ + ori r4,r4,CONFIG_SYS_MONITOR_BASE@l + lwz r5,GOT(__bss_start) + sub r5,r5,r4 + li r6,CONFIG_SYS_CACHELINE_SIZE /* cache line size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + * + Destination Address + * + * Offset: + */ + sub r15,r10,r4 + + /* First our own GOT */ + add r14,r14,r15 + /* then the one used by the C code */ + add r30,r30,r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* in place copy is not necessary */ + beq 7f /* protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0,r10,in_ram - _start + _START_OFFSET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0,r3,r4 + beq 6f + + li r0,0 +5: + stw r0,0(r3) + addi r3,r3,4 + cmplw 0,r3,r4 + bne 5b +6: + mr r3,r9 /* global data pointer */ + mr r4,r10 /* destination address */ + bl board_init_r +/* + * jump to board_init_r, run at AS=0 space, leave + * four TLB entries: + * TLB1[0] - 1M CCSRBAR, TLB1[15] - 256K NAND FLASH + * TLB1[14] - 16K stack on L1 cache, TLB1[8] - DDR memory + * and two LAW entries: + * LAW0 - DDR, LAW1 - NAND FLASH to the second u-boot. + */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 651ff1c..31cf729 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -183,6 +183,7 @@ _start_e500: mtspr DBCR0,r0 #endif

+#ifndef CONFIG_NAND_U_BOOT /* create a temp mapping in AS=1 to the boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l @@ -254,6 +255,8 @@ switch_as: addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b

+#endif + /* Jump out the last 4K page and continue to 'normal' start */ #ifdef CONFIG_SYS_RAMBOOT b _start_cont diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 44c9e91..9b18ca6 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -29,7 +29,6 @@

DECLARE_GLOBAL_DATA_PTR;

-#define LAWAR_EN 0x80000000 /* number of LAWs in the hw implementation */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) @@ -166,7 +165,13 @@ void init_laws(void) int i;

gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); - +#ifdef CONFIG_NAND_U_BOOT + /* + * keep the LAW0 reserved as DDR at NAND boot case + * we init already the LAW0 for DDR in SPL nand stage + */ + gd->used_laws |= (1 << 0); +#endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 5bba08d..18eb9d6 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -9,6 +9,8 @@ #define SET_LAW(a, sz, trgt) \ { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }

+#define LAWAR_EN 0x80000000 + enum law_size { LAW_SIZE_4K = 0xb, LAW_SIZE_8K, diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 3365827..7776d7b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -60,7 +60,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_CLK_FREQ 100000000 +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#endif #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq @@ -95,8 +99,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE + +#ifdef CONFIG_NAND_U_BOOT +#undef CONFIG_SPD_EEPROM +#undef CONFIG_DDR_SPD +#else #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD +#endif + #undef CONFIG_DDR_DLL

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER @@ -164,8 +175,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE

-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_FLASH_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR0_PRELIM 0xf8000ff7

#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 @@ -182,6 +193,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);

#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */

+#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -247,7 +262,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 +#ifdef CONFIG_NAND_SPL #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#else +#define CONFIG_SYS_INIT_RAM_ADDR 0x07f00000 +#endif #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ @@ -257,7 +276,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */

+#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#else #define CONFIG_SYS_NAND_BASE 0xffa00000 +#endif + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ @@ -285,8 +309,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR)

-#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* CS0=NAND at NAND boot */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM +#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* CS2=NOR at NAND boot */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* CS0=NOR at NOR boot */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* CS2=NAND at NOR boot */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM +#endif

#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -308,6 +341,19 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | BR_V) /* valid */ #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */

+/* NAND boot + * we load the first stage and second stage binary + * from NAND to RAM, so the RAM will have the 1st + * and 2nd boot code. then, code jump to _START to + * excute the second stage boot. + */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x4000 /* the first stage 16KB bootstrap */ +#define CONFIG_SYS_NAND_U_BOOT_START 0x01000000 /* the second stage u-boot */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 /* offset we load u-boot-nand.bin from NAND */ +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_NAND_U_BOOT_START \ + - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (CONFIG_SYS_NAND_SPL_SIZE + (512 << 10)) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

/* Serial Port - controlled on board with jumper J8 @@ -507,6 +553,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Environment */ +#if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE +#elif !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 @@ -515,6 +566,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x2000) +#define CONFIG_ENV_SIZE 0x2000 +#endif

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile new file mode 100644 index 0000000..6ed1fd5 --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -0,0 +1,110 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +# we should set TEXT_BASE=CONFIG_SYS_NAND_BASE +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff04000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL +PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + +SOBJS = nand_start.o resetvec.o ticks.o +COBJS = nand_boot_fsl_elbc.o ns16550.o nand_init.o fixed-sdram.o nand_boot.o \ + time.o cache.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)nand_start.S: + ln -sf $(SRCTREE)/cpu/mpc85xx/nand_start.S $(obj)nand_start.S + +$(obj)resetvec.S: + ln -sf $(SRCTREE)/cpu/mpc85xx/resetvec.S $(obj)resetvec.S + +$(obj)nand_init.c: + ln -sf $(SRCTREE)/cpu/mpc85xx/nand_init.c $(obj)nand_init.c + +$(obj)nand_boot_fsl_elbc.c: + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)fixed-sdram.c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/fixed-sdram.c $(obj)fixed-sdram.c + +$(obj)nand_boot.c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + +$(obj)ns16550.c: + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)time.c: + ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c + +$(obj)ticks.S: + ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S + +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8572ds/u-boot.lds b/nand_spl/board/freescale/mpc8572ds/u-boot.lds new file mode 100644 index 0000000..877812e --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + .resetvec 0xfff00ffc : { + *(.resetvec) + } = 0xffff + + .text : { + nand_start.o (.text) + *(.text*) + . = ALIGN(16); + *(.rodata*) + *(.eh_frame) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff01000, "NAND bootstrap too big");