While porting from the Marvell source, I introduced a bug by misplacing the parenthesis. This patch fixes this issue.

Signed-off-by: Stefan Roese sr@denx.de ---

arch/mips/mach-octeon/cvmx-bootmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c b/arch/mips/mach-octeon/cvmx-bootmem.c index 4b10effefb7d..12695df9bca6 100644 --- a/arch/mips/mach-octeon/cvmx-bootmem.c +++ b/arch/mips/mach-octeon/cvmx-bootmem.c @@ -283,8 +283,8 @@ static int __cvmx_bootmem_check_version(int exact_match) int major_version;

major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version); - if (major_version > 3 || - (exact_match && major_version) != exact_match) { + if ((major_version > 3) || + (exact_match && major_version != exact_match)) { debug("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: 0x%llx\n", major_version, (int)CVMX_BOOTMEM_DESC_GET_FIELD(minor_version),

This patch adds the PCI remote console feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-console" tool on host PC's to communicate with the PCIe target.

Signed-off-by: Stefan Roese sr@denx.de Cc: Aaron Williams awilliams@marvell.com Cc: Chandrakala Chavva cchavva@marvell.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---

drivers/serial/Kconfig | 13 + drivers/serial/Makefile | 1 + drivers/serial/serial_octeon_pcie_console.c | 365 ++++++++++++++++++++ 3 files changed, 379 insertions(+) create mode 100644 drivers/serial/serial_octeon_pcie_console.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 24413d14f9ce..d6fe1dc7b1a8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -788,6 +788,19 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200).

+config OCTEON_SERIAL_PCIE_CONSOLE + bool "MIPS Octeon PCIe remote console" + depends on ARCH_OCTEON + depends on (DM_SERIAL && DM_STDIO) + select SYS_STDIO_DEREGISTER + select SYS_CONSOLE_IS_IN_ENV + select CONSOLE_MUX + help + This driver supports remote console over the PCIe bus when the + Octeon is running in PCIe target mode. The host program + 'oct-remote-console' can be used to connect to this console. + The console number will likely be 0 or 1. + config OMAP_SERIAL bool "Support for OMAP specific UART" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 92bcb30b8509..4900e9cb27dc 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_OCTEON_SERIAL_PCIE_CONSOLE) += serial_octeon_pcie_console.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o diff --git a/drivers/serial/serial_octeon_pcie_console.c b/drivers/serial/serial_octeon_pcie_console.c new file mode 100644 index 000000000000..c76e787d0308 --- /dev/null +++ b/drivers/serial/serial_octeon_pcie_console.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + * Copyright (C) 2021 Stefan Roese sr@denx.de + */ + +#include <dm.h> +#include <dm/uclass.h> +#include <errno.h> +#include <input.h> +#include <iomux.h> +#include <log.h> +#include <serial.h> +#include <stdio_dev.h> +#include <string.h> +#include <watchdog.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <mach/cvmx-regs.h> +#include <mach/cvmx-bootmem.h> + +#define DRIVER_NAME "pci-console" +#define OCTEONTX_PCIE_CONSOLE_NAME_LEN 16 + +/* Current versions */ +#define OCTEON_PCIE_CONSOLE_MAJOR_VERSION 1 +#define OCTEON_PCIE_CONSOLE_MINOR_VERSION 0 + +#define OCTEON_PCIE_CONSOLE_BLOCK_NAME "__pci_console" + +/* + * Structure that defines a single console. + * Note: when read_index == write_index, the buffer is empty. + * The actual usable size of each console is console_buf_size -1; + */ +struct octeon_pcie_console { + u64 input_base_addr; + u32 input_read_index; + u32 input_write_index; + u64 output_base_addr; + u32 output_read_index; + u32 output_write_index; + u32 lock; + u32 buf_size; +}; + +/* + * This is the main container structure that contains all the information + * about all PCI consoles. The address of this structure is passed to various + * routines that operation on PCI consoles. + */ +struct octeon_pcie_console_desc { + u32 major_version; + u32 minor_version; + u32 lock; + u32 flags; + u32 num_consoles; + u32 pad; + /* must be 64 bit aligned here... */ + /* Array of addresses of octeon_pcie_console_t structures */ + u64 console_addr_array[0]; + /* Implicit storage for console_addr_array */ +}; + +struct octeon_pcie_console_priv { + struct octeon_pcie_console *console; + int console_num; + bool console_active; +}; + +/* Flag definitions for read/write functions */ +enum { + /* + * If set, read/write functions won't block waiting for space or data. + * For reads, 0 bytes may be read, and for writes not all of the + * supplied data may be written. + */ + OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0, +}; + +static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx) +{ + if (rd_idx >= buffer_size || wr_idx >= buffer_size) + return -1; + + return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size; +} + +static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx) +{ + if (rd_idx >= buffer_size || wr_idx >= buffer_size) + return -1; + + return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx); +} + +static int buffer_read_avail(struct udevice *dev, unsigned int console_num) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + + avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index); + if (avail >= 0) + return avail; + + return 0; +} + +static int octeon_pcie_console_read(struct udevice *dev, + unsigned int console_num, char *buffer, + int buffer_size, u32 flags) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + char *buf_ptr; + int bytes_read; + int read_size; + + buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr); + + avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index); + if (avail < 0) + return avail; + + if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) { + /* Wait for some data to be available */ + while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index))) { + mdelay(10); + WATCHDOG_RESET(); + } + } + + bytes_read = 0; + + /* Don't overflow the buffer passed to us */ + read_size = min_t(int, avail, buffer_size); + + /* Limit ourselves to what we can input in a contiguous block */ + if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size) + read_size = cons_ptr->buf_size - cons_ptr->input_read_index; + + memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size); + cons_ptr->input_read_index = + (cons_ptr->input_read_index + read_size) % cons_ptr->buf_size; + bytes_read += read_size; + + /* Mark the PCIe console to be active from now on */ + if (bytes_read) + priv->console_active = true; + + return bytes_read; +} + +static int octeon_pcie_console_write(struct udevice *dev, + unsigned int console_num, + const char *buffer, + int bytes_to_write, u32 flags) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + char *buf_ptr; + int bytes_written; + + buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr); + bytes_written = 0; + while (bytes_to_write > 0) { + avail = buffer_free_bytes(cons_ptr->buf_size, + cons_ptr->output_write_index, + cons_ptr->output_read_index); + + if (avail > 0) { + int write_size = min_t(int, avail, bytes_to_write); + + /* + * Limit ourselves to what we can output in a contiguous + * block + */ + if (cons_ptr->output_write_index + write_size >= + cons_ptr->buf_size) { + write_size = cons_ptr->buf_size - + cons_ptr->output_write_index; + } + + memcpy(buf_ptr + cons_ptr->output_write_index, + buffer + bytes_written, write_size); + /* + * Make sure data is visible before changing write + * index + */ + CVMX_SYNCW; + cons_ptr->output_write_index = + (cons_ptr->output_write_index + write_size) % + cons_ptr->buf_size; + bytes_to_write -= write_size; + bytes_written += write_size; + } else if (avail == 0) { + /* + * Check to see if we should wait for room, or return + * after a partial write + */ + if (flags & OCT_PCI_CON_FLAG_NONBLOCK) + goto done; + + WATCHDOG_RESET(); + mdelay(10); /* Delay if we are spinning */ + } else { + bytes_written = -1; + goto done; + } + } + +done: + return bytes_written; +} + +static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles, + int buffer_size) +{ + struct octeon_pcie_console_desc *cons_desc_ptr; + struct octeon_pcie_console *cons_ptr; + s64 addr; + u64 avail_addr; + int alloc_size; + int i; + + /* Compute size required for pci console structure */ + alloc_size = num_consoles * + (buffer_size * 2 + sizeof(struct octeon_pcie_console) + + sizeof(u64)) + sizeof(struct octeon_pcie_console_desc); + + /* + * Allocate memory for the consoles. This must be in the range + * addresssible by the bootloader. + * Try to do so in a manner which minimizes fragmentation. We try to + * put it at the top of DDR0 or bottom of DDR2 first, and only do + * generic allocation if those fail + */ + addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, + OCTEON_DDR0_SIZE - alloc_size - 128, + OCTEON_DDR0_SIZE, 128, + OCTEON_PCIE_CONSOLE_BLOCK_NAME, + CVMX_BOOTMEM_FLAG_END_ALLOC); + if (addr < 0) { + addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, + 0x1fffffff, 128, + OCTEON_PCIE_CONSOLE_BLOCK_NAME, + CVMX_BOOTMEM_FLAG_END_ALLOC); + } + if (addr < 0) + return 0; + + cons_desc_ptr = cvmx_phys_to_ptr(addr); + + /* Clear entire alloc'ed memory */ + memset(cons_desc_ptr, 0, alloc_size); + + /* Initialize as locked until we are done */ + cons_desc_ptr->lock = 1; + CVMX_SYNCW; + cons_desc_ptr->num_consoles = num_consoles; + cons_desc_ptr->flags = 0; + cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION; + cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION; + + avail_addr = addr + sizeof(struct octeon_pcie_console_desc) + + num_consoles * sizeof(u64); + + for (i = 0; i < num_consoles; i++) { + cons_desc_ptr->console_addr_array[i] = avail_addr; + cons_ptr = (void *)cons_desc_ptr->console_addr_array[i]; + avail_addr += sizeof(struct octeon_pcie_console); + cons_ptr->input_base_addr = avail_addr; + avail_addr += buffer_size; + cons_ptr->output_base_addr = avail_addr; + avail_addr += buffer_size; + cons_ptr->buf_size = buffer_size; + } + CVMX_SYNCW; + cons_desc_ptr->lock = 0; + + return cvmx_phys_to_ptr(addr); +} + +static int octeon_pcie_console_getc(struct udevice *dev) +{ + char c; + + octeon_pcie_console_read(dev, 0, &c, 1, 0); + return c; +} + +static int octeon_pcie_console_putc(struct udevice *dev, const char c) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + + if (priv->console_active) + octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0); + + return 0; +} + +static int octeon_pcie_console_pending(struct udevice *dev, bool input) +{ + if (input) { + udelay(100); + return buffer_read_avail(dev, 0) > 0; + } + + return 0; +} + +static const struct dm_serial_ops octeon_pcie_console_ops = { + .getc = octeon_pcie_console_getc, + .putc = octeon_pcie_console_putc, + .pending = octeon_pcie_console_pending, +}; + +static int octeon_pcie_console_probe(struct udevice *dev) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console_desc *cons_desc; + int console_count; + int console_size; + int console_num; + + /* + * Currently only 1 console is supported. Perhaps we need to add + * a console nexus if more than one needs to be supported. + */ + console_count = 1; + console_size = 1024; + console_num = 0; + + cons_desc = octeon_pcie_console_init(console_count, console_size); + priv->console = + cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]); + + debug("PCI console init succeeded, %d consoles, %d bytes each\n", + console_count, console_size); + + return 0; +} + +static const struct udevice_id octeon_pcie_console_serial_id[] = { + { .compatible = "marvell,pci-console", }, + { }, +}; + +U_BOOT_DRIVER(octeon_pcie_console) = { + .name = DRIVER_NAME, + .id = UCLASS_SERIAL, + .ops = &octeon_pcie_console_ops, + .of_match = of_match_ptr(octeon_pcie_console_serial_id), + .probe = octeon_pcie_console_probe, + .priv_auto = sizeof(struct octeon_pcie_console_priv), +};

This patch adds the necessary platform infrastructure code, so that the MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can be used. This is e.g. the bootmem initialization in a compatible way to the Marvell 2013 U-Boot, so that the exisiting PC remote tools like "oct-remote-console" & "oct-remote-load" can be used. This is be done in the newly introduced arch_misc_init(), which calls the necessary init functions when enabled.

These patches are in preparation for the MIPS Octeon NIC23 board support, which is a desktop PCIe target board enabling these features.

Signed-off-by: Stefan Roese sr@denx.de Cc: Aaron Williams awilliams@marvell.com Cc: Chandrakala Chavva cchavva@marvell.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---

arch/mips/mach-octeon/cpu.c | 327 ++++++++++++++++++++++++++++++++++++ 1 file changed, 327 insertions(+)

diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c index 6f87a4ef8cbb..3fde9fbc4708 100644 --- a/arch/mips/mach-octeon/cpu.c +++ b/arch/mips/mach-octeon/cpu.c @@ -3,6 +3,10 @@ * Copyright (C) 2020 Marvell International Ltd. */

+#include <dm.h> +#include <dm/uclass.h> +#include <env.h> +#include <iomux.h> #include <asm/global_data.h> #include <linux/bitfield.h> #include <linux/bitops.h> @@ -10,9 +14,24 @@ #include <linux/io.h> #include <mach/clock.h> #include <mach/cavm-reg.h> +#include <mach/cvmx-bootmem.h>

DECLARE_GLOBAL_DATA_PTR;

+/* + * Important: + * This address cannot be changed as the PCI console tool relies on exactly + * this value! + */ +#define BOOTLOADER_BOOTMEM_DESC_ADDR 0x6c100 +#define BOOTLOADER_BOOTMEM_DESC_SPACE (BOOTLOADER_BOOTMEM_DESC_ADDR + 0x8) + +#define OCTEON_RESERVED_LOW_BOOT_MEM_SIZE (1024 * 1024) + +#define BOOTCMD_NAME "pci-bootcmd" +#define CONSOLE_NAME "pci-console@0" +#define OCTEON_BOOTLOADER_LOAD_MEM_NAME "__tmp_load" + /* * TRUE for devices having registers with little-endian byte * order, FALSE for registers with native-endian byte order. @@ -85,3 +104,311 @@ int print_cpuinfo(void)

return 0; } + +static int octeon_bootmem_init(void) +{ + int ret; + + /* Call old single-node func: it uses only gd->ram_size */ + ret = cvmx_bootmem_phy_mem_list_init(gd->ram_size, + OCTEON_RESERVED_LOW_BOOT_MEM_SIZE, + (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE)); + if (!ret) { + printf("FATAL: Error initializing bootmem list\n"); + return -ENOSPC; + } + + /* + * Put bootmem descriptor address in known location for host. + * Make sure it is not in kseg0, as we want physical address + */ + writeq((u64)__cvmx_bootmem_internal_get_desc_ptr() & 0x7fffffffull, + (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_ADDR)); + + debug("Reserving first 1MB of memory\n"); + ret = cvmx_bootmem_reserve_memory(0, OCTEON_RESERVED_LOW_BOOT_MEM_SIZE, + "__low_reserved", 0); + if (!ret) + puts("Error reserving low 1MB of memory\n"); + +#ifdef DEBUG + cvmx_bootmem_phy_list_print(); +#endif + + return 0; +} + +static int octeon_configure_load_memory(void) +{ + char *eptr; + u32 addr; + u32 size; + int ret; + + eptr = env_get("octeon_reserved_mem_load_size"); + if (!eptr || !strcmp("auto", eptr)) { + /* + * Pick a size that we think is appropriate. + * Please note that for small memory boards this guess + * will likely not be ideal. + * Please pick a specific size for boards/applications + * that require it. + */ + if (gd->ram_size <= (256 << 20)) { + size = min_t(u64, (128 << 20), + ((gd->ram_size * 2) / 5) & ~0xFFFFF); + } else { + size = min_t(u64, (256 << 20), + ((gd->ram_size - (256 << 20)) / 3) & ~0xFFFFF); + } + } else { + size = simple_strtol(eptr, NULL, 16); + debug("octeon_reserved_mem_load_size=0x%08x\n", size); + } + + if (size) { + debug("Linux reserved load size 0x%08x\n", size); + eptr = env_get("octeon_reserved_mem_load_base"); + if (!eptr || !strcmp("auto", eptr)) { + u64 mem_top; + /* + * Leave some room for previous allocations that + * are made starting at the top of the low + * 256 Mbytes of DRAM + */ + int adjust = (1 << 20); + + if (gd->ram_size <= (512 << 20)) + adjust = (17 << 20); + + /* Put block at the top of DDR0, or bottom of DDR2 */ + if ((gd->ram_size <= (256 << 20)) || + (size > (gd->ram_size - (256 << 20)))) { + mem_top = min_t(u64, gd->ram_size - adjust, + (256 << 20) - adjust); + } else if ((gd->ram_size <= (512 << 20)) || + (size > (gd->ram_size - (512 << 20)))) { + mem_top = min_t(u64, gd->ram_size - adjust, + (512 << 20) - adjust); + } else { + /* + * We have enough room, so set + * mem_top so that the block is + * at the base of the DDR2 + * segment + */ + mem_top = (512 << 20) + size; + } + + /* + * Adjust for boot bus memory hole on OCTEON II + * and later. + */ + if ((gd->ram_size > (256 << 20))) + mem_top += (256 << 20); + + debug("Adjusted memory top is 0x%llx\n", mem_top); + addr = mem_top - size; + if (addr > (512 << 20)) + addr = (512 << 20); + if ((addr >= (256 << 20)) && addr < (512 << 20)) { + /* + * The address landed in the boot-bus + * memory hole. Dig it out of the hole. + */ + addr = (512 << 20); + } + } else { + addr = simple_strtol(eptr, NULL, 16); + } + + ret = cvmx_bootmem_phy_named_block_alloc(size, addr, + addr + size, 0, + OCTEON_BOOTLOADER_LOAD_MEM_NAME, + 0); + if (ret < 0) { + printf("ERROR: Unable to allocate bootloader reserved memory (addr: 0x%x, size: 0x%x).\n", + addr, size); + } else { + /* + * Set default load address to base of memory + * reserved for loading. The setting of the + * env. variable also sets the load_addr global + * variable. + * This environment variable is overridden each + * boot if a reserved block is created. + */ + char str[20]; + + snprintf(str, sizeof(str), "0x%x", addr); + env_set("loadaddr", str); + debug("Setting load address to 0x%08x, size 0x%x\n", + addr, size); + } + return 0; + } + + printf("WARNING: No reserved memory for image loading.\n"); + return -1; +} + +static int init_pcie_console(void) +{ + char *stdinname = env_get("stdin"); + char *stdoutname = env_get("stdout"); + char *stderrname = env_get("stderr"); + struct udevice *pcie_console_dev = NULL; + bool stdin_set, stdout_set, stderr_set; + char iomux_name[128]; + int ret = 0; + + debug("%s: stdin: %s, stdout: %s, stderr: %s\n", __func__, stdinname, + stdoutname, stderrname); + if (!stdinname) { + env_set("stdin", "serial"); + stdinname = env_get("stdin"); + } + if (!stdoutname) { + env_set("stdout", "serial"); + stdoutname = env_get("stdout"); + } + if (!stderrname) { + env_set("stderr", "serial"); + stderrname = env_get("stderr"); + } + + if (!stdinname || !stdoutname || !stderrname) { + printf("%s: Error setting environment variables for serial\n", + __func__); + return -1; + } + + stdin_set = !!strstr(stdinname, CONSOLE_NAME); + stdout_set = !!strstr(stdoutname, CONSOLE_NAME); + stderr_set = !!strstr(stderrname, CONSOLE_NAME); + + log_debug("stdin: %d, "%s", stdout: %d, "%s", stderr: %d, "%s"\n", + stdin_set, stdinname, stdout_set, stdoutname, + stderr_set, stderrname); + ret = uclass_get_device_by_name(UCLASS_SERIAL, CONSOLE_NAME, + &pcie_console_dev); + if (ret || !pcie_console_dev) { + debug("%s: No PCI console device %s found\n", __func__, + CONSOLE_NAME); + return 0; + } + + if (stdin_set) + strncpy(iomux_name, stdinname, sizeof(iomux_name)); + else + snprintf(iomux_name, sizeof(iomux_name), "%s,%s", + stdinname, pcie_console_dev->name); + + ret = iomux_doenv(stdin, iomux_name); + if (ret) { + log_err("%s: Error setting I/O stdin MUX to %s\n", + __func__, iomux_name); + return ret; + } + + if (!stdin_set) + env_set("stdin", iomux_name); + + if (stdout_set) + strncpy(iomux_name, stdoutname, sizeof(iomux_name)); + else + snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stdoutname, + pcie_console_dev->name); + + ret = iomux_doenv(stdout, iomux_name); + if (ret) { + log_err("%s: Error setting I/O stdout MUX to %s\n", + __func__, iomux_name); + return ret; + } + if (!stdout_set) + env_set("stdout", iomux_name); + + if (stderr_set) + strncpy(iomux_name, stderrname, sizeof(iomux_name)); + else + snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stderrname, + pcie_console_dev->name); + + ret = iomux_doenv(stderr, iomux_name); + if (ret) { + log_err("%s: Error setting I/O stderr MUX to %s\n", + __func__, iomux_name); + return ret; + } + + if (!stderr_set) + env_set("stderr", iomux_name); + + debug("%s: stdin: %s, stdout: %s, stderr: %s, ret: %d\n", + __func__, env_get("stdin"), env_get("stdout"), + env_get("stderr"), ret); + + return ret; +} + +static int init_bootcmd_console(void) +{ + char *stdinname = env_get("stdin"); + struct udevice *bootcmd_dev = NULL; + bool stdin_set; + char iomux_name[128]; + int ret = 0; + + debug("%s: stdin before: %s\n", __func__, + stdinname ? stdinname : "NONE"); + if (!stdinname) { + env_set("stdin", "serial"); + stdinname = env_get("stdin"); + } + stdin_set = !!strstr(stdinname, BOOTCMD_NAME); + ret = uclass_get_device_by_driver(UCLASS_SERIAL, + DM_DRIVER_GET(octeon_bootcmd), + &bootcmd_dev); + if (ret) { + log_err("%s: Error getting %s serial class\n", __func__, + BOOTCMD_NAME); + } else if (bootcmd_dev) { + if (stdin_set) + strncpy(iomux_name, stdinname, sizeof(iomux_name)); + else + snprintf(iomux_name, sizeof(iomux_name), "%s,%s", + stdinname, bootcmd_dev->name); + ret = iomux_doenv(stdin, iomux_name); + if (ret) + log_err("%s: Error %d enabling the PCI bootcmd input console "%s"\n", + __func__, ret, iomux_name); + if (!stdin_set) + env_set("stdin", iomux_name); + } + + debug("%s: Set iomux and stdin to %s (ret: %d)\n", + __func__, iomux_name, ret); + return ret; +} + +int arch_misc_init(void) +{ + int ret; + + ret = octeon_bootmem_init(); + if (ret) + return ret; + + ret = octeon_configure_load_memory(); + if (ret) + return ret; + + if (CONFIG_IS_ENABLED(OCTEON_SERIAL_PCIE_CONSOLE)) + init_pcie_console(); + + if (CONFIG_IS_ENABLED(OCTEON_SERIAL_BOOTCMD)) + init_bootcmd_console(); + + return 0; +}

This patch enables the usage of the MVEBU AHCI/SATA driver. The only changes necessary to support MIPS Octeon via DT based probing are, to add the compatible DT property and the use of dev_remap_addr() so that the correct mapped address is used in the Octeon case (phys != virt).

Please note that this driver supports the usage of the "scsi" command and not the "sata" command, since it does not provide an own "scan" function, which is needed for the "sata" cmd support.

Signed-off-by: Stefan Roese sr@denx.de Cc: Aaron Williams awilliams@marvell.com Cc: Chandrakala Chavva cchavva@marvell.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---

drivers/ata/Kconfig | 2 +- drivers/ata/ahci_mvebu.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index f2f8275aeca8..6e47964cdc8f 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -121,7 +121,7 @@ config SUNXI_AHCI

config AHCI_MVEBU bool "Marvell EBU AHCI SATA support" - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_OCTEON depends on AHCI select SCSI_AHCI select DM_SCSI diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index 7d82d2ea3fff..f05150d61ddf 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -39,7 +39,7 @@ static int mvebu_ahci_probe(struct udevice *dev) */ board_ahci_enable();

- ahci_probe_scsi(dev, dev_read_addr(dev)); + ahci_probe_scsi(dev, (ulong)dev_remap_addr(dev));

return 0; } @@ -48,6 +48,7 @@ static const struct udevice_id mvebu_ahci_ids[] = { { .compatible = "marvell,armada-380-ahci" }, { .compatible = "marvell,armada-3700-ahci" }, { .compatible = "marvell,armada-8k-ahci" }, + { .compatible = "cavium,octeon-7130-ahci" }, { } };

Otherwise the output will look like this on MIPS Octeon NIC23:

Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)

instead of this version:

Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512)

Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Aaron Williams awilliams@marvell.com Cc: Chandrakala Chavva cchavva@marvell.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---

drivers/scsi/scsi.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 738948449053..ce69750c7ff0 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -9,6 +9,7 @@ #include <bootstage.h> #include <dm.h> #include <env.h> +#include <libata.h> #include <log.h> #include <part.h> #include <pci.h> @@ -594,6 +595,11 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor)); memcpy(&bdesc->product, &bd.product, sizeof(bd.product)); memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision)); + if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN)) { + ata_swap_buf_le16((u16 *)&bdesc->vendor, sizeof(bd.vendor) / 2); + ata_swap_buf_le16((u16 *)&bdesc->product, sizeof(bd.product) / 2); + ata_swap_buf_le16((u16 *)&bdesc->revision, sizeof(bd.revision) / 2); + }

if (verbose) { printf(" Device %d: ", bdesc->devnum);

This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC.

Signed-off-by: Stefan Roese sr@denx.de ---

arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,octeon-nic23.dts | 162 +++++++++++++++ arch/mips/mach-octeon/Kconfig | 7 + board/Marvell/octeon_nic23/Kconfig | 19 ++ board/Marvell/octeon_nic23/MAINTAINERS | 7 + board/Marvell/octeon_nic23/Makefile | 8 + board/Marvell/octeon_nic23/board.c | 106 ++++++++++ board/Marvell/octeon_nic23/board_ddr.h | 269 +++++++++++++++++++++++++ configs/octeon_nic23_defconfig | 70 +++++++ include/configs/octeon_nic23.h | 21 ++ 10 files changed, 670 insertions(+) create mode 100644 arch/mips/dts/mrvl,octeon-nic23.dts create mode 100644 board/Marvell/octeon_nic23/Kconfig create mode 100644 board/Marvell/octeon_nic23/MAINTAINERS create mode 100644 board/Marvell/octeon_nic23/Makefile create mode 100644 board/Marvell/octeon_nic23/board.c create mode 100644 board/Marvell/octeon_nic23/board_ddr.h create mode 100644 configs/octeon_nic23_defconfig create mode 100644 include/configs/octeon_nic23.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 7c429231340c..215283cfa05b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -20,6 +20,7 @@ dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb +dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb diff --git a/arch/mips/dts/mrvl,octeon-nic23.dts b/arch/mips/dts/mrvl,octeon-nic23.dts new file mode 100644 index 000000000000..72ef56d834e4 --- /dev/null +++ b/arch/mips/dts/mrvl,octeon-nic23.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. NIC23 + */ + +/dts-v1/; + +#include "mrvl,cn73xx.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "cavium,nic23"; + compatible = "cavium,nic23"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart0; + spi0 = &spi; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* Power on GPIO 8, active high */ + reg_mmc_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "mmc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&bootbus { + /* + * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) + * as the initial size is too small for the 8MiB flash device + */ + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x10000000 0>, + <2 0 0x10000 0x20000000 0>, + <3 0 0x10000 0x30000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0x10000 0x50000000 0>, + <6 0 0x10000 0x60000000 0>, + <7 0 0x10000 0x70000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <50>; + cavium,t-page = <30>; + cavium,t-rd-dly = <0>; + cavium,page-mode = <1>; + cavium,pages = <8>; + cavium,bus-width = <8>; + }; + + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <10>; + cavium,t-ce = <10>; + cavium,t-oe = <160>; + cavium,t-we = <100>; + cavium,t-rd-hld = <10>; + cavium,t-wr-hld = <0>; + cavium,t-pause = <50>; + cavium,t-wait = <50>; + cavium,t-page = <10>; + cavium,t-rd-dly = <10>; + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0 0x340000>; + read-only; + }; + partition@300000 { + label = "storage"; + reg = <0x340000 0x4be000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <800000000>; +}; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&mmc { + status = "okay"; + + mmc0: mmc-slot@0 { + compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; + reg = <0>; + vqmmc-supply = <&reg_mmc_3v3>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <52000000>; + /* bus width can be 1, 4 or 8 */ + bus-width = <8>; /* new std property */ + cavium,bus-max-width = <8>; /* custom property */ + non-removable; + }; +}; + +&soc0 { + pci-console@0 { + compatible = "marvell,pci-console"; + status = "okay"; + }; + + pci-bootcmd@0 { + compatible = "marvell,pci-bootcmd"; + status = "okay"; + }; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index d69408cc2753..624039df2536 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -41,6 +41,12 @@ config TARGET_OCTEON_EBB7304 help Choose this for the Octeon EBB7304 board

+config TARGET_OCTEON_NIC23 + bool "Marvell Octeon NIC23" + select OCTEON_CN73XX + help + Choose this for the Octeon NIC23 board + endchoice

config SYS_DCACHE_SIZE @@ -60,5 +66,6 @@ config SYS_PCI_64BIT default y

source "board/Marvell/octeon_ebb7304/Kconfig" +source "board/Marvell/octeon_nic23/Kconfig"

endmenu diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig new file mode 100644 index 000000000000..3c42e8acdadc --- /dev/null +++ b/board/Marvell/octeon_nic23/Kconfig @@ -0,0 +1,19 @@ +if TARGET_OCTEON_NIC23 + +config SYS_BOARD + string + default "octeon_nic23" + +config SYS_VENDOR + string + default "Marvell" + +config SYS_CONFIG_NAME + string + default "octeon_nic23" + +config DEFAULT_DEVICE_TREE + string + default "mrvl,octeon-nic23" + +endif diff --git a/board/Marvell/octeon_nic23/MAINTAINERS b/board/Marvell/octeon_nic23/MAINTAINERS new file mode 100644 index 000000000000..cd5148dcfee9 --- /dev/null +++ b/board/Marvell/octeon_nic23/MAINTAINERS @@ -0,0 +1,7 @@ +OCTEON_NIC23 BOARD +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: board/Marvell/octeon_nic23/* +F: configs/octeon_nic23_defconfig +F: include/configs/octeon_nic23.h +F: arch/mips/dts/mrvl,octeon-nic23.dts diff --git a/board/Marvell/octeon_nic23/Makefile b/board/Marvell/octeon_nic23/Makefile new file mode 100644 index 000000000000..a79b94ec6f1b --- /dev/null +++ b/board/Marvell/octeon_nic23/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2021 Stefan Roese sr@denx.de +# Copyright (C) 2019-2020 Marvell International Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c new file mode 100644 index 000000000000..9f5eb2e2a182 --- /dev/null +++ b/board/Marvell/octeon_nic23/board.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Stefan Roese sr@denx.de + */ + +#include <dm.h> +#include <ram.h> + +#include <mach/octeon_ddr.h> +#include <mach/cvmx-qlm.h> +#include <mach/octeon_qlm.h> +#include <mach/octeon_fdt.h> +#include <mach/cvmx-helper.h> +#include <mach/cvmx-helper-cfg.h> +#include <mach/cvmx-helper-util.h> +#include <mach/cvmx-bgxx-defs.h> + +#include "board_ddr.h" + +#define NIC23_DEF_DRAM_FREQ 800 + +static u8 octeon_nic23_cfg0_spd_values[512] = { + OCTEON_NIC23_CFG0_SPD_VALUES +}; + +static struct ddr_conf board_ddr_conf[] = { + OCTEON_NIC23_DDR_CONFIGURATION +}; + +struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq) +{ + *count = ARRAY_SIZE(board_ddr_conf); + *def_ddr_freq = NIC23_DEF_DRAM_FREQ; + + return board_ddr_conf; +} + +int board_fix_fdt(void *fdt) +{ + u32 range_data[5 * 8]; + bool rev4; + int node; + int rc; + + /* + * ToDo: + * Read rev4 info from EEPROM or where the original U-Boot does + * and don't hard-code it here. + */ + rev4 = true; + + debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false"); + /* Patch the PHY configuration based on board revision */ + rc = octeon_fdt_patch_rename(fdt, + rev4 ? "4,nor-flash" : "4,no-nor-flash", + "cavium,board-trim", false, NULL, NULL); + if (!rev4) { + /* Modify the ranges for CS 0 */ + node = fdt_node_offset_by_compatible(fdt, -1, + "cavium,octeon-3860-bootbus"); + if (node < 0) { + printf("%s: Error: cannot find boot bus in device tree!\n", + __func__); + return -1; + } + + rc = fdtdec_get_int_array(fdt, node, "ranges", + range_data, 5 * 8); + if (rc) { + printf("%s: Error reading ranges from boot bus FDT\n", + __func__); + return -1; + } + range_data[2] = cpu_to_fdt32(0x10000); + range_data[3] = 0; + range_data[4] = 0; + rc = fdt_setprop(fdt, node, "ranges", range_data, + sizeof(range_data)); + if (rc) { + printf("%s: Error updating boot bus ranges in fdt\n", + __func__); + } + } + return rc; +} + +void board_configure_qlms(void) +{ + octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0); + octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0); + /* Apply amplitude tuning to 10G interface */ + octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1); + octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1); + octeon_qlm_set_channel_v3(0, 5, 0); + octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2); + debug("QLM 4 reference clock: %d\n" + "DLM 5 reference clock: %d\n", + cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5)); +} + +int board_late_init(void) +{ + board_configure_qlms(); + + return 0; +} diff --git a/board/Marvell/octeon_nic23/board_ddr.h b/board/Marvell/octeon_nic23/board_ddr.h new file mode 100644 index 000000000000..eac877faf853 --- /dev/null +++ b/board/Marvell/octeon_nic23/board_ddr.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __BOARD_DDR_H__ +#define __BOARD_DDR_H__ + +#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \ + { {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} } + +#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \ + 0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \ + 0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \ + 0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \ + 0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \ + 0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \ + 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \ + 0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \ + 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \ + 0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \ + 0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \ + 0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \ + 0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \ + 0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \ + 0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES + +#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56 + +#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \ +{ \ + .cn78xx = { \ + .pasr_00 = 0, \ + .asr_00 = 0, \ + .srt_00 = 0, \ + .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_00 = ddr4_dic_34ohm, \ + .rtt_nom_00 = 0, \ + .pasr_01 = 0, \ + .asr_01 = 0, \ + .srt_01 = 0, \ + .rtt_wr_01 = 0, \ + .dic_01 = ddr4_dic_34ohm, \ + .rtt_nom_01 = 0, \ + .pasr_10 = 0, \ + .asr_10 = 0, \ + .srt_10 = 0, \ + .rtt_wr_10 = 0, \ + .dic_10 = ddr4_dic_34ohm, \ + .rtt_nom_10 = 0, \ + .pasr_11 = 0, \ + .asr_11 = 0, \ + .srt_11 = 0, \ + .rtt_wr_11 = 0, \ + .dic_11 = ddr4_dic_34ohm, \ + .rtt_nom_11 = 0, \ + } \ + } + +#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \ +{ \ + .cn78xx = { \ + .pasr_00 = 0, \ + .asr_00 = 0, \ + .srt_00 = 0, \ + .rtt_wr_00 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_00 = ddr4_dic_34ohm, \ + .rtt_nom_00 = 0, \ + .pasr_01 = 0, \ + .asr_01 = 0, \ + .srt_01 = 0, \ + .rtt_wr_01 = 0, \ + .dic_01 = ddr4_dic_34ohm, \ + .rtt_nom_01 = 0, \ + .pasr_10 = 0, \ + .asr_10 = 0, \ + .srt_10 = 0, \ + .rtt_wr_10 = ddr4_rttwr_80ohm & 3, \ + .rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \ + .dic_10 = ddr4_dic_34ohm, \ + .rtt_nom_10 = 0, \ + .pasr_11 = 0, \ + .asr_11 = 0, \ + .srt_11 = 0, \ + .rtt_wr_11 = 0, \ + .dic_11 = ddr4_dic_34ohm, \ + .rtt_nom_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \ +{ \ + .cn78xx = { \ + .rtt_park_00 = ddr4_rttpark_60ohm, \ + .vref_value_00 = 0x22, \ + .vref_range_00 = 0, \ + .rtt_park_01 = 0, \ + .vref_value_01 = 0, \ + .vref_range_01 = 0, \ + .rtt_park_10 = 0, \ + .vref_value_10 = 0, \ + .vref_range_10 = 0, \ + .rtt_park_11 = 0, \ + .vref_value_11 = 0, \ + .vref_range_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \ +{ \ + .cn78xx = { \ + .rtt_park_00 = ddr4_rttpark_48ohm, \ + .vref_value_00 = 0x1f, \ + .vref_range_00 = 0, \ + .rtt_park_01 = 0, \ + .vref_value_01 = 0, \ + .vref_range_01 = 0, \ + .rtt_park_10 = ddr4_rttpark_48ohm, \ + .vref_value_10 = 0x1f, \ + .vref_range_10 = 0, \ + .rtt_park_11 = 0, \ + .vref_value_11 = 0, \ + .vref_range_11 = 0 \ + } \ +} + +#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \ + /* 1 */ \ + { \ + ddr4_dqx_driver_34_ohm, \ + 0x00000000ULL, \ + OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \ + OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \ + ddr4_rodt_ctl_48_ohm, \ + 0x00000000ULL, \ + 0 \ + }, \ + /* 2 */ \ + { \ + ddr4_dqx_driver_34_ohm, \ + 0x00000000ULL, \ + OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \ + OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \ + ddr4_rodt_ctl_80_ohm, \ + 0x00000000ULL, \ + 0 \ + } + +/* + * Construct a static initializer for the ddr_configuration_t variable that + * holds (almost) all of the information required for DDR initialization. + */ + +/* + * The parameters below make up the custom_lmc_config data structure. + * This structure is used to customize the way that the LMC DRAM + * Controller is configured for a particular board design. + * + * Refer to the file lib_octeon_board_table_entry.h for a description + * of the custom board settings. It is usually kept in the following + * location... arch/mips/include/asm/arch-octeon/ + * + */ + +#define OCTEON_NIC23_DDR_CONFIGURATION \ +/* Interface 0 */ \ +{ \ + .custom_lmc_config = { \ + .min_rtt_nom_idx = 2, \ + .max_rtt_nom_idx = 5, \ + .min_rodt_ctl = 2, \ + .max_rodt_ctl = 4, \ + .ck_ctl = ddr4_driver_34_ohm, \ + .cmd_ctl = ddr4_driver_34_ohm, \ + .ctl_ctl = ddr4_driver_34_ohm, \ + .min_cas_latency = 7, \ + .offset_en = 1, \ + .offset_udimm = 2, \ + .offset_rdimm = 2, \ + .ddr_rtt_nom_auto = 0, \ + .ddr_rodt_ctl_auto = 0, \ + .rlevel_compute = 0, \ + .ddr2t_udimm = 1, \ + .ddr2t_rdimm = 1, \ + .maximum_adjacent_rlevel_delay_increment = 2, \ + .fprch2 = 2, \ + .dll_write_offset = NULL, \ + .dll_read_offset = NULL, \ + .disable_sequential_delay_check = 1, \ + .parity = 0 \ + }, \ + .dimm_config_table = { \ + OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \ + DIMM_CONFIG_TERMINATOR \ + }, \ + .unbuffered = { \ + .ddr_board_delay = 0, \ + .lmc_delay_clk = 0, \ + .lmc_delay_cmd = 0, \ + .lmc_delay_dq = 0 \ + }, \ + .registered = { \ + .ddr_board_delay = 0, \ + .lmc_delay_clk = 0, \ + .lmc_delay_cmd = 0, \ + .lmc_delay_dq = 0 \ + }, \ + .odt_1rank_config = { \ + OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \ + }, \ +}, + +#endif /* __BOARD_DDR_H__ */ diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig new file mode 100644 index 000000000000..f36af437c029 --- /dev/null +++ b/configs/octeon_nic23_defconfig @@ -0,0 +1,70 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xe000 +CONFIG_ENV_SECT_SIZE=0x100 +CONFIG_DEBUG_UART_BASE=0x8001180000000800 +CONFIG_DEBUG_UART_CLOCK=800000000 +CONFIG_ARCH_OCTEON=y +CONFIG_TARGET_OCTEON_NIC23=y +# CONFIG_MIPS_CACHE_SETUP is not set +# CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0xe000 +CONFIG_SATA=y +CONFIG_AHCI_MVEBU=y +CONFIG_CLK=y +# CONFIG_INPUT is not set +CONFIG_MISC=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_NETDEVICES is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_RAM_OCTEON=y +CONFIG_RAM_OCTEON_DDR4=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_SHIFT=3 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_OCTEON_SERIAL_BOOTCMD=y +CONFIG_OCTEON_SERIAL_PCIE_CONSOLE=y +CONFIG_SPI=y +CONFIG_OCTEON_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_OCTEON=y +CONFIG_HEXDUMP=y diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h new file mode 100644 index 000000000000..0a7b4d8f93e2 --- /dev/null +++ b/include/configs/octeon_nic23.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell <www.marvell.com> + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* + * SATA/SCSI/AHCI configuration + */ +/* AHCI support Definitions */ +/** Enable 48-bit SATA addressing */ +#define CONFIG_LBA48 +/** Enable 64-bit addressing */ +#define CONFIG_SYS_64BIT_LBA + +#include "octeon_common.h" + +#endif /* __CONFIG_H__ */

From: Aaron Williams awilliams@marvell.com

This patch adds support for the following I2C devices connected to I2C bus 0 on the Octeon EBB7304: - Dallas DS1337 RTC - TLV EEPROM

Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de Cc: Chandrakala Chavva cchavva@marvell.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com ---

arch/mips/dts/mrvl,octeon-ebb7304.dts | 11 +++++++++++ configs/octeon_ebb7304_defconfig | 4 ++++ 2 files changed, 15 insertions(+)

diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts index b95c18d34482..fda559d8629d 100644 --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -115,6 +115,17 @@ &i2c0 { u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + + tlv-eeprom@56 { + compatible = "atmel,24c256", "microchip,24lc256"; + reg = <0x56>; + pagesize = <64>; + }; };

&i2c1 { diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 4b25a4068245..8f0847fd0701 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_CLOCK=1200000000 CONFIG_ARCH_OCTEON=y # CONFIG_MIPS_CACHE_SETUP is not set # CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000 CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,6 +24,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y @@ -57,6 +59,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_RAM_OCTEON=y CONFIG_RAM_OCTEON_DDR4=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y CONFIG_DEBUG_UART_SHIFT=3 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y