[U-Boot] [PATCH v11 0/4] mtd: nand: omap: optimize and clean-up of OMAP NAND driver
*changes in v11* [PATCH 2/4] fixed 'unused variable' warning
*changes in v10* [PATCH 1/4] re-generated patche using 'git format-patch -M -C' to detect renames [PATCH 2/4] removed #ifdef while including omap_elm.h header in omap_gpmc.c [PATCH 3/4] and [PATCH 4/4] <no update>
*changes in v9* (Important) As this patch series was becoming bulky and had many un-related patches, so it has been split into two parts. Part-1: Current patch series focuses on cleaning up GPMC and ELM drivers maintaining existing functionality. And update ecc-scheme selection mechanism across all platforms. Part-2: Next patch series will focus on optimizing data-paths of GPMC and ELM drivers for better performance and scalability.
This Part-1 series has following patches, maintaining earlier feedbacks. [PATCH 1/4] [NEW] mtd: nand: omap: make am33xx/elm.c as common driver - move ELM driver source to drivers/mtd/nand/ to reuse driver on all platforms
[PATCH 2/4] [SPLIT] mtd: nand: omap: enable BCH ECC scheme using ELM for ... v8 version of this patch is split into follwing part maintaining earlier feedbacks. - [PATCH 2/4] handles ecc-scheme selection clean-up - [PATCH 3/4] add CONFIG_NAND_OMAP_ECCSCHEME
[PATCH 3/4] [NEW] mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME ... - split from previous patch to introduce new CONFIG_xx for having common method of ecc-scheme selection across all platforms. - updated include/configs/ for SoC platforms (like OMAP3) which use omap_gpmc.c
[PATCH 4/4] [NEW] am335x: fix GPMC config for NAND and NOR SPL boot - clean separation of NOR Boot and NAND Boot configurations - configuration of GPMC registers moved to arch/am33xx from board/ti/am335x/board.c, so that its re-usable for other boards also.
This patch is tested on beagle-bone (white) with NAND cape, using following (a) Patch to add beaglebone pin-mux support http://lists.denx.de/pipermail/u-boot/2013-September/163881.html (b) Hack in board-file to configure GPMC for x16 device -------------- diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 56c9e7d..b166a94 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -64,7 +64,7 @@ void gpmc_init(void) u32 base = CONFIG_SYS_FLASH_BASE; #elif defined(CONFIG_NAND) /* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1 | 0x1000, M_NAND_GPMC_CONFIG2, M_NAND_GPMC_CONFIG3, M_NAND_GPMC_CONFIG4, --------------
*changes in v8* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - incorporated following feedbacks from Scott Wood scottwood@freescale.com - using symbolic names (enums) as values of CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme(): perform ecc-scheme compatibility checks before updating nand_chip.ecc fields. This avoids corrupting of existing ecc-scheme in case of switching failures. - code clean-up (removed fall-back on omap_select_ecc_scheme() failures)
*changes in v7* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - omap_gpmc.c: fix: free bytes in OOB (ecclayout->oobfree[0].length) - omap_gpmc.c: cleanup: redundant code added in previous patch versions - am335x_evm.h: cleanup: redundant code added in previous patch versions - tricorder.h: fix: CONFIG_NAND_OMAP_ECCSCHEME
*changes in v6* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - incorporated feedbacks from Scott Wood scottwood@freescale.com - renamed CONFIG_SYS_NAND_ECCSCHEME to CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme() to handle error conditions without depending on caller. - renamed OMAP_ECC_HAM1_CODE_HW_ROMCODE to OMAP_ECC_HAM1_CODE_HW to keep it naming compatible to linux kernel - updated doc/README.nand and doc/README.omap3 - moved CONFIG_NAND_OMAP_ECCSCHEME description to README.nand
*changes in v5* This version of patch is tested on am335x-evm with x8 NAND device, and boots SPL and u-boot from NAND [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - re-added omap_read_page_bch(): needed proper sequence of while reading DATA and ECC from NAND page, so that calc_ecc generated from GPMC is understood by ELM. - added check to see if NAND OOB can accomodate ECC for entire page
*changes in v4* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - removed omap_read_page_bch(): chip->ecc.read_page uses default API nand_read_page_hwecc() in nand_base.c - updated tricorder.h: added new CONFIGS for ECCSCHEME & ONFI_DETECTION - converted printf("ECC-SCHEME") to debug("ECC-SCHEME")
*changes in v3* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform (complete re-work) - ecc-scheme is selection is controller by s/w, not CONFIG_NAND_xx - added omap_select_ecc_scheme(), as common function to handle all ecc-scheme related configurations for both board_nand_init() & omap_nand_switch_ecc(). - removed un-used defines from asm/arch-am33xx/omap_gpmc.h - updated doc/REAME.nand - removed un-used defines from asm/omap_gpmc.h
*changes in v2* - added documentation for CONFIG_NAND_OMAP_xx in doc/README.nand - added CONFIG_BCH along with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW to include software library lib/bch.c - fixed board_nand_init() and omap_enable_hwecc()
*original v1* This patch series updates BCH8_ECC schemes in mtd/nand/omap_gpmc.c driver - adds scalability for higher ECC schemes in future. - removes CONFIG_AM335x and it makes it generic for all platforms. - optimizes read_data paths
Pekon Gupta (4): mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme am335x: fix GPMC config for NAND and NOR SPL boot
arch/arm/cpu/armv7/am33xx/Makefile | 1 - arch/arm/cpu/armv7/am33xx/mem.c | 52 ++-- arch/arm/include/asm/arch-am33xx/mem.h | 5 - .../include/asm/{arch-am33xx/elm.h => omap_elm.h} | 0 arch/arm/include/asm/omap_gpmc.h | 16 + board/ti/am335x/board.c | 14 +- doc/README.nand | 53 ++++ doc/README.omap3 | 3 +- drivers/mtd/nand/Makefile | 1 + .../am33xx/elm.c => drivers/mtd/nand/omap_elm.c | 6 +- drivers/mtd/nand/omap_gpmc.c | 321 +++++++++++++-------- include/configs/am335x_evm.h | 5 +- include/configs/am335x_igep0033.h | 2 + include/configs/am3517_crane.h | 1 + include/configs/am3517_evm.h | 1 + include/configs/devkit8000.h | 1 + include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_evm_quick_nand.h | 1 + include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/siemens-am33x-common.h | 2 + include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 2 +- 25 files changed, 319 insertions(+), 176 deletions(-) rename arch/arm/include/asm/{arch-am33xx/elm.h => omap_elm.h} (100%) rename arch/arm/cpu/armv7/am33xx/elm.c => drivers/mtd/nand/omap_elm.c (97%)
ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform.
Signed-off-by: Pekon Gupta pekon@ti.com --- arch/arm/cpu/armv7/am33xx/Makefile | 1 - .../arm/include/asm/{arch-am33xx/elm.h => omap_elm.h} | 0 doc/README.nand | 19 +++++++++++++++++++ drivers/mtd/nand/Makefile | 1 + .../armv7/am33xx/elm.c => drivers/mtd/nand/omap_elm.c | 6 +++--- drivers/mtd/nand/omap_gpmc.c | 2 +- include/configs/am335x_evm.h | 2 ++ include/configs/am335x_igep0033.h | 1 + include/configs/siemens-am33x-common.h | 1 + 9 files changed, 28 insertions(+), 5 deletions(-) rename arch/arm/include/asm/{arch-am33xx/elm.h => omap_elm.h} (100%) rename arch/arm/cpu/armv7/am33xx/elm.c => drivers/mtd/nand/omap_elm.c (97%)
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 966fcab..5566310 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -19,4 +19,3 @@ obj-y += ddr.o obj-y += emif4.o obj-y += board.o obj-y += mux.o -obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/omap_elm.h similarity index 100% rename from arch/arm/include/asm/arch-am33xx/elm.h rename to arch/arm/include/asm/omap_elm.h diff --git a/doc/README.nand b/doc/README.nand index 913e9b5..8d73df8 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -169,6 +169,25 @@ Configuration Options: Please convert your driver even if you don't need the extra flexibility, so that one day we can eliminate the old mechanism.
+ +Platform specific options +========================= + CONFIG_NAND_OMAP_GPMC + Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. + GPMC controller is used for parallel NAND flash devices, and can + do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 + and BCH16 ECC algorithms. + + CONFIG_NAND_OMAP_ELM + Enables omap_elm.c driver for OMAPx and AMxxxx platforms. + ELM controller is used for ECC error detection (not ECC calculation) + of BCH4, BCH8 and BCH16 ECC algorithms. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + thus such SoC platforms need to depend on software library for ECC error + detection. However ECC calculation on such plaforms would still be + done by GPMC controller. + + NOTE: =====
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index eb1eafa..e145cd1 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_DOCG4) += docg4.o
diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/drivers/mtd/nand/omap_elm.c similarity index 97% rename from arch/arm/cpu/armv7/am33xx/elm.c rename to drivers/mtd/nand/omap_elm.c index 8f1d6af..2aa7807 100644 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -18,7 +18,7 @@ #include <asm/errno.h> #include <asm/arch/cpu.h> #include <asm/omap_gpmc.h> -#include <asm/arch/elm.h> +#include <asm/omap_elm.h>
#define ELM_DEFAULT_POLY (0)
@@ -127,7 +127,7 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
for (i = 0; i < *error_count; i++) { error_locations[i] = - readl(&elm_cfg->error_location[poly].error_location_x[i]); + readl(&elm_cfg->error_location[poly].error_location_x[i]); }
return 0; @@ -175,7 +175,7 @@ void elm_reset(void) { /* initiate reset */ writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), - &elm_cfg->sysconfig); + &elm_cfg->sysconfig);
/* wait for reset complete and normal operation */ while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index ec1787f..c828859 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -16,7 +16,7 @@ #include <linux/compiler.h> #include <nand.h> #ifdef CONFIG_AM33XX -#include <asm/arch/elm.h> +#include <asm/omap_elm.h> #endif
static uint8_t cs; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index f35ed6f..4c79ddb 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -220,6 +220,8 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 2c69d4e..88ced73 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -187,6 +187,7 @@ /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 745e3be..85d6dc2 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -430,6 +430,7 @@ "\0"
#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+
Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM.
This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3
Signed-off-by: Pekon Gupta pekon@ti.com --- arch/arm/include/asm/omap_gpmc.h | 16 ++ doc/README.nand | 11 ++ drivers/mtd/nand/omap_gpmc.c | 326 ++++++++++++++++++++++++--------------- 3 files changed, 228 insertions(+), 125 deletions(-)
diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index dd40cb6..d4143ec 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -68,4 +68,20 @@ } #endif
+enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, +}; + #endif /* __ASM_OMAP_GPMC_H */ diff --git a/doc/README.nand b/doc/README.nand index 8d73df8..8a4252b 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -170,6 +170,17 @@ Configuration Options: flexibility, so that one day we can eliminate the old mechanism.
+ CONFIG_SYS_NAND_ONFI_DETECTION + Enables detection of ONFI compliant devices during probe. + And fetching device parameters flashed on device, by parsing + ONFI parameter page. + + CONFIG_BCH + Enables software based BCH ECC algorithm present in lib/bch.c + This is used by SoC platforms which do not have built-in ELM + hardware engine required for BCH ECC correction. + + Platform specific options ========================= CONFIG_NAND_OMAP_GPMC diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index c828859..e6b289d 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -15,15 +15,13 @@ #include <linux/bch.h> #include <linux/compiler.h> #include <nand.h> -#ifdef CONFIG_AM33XX #include <asm/omap_elm.h> -#endif + +#define BADBLOCK_MARKER_LENGTH 2 +#define SECTOR_BYTES 512
static uint8_t cs; -static __maybe_unused struct nand_ecclayout hw_nand_oob = - GPMC_NAND_HW_ECC_LAYOUT; -static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = - GPMC_NAND_HW_BCH8_ECC_LAYOUT; +static __maybe_unused struct nand_ecclayout omap_ecclayout;
/* * omap_nand_hwcontrol - Set the address pointers corretly for the @@ -233,6 +231,7 @@ struct nand_bch_priv { uint8_t type; uint8_t nibbles; struct bch_control *control; + enum omap_ecc ecc_scheme; };
/* bch types */ @@ -274,17 +273,15 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) { uint32_t val; uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; -#ifdef CONFIG_AM33XX uint32_t unused_length = 0; -#endif uint32_t wr_mode = BCH_WRAPMODE_6; struct nand_bch_priv *bch = chip->priv;
/* Clear the ecc result registers, select ecc reg as 1 */ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-#ifdef CONFIG_AM33XX - wr_mode = BCH_WRAPMODE_1; + if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) { + wr_mode = BCH_WRAPMODE_1;
switch (bch->nibbles) { case ECC_BCH4_NIBBLES: @@ -320,7 +317,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) val |= (unused_length << 22); break; } -#else + } else { /* * This ecc_size_config setting is for BCH sw library. * @@ -333,7 +330,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) */ val = (32 << 22) | (0 << 12); -#endif + } /* ecc size configuration */ writel(val, &gpmc_cfg->ecc_size_config);
@@ -376,9 +373,9 @@ static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) }
/* - * BCH8 support (needs ELM and thus AM33xx-only) + * BCH support using ELM module */ -#ifdef CONFIG_AM33XX +#ifdef CONFIG_NAND_OMAP_ELM /* * omap_read_bch8_result - Read BCH result for BCH8 level * @@ -631,20 +628,20 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, } return 0; } -#endif /* CONFIG_AM33XX */ +#endif /* CONFIG_NAND_OMAP_ELM */
/* * OMAP3 BCH8 support (with BCH library) */ -#ifdef CONFIG_NAND_OMAP_BCH8 +#ifdef CONFIG_BCH /* - * omap_calculate_ecc_bch - Read BCH ECC result + * omap_calculate_ecc_bch_sw - Read BCH ECC result * * @mtd: MTD device structure * @dat: The pointer to data on which ecc is computed (unused here) * @ecc: The ECC output buffer */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, +static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc) { int ret = 0; @@ -689,13 +686,13 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, }
/** - * omap_correct_data_bch - Decode received data and correct errors + * omap_correct_data_bch_sw - Decode received data and correct errors * @mtd: MTD device structure * @data: page data * @read_ecc: ecc read from nand flash * @calc_ecc: ecc read from HW ECC registers */ -static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, +static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, u_char *read_ecc, u_char *calc_ecc) { int i, count; @@ -752,7 +749,150 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) chip_priv->control = NULL; } } -#endif /* CONFIG_NAND_OMAP_BCH8 */ +#endif /* CONFIG_BCH */ + +/** + * omap_select_ecc_scheme - configures driver for particular ecc-scheme + * @nand: NAND chip device structure + * @ecc_scheme: ecc scheme to configure + * @pagesize: number of main-area bytes per page of NAND device + * @oobsize: number of OOB/spare bytes per page of NAND device + */ +static int omap_select_ecc_scheme(struct nand_chip *nand, + enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { + struct nand_bch_priv *bch = nand->priv; + struct nand_ecclayout *ecclayout = nand->ecc.layout; + int eccsteps = pagesize / SECTOR_BYTES; + int i; + + switch (ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); + /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are + * initialized in nand_scan_tail(), so just set ecc.mode */ + bch_priv.control = NULL; + bch_priv.type = 0; + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = NULL; + nand->ecc.size = pagesize; + bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW; + break; + + case OMAP_ECC_HAM1_CODE_HW: + debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + bch_priv.control = NULL; + bch_priv.type = 0; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 1; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 3; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW; + break; + + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: +#ifdef CONFIG_BCH + debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* check if BCH S/W library can be used for error detection */ + bch_priv.control = init_bch(13, 8, 0x201b); + if (!bch_priv.control) { + printf("nand: error: could not init_bch()\n"); + return -ENODEV; + } + bch_priv.type = ECC_BCH8; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 13; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch_sw; + nand->ecc.calculate = omap_calculate_ecc_bch_sw; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + for (i = 1; i < ecclayout->eccbytes; i++) { + if (i % nand->ecc.bytes) + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 1; + else + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 2; + } + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + omap_hwecc_init_bch(nand, NAND_ECC_READ); + bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; + break; +#else + printf("nand: error: CONFIG_BCH required for ECC\n"); + return -EINVAL; +#endif + + case OMAP_ECC_BCH8_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + bch_priv.type = ECC_BCH8; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 14; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif + + default: + debug("nand: error: ecc scheme not enabled or supported\n"); + return -EINVAL; + } + return 0; +}
#ifndef CONFIG_SPL_BUILD /* @@ -763,77 +903,45 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) * @eccstrength - the number of bits that could be corrected * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) */ -void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) +int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; + int err = 0;
if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[nand_curr_device].name) { - printf("Error: Can't switch ecc, no devices available\n"); - return; + printf("nand: error: no NAND devices found\n"); + return -ENODEV; }
mtd = &nand_info[nand_curr_device]; nand = mtd->priv; - nand->options |= NAND_OWN_BUFFERS; - - /* Reset ecc interface */ - nand->ecc.mode = NAND_ECC_NONE; - nand->ecc.read_page = NULL; - nand->ecc.write_page = NULL; - nand->ecc.read_oob = NULL; - nand->ecc.write_oob = NULL; - nand->ecc.hwctl = NULL; - nand->ecc.correct = NULL; - nand->ecc.calculate = NULL; - nand->ecc.strength = eccstrength; - /* Setup the ecc configurations again */ if (hardware) { if (eccstrength == 1) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - omap_hwecc_init(nand); - printf("1-bit hamming HW ECC selected\n"); - } -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - else if (eccstrength == 8) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = 512; -#ifdef CONFIG_AM33XX - nand->ecc.bytes = 14; - nand->ecc.read_page = omap_read_page_bch; -#else - nand->ecc.bytes = 13; -#endif - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; - omap_hwecc_init_bch(nand, NAND_ECC_READ); - printf("8-bit BCH HW ECC selected\n"); + err = omap_select_ecc_scheme(nand, + OMAP_ECC_HAM1_CODE_HW, + mtd->writesize, mtd->oobsize); + } else if (eccstrength == 8) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_BCH8_CODE_HW, + mtd->writesize, mtd->oobsize); + } else { + printf("nand: error: unsupported ECC scheme\n"); + return -EINVAL; } -#endif } else { - nand->ecc.mode = NAND_ECC_SOFT; - /* Use mtd default settings */ - nand->ecc.layout = NULL; - nand->ecc.size = 0; - printf("SW ECC selected\n"); + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + mtd->writesize, mtd->oobsize); }
/* Update NAND handling after ECC mode switch */ - nand_scan_tail(mtd); - - nand->options &= ~NAND_OWN_BUFFERS; + if (!err) + err = nand_scan_tail(mtd); + return err; } #endif /* CONFIG_SPL_BUILD */
@@ -856,7 +964,7 @@ int board_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; cs = 0; - + int err = 0; /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -873,7 +981,7 @@ int board_nand_init(struct nand_chip *nand) cs++; } if (cs >= GPMC_MAX_CS) { - printf("NAND: Unable to find NAND settings in " + printf("nand: error: Unable to find NAND settings in " "GPMC Configuration - quitting\n"); return -ENODEV; } @@ -885,64 +993,32 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - - nand->cmd_ctrl = omap_nand_hwcontrol; - nand->options = NAND_NO_PADDING | NAND_CACHEPRG; + nand->priv = &bch_priv; + nand->cmd_ctrl = omap_nand_hwcontrol; + nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; /* If we are 16 bit dev, our gpmc config tells us that */ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100; - -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) -#ifdef CONFIG_AM33XX - /* AM33xx uses the ELM */ - /* required in case of BCH */ - elm_init(); -#else - /* - * Whereas other OMAP based SoC do not have the ELM, they use the BCH - * SW library. - */ - bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); - if (!bch_priv.control) { - puts("Could not init_bch()\n"); - return -ENODEV; - } -#endif - /* BCH info that will be correct for SPL or overridden otherwise. */ - nand->priv = &bch_priv; -#endif - - /* Default ECC mode */ -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.strength = 8; - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; -#ifdef CONFIG_AM33XX - nand->ecc.read_page = omap_read_page_bch; -#endif - omap_hwecc_init_bch(nand, NAND_ECC_READ); -#else -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) - nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &omap_ecclayout; + + /* select ECC scheme */ +#if defined(CONFIG_NAND_OMAP_ELM) + err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); +#elif defined(CONFIG_NAND_OMAP_BCH8) + err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); +#elif !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + 0, 0); #else - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - nand->ecc.strength = 1; - omap_hwecc_init(nand); -#endif + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_HW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); #endif + if (err) + return err;
#ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16)
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues.
1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also.
2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library
Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)
Signed-off-by: Pekon Gupta pekon@ti.com --- doc/README.nand | 23 +++++++++++++++++++++++ doc/README.omap3 | 3 +-- drivers/mtd/nand/omap_gpmc.c | 13 ++++--------- include/configs/am335x_evm.h | 3 ++- include/configs/am335x_igep0033.h | 1 + include/configs/am3517_crane.h | 1 + include/configs/am3517_evm.h | 1 + include/configs/devkit8000.h | 1 + include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_evm_quick_nand.h | 1 + include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/siemens-am33x-common.h | 1 + include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 2 +- 17 files changed, 43 insertions(+), 15 deletions(-)
diff --git a/doc/README.nand b/doc/README.nand index 8a4252b..25a4412 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -198,6 +198,29 @@ Platform specific options detection. However ECC calculation on such plaforms would still be done by GPMC controller.
+ CONFIG_NAND_OMAP_ECCSCHEME + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW + 1-bit Hamming code using software lib. + (for legacy devices only) + OMAP_ECC_HAM1_CODE_HW + 1-bit Hamming code using GPMC hardware. + (for legacy devices only) + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH4_CODE_HW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using software library. + - requires CONFIG_BCH to enable software BCH library + (For legacy device which do not have ELM h/w engine) + OMAP_ECC_BCH8_CODE_HW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using ELM hardware engine.
NOTE: ===== diff --git a/doc/README.omap3 b/doc/README.omap3 index 1fbe79d..a62c357 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -161,8 +161,7 @@ BCH8
To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH -to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted -syndrom generation to your board config. +and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW. The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8 implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index e6b289d..5e7e6b3 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -1004,18 +1004,13 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.layout = &omap_ecclayout;
/* select ECC scheme */ -#if defined(CONFIG_NAND_OMAP_ELM) - err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW, +#if defined(CONFIG_NAND_OMAP_ECCSCHEME) + err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); -#elif defined(CONFIG_NAND_OMAP_BCH8) - err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); -#elif !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) +#else + /* pagesize and oobsize are not required to configure sw ecc-scheme */ err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, 0, 0); -#else - err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_HW, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); #endif if (err) return err; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 4c79ddb..d75df92 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -239,7 +239,8 @@
#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 - +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 88ced73..115d1b3 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -264,6 +264,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 6fd3fb9..468fb43 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -340,6 +340,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 7e9c55e..a3473b5 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -334,6 +334,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 474a568..4f43ba9 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -327,6 +327,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mcx.h b/include/configs/mcx.h index a2f7cf7..dcd29ce 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -353,7 +353,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT @@ -395,6 +394,7 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index bba39d4..9eab190 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -431,6 +431,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 3ace8bb..b7638fb 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -107,6 +107,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 9ecd70d..4427e88 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -86,6 +86,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 75d7d70..71062a6 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -362,6 +362,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 84b4aee..e0f0262 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -324,6 +324,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 85d6dc2..f37653f 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -195,6 +195,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCSTEPS 4 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 6112c1b..439fc47 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -224,7 +224,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_CONSOLE #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
#define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -261,6 +260,7 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index afd8707..b38b955 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -138,7 +138,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_NAND_OMAP_BCH8 #define CONFIG_BCH
/* commands to include */ @@ -374,6 +373,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot.
Signed-off-by: Pekon Gupta pekon@ti.com --- arch/arm/cpu/armv7/am33xx/mem.c | 52 +++++++++++++++++++--------------- arch/arm/include/asm/arch-am33xx/mem.h | 5 ---- board/ti/am335x/board.c | 14 +-------- 3 files changed, 30 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index b6eb466..56c9e7d 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -22,17 +22,6 @@
struct gpmc *gpmc_cfg;
-#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif -
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) @@ -61,11 +50,34 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#ifdef CONFIG_CMD_NAND - const u32 *gpmc_config = NULL; - u32 base = 0; +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; u32 size = 0; + u32 base = 0; #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); @@ -81,12 +93,6 @@ void gpmc_init(void) */ writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); - -#ifdef CONFIG_CMD_NAND - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 983ea28..e7e8c58 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -68,9 +68,4 @@ #define PISMO2_NAND_CS0 7 #define PISMO2_NAND_CS1 8
-/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE -#define PISMO1_NAND_SIZE GPMC_SIZE_256M - #endif /* endif _MEM_H_ */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 8edd21b..db225ce 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -481,26 +481,14 @@ void sdram_init(void) */ int board_init(void) { -#ifdef CONFIG_NOR - const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; -#endif - #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); - -#ifdef CONFIG_NOR - /* Reconfigure CS0 for NOR instead of NAND. */ - enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], - CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); #endif - return 0; }
On Thu, Nov 21, 2013 at 10:41:59AM +0530, Pekon Gupta wrote:
*changes in v11* [PATCH 2/4] fixed 'unused variable' warning
If this is the only thing that changed, and the fix was just to remove the bch variable, I'll keep the v10 patches that I've already applied locally with the fix.
-Scott
From: Scott Wood [mailto:scottwood@freescale.com]
On Thu, Nov 21, 2013 at 10:41:59AM +0530, Pekon Gupta wrote:
*changes in v11* [PATCH 2/4] fixed 'unused variable' warning
If this is the only thing that changed, and the fix was just to remove the bch variable, I'll keep the v10 patches that I've already applied locally with the fix.
Yes, this is the only change.. Thank you for accepting ..
with regards, pekon
participants (3)
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Gupta, Pekon -
Pekon Gupta
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Scott Wood