From: Wan Yee Lau wan.yee.lau@intel.com

Add platform related files for new platform Agilex7 M-series.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- arch/arm/mach-socfpga/include/mach/misc.h | 3 +- .../{spl_agilex.c => spl_agilex7m.c} | 45 ++++++++++++------- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 ++ board/intel/agilex7m-socdk/MAINTAINERS | 7 +++ board/intel/agilex7m-socdk/socfpga.c | 4 ++ 5 files changed, 45 insertions(+), 18 deletions(-) copy arch/arm/mach-socfpga/{spl_agilex.c => spl_agilex7m.c} (68%) create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS create mode 100644 board/intel/agilex7m-socdk/socfpga.c

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 8460acb00d..e271d2855f 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,7 +40,8 @@ void socfpga_sdram_remap_zero(void); #endif

#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) + defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif

diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex7m.c similarity index 68% copy from arch/arm/mach-socfpga/spl_agilex.c copy to arch/arm/mach-socfpga/spl_agilex7m.c index ee5a9dc1e2..ee41db8884 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -1,26 +1,25 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> - * + * Copyright (C) 2024 Intel Corporation <www.intel.com> */

-#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include <asm/utils.h> #include <common.h> #include <hang.h> #include <image.h> +#include <init.h> +#include <log.h> #include <spl.h> +#include <wdt.h> #include <asm/arch/clock_manager.h> #include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> #include <dm/uclass.h>

DECLARE_GLOBAL_DATA_PTR; @@ -40,13 +39,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);

-#ifdef CONFIG_HW_WATCHDOG - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR);

@@ -60,11 +52,30 @@ void board_init_f(ulong dummy) hang(); }

+ /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary();

- firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 6aa9bb26b4..8c06b3d59e 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -39,6 +39,10 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC: debug("%s: PHY engine handoff data\n", __func__); return LITTLE_ENDIAN; +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) + case SOC64_HANDOFF_MAGIC_DDR: + debug("%s: SOC64_HANDOFF_MAGIC_DDR\n", __func__); + return BIG_ENDIAN; #endif default: debug("%s: Unknown endianness!!\n", __func__); diff --git a/board/intel/agilex7m-socdk/MAINTAINERS b/board/intel/agilex7m-socdk/MAINTAINERS new file mode 100644 index 0000000000..feb2916488 --- /dev/null +++ b/board/intel/agilex7m-socdk/MAINTAINERS @@ -0,0 +1,7 @@ +SOCFPGA BOARD +M: Tien Fong Chee tien.fong.chee@intel.com +M: Teik Heng Chong teik.heng.chong@intel.com +S: Maintained +F: board/intel/agilex7m-socdk/ +F: include/configs/socfpga_agilex7m_socdk.h +F: configs/socfpga_agilex7m_sdmmc_defconfig diff --git a/board/intel/agilex7m-socdk/socfpga.c b/board/intel/agilex7m-socdk/socfpga.c new file mode 100644 index 0000000000..52921d90aa --- /dev/null +++ b/board/intel/agilex7m-socdk/socfpga.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */

From: Wan Yee Lau wan.yee.lau@intel.com

Handoff settings updated for new platform Agilex7 M-series.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f28841..747016b436 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -28,10 +28,20 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096

-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x62C) +/* DDR handoff */ +#define SOC64_HANDOFF_MAGIC_DDR 0x5344524D +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 2 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)

From: Siew Chin Lim elly.siew.chin.lim@intel.com

ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command.

Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper.

Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- arch/arm/Kconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e1933..56e190adf6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -21,6 +21,9 @@ config ARM64_CRC32 not be present on all ARMv8.0, but is always present on ARMv8.1 and newer.

+config BOOTFILE + default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 + config COUNTER_FREQUENCY int "Timer clock frequency" depends on ARM64 || CPU_V7A

From: Wan Yee Lau wan.yee.lau@intel.com

Add iossm mailbox driver for Agilex7 M-series. HPS will interact with IO96B and DDR subsystem through software defined mailbox interface. HPS can retrieve memory interface calibration status, IO96B configuration, memory interfae configuration, trigger calibration and etc with the list of supported mailbox command type and opcode.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- drivers/ddr/altera/iossm_mailbox.c | 637 +++++++++++++++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 182 +++++++++ 2 files changed, 819 insertions(+) create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h

diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c new file mode 100644 index 0000000000..f84a3a070d --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include <hang.h> +#include <string.h> +#include <wait_bit.h> +#include <asm/arch/base_addr_soc64.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include "iossm_mailbox.h" + +#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C +#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0 +#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16) +#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17) + +#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(x) (i == 0 ? DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \ + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK) + +#define IO96B_MB_REQ_SETUP(v, w, x, y, z) usr_req.ip_type = v; \ + usr_req.ip_id = w; \ + usr_req.usr_cmd_type = x; \ + usr_req.usr_cmd_opcode = y; \ + usr_req.cmd_param[0] = z; \ + for (n = 1; n < NUM_CMD_PARAM; n++) \ + usr_req.cmd_param[n] = 0 +#define MAX_RETRY_COUNT 3 + +#define IO96B0_PLL_A_MASK BIT(0) +#define IO96B0_PLL_B_MASK BIT(1) +#define IO96B1_PLL_A_MASK BIT(2) +#define IO96B1_PLL_B_MASK BIT(3) + +/* supported DDR type list */ +static const char *ddr_type_list[7] = { + "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN" +}; + +static int is_ddr_csr_clkgen_locked(u8 io96b_pll) +{ + int ret = 0; + + if (FIELD_GET(IO96B0_PLL_A_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_0 clkgenA locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B0_PLL_B_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_0 clkgenB locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B1_PLL_A_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_1 clkgenA locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B1_PLL_B_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_1 clkgenB locked is timeout\n", __func__); + goto err; + } + } + +err: + return ret; +} + +/* Mailbox request function + * This function will send the request to IOSSM mailbox and wait for response return + * + * @io96b_csr_addr: CSR address for the target IO96B + * @req: Structure contain command request for IOSSM mailbox command + * @resp_data_len: User desire extra response data fields other than + * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS + * @resp: Structure contain responses returned from the requested IOSSM + * mailbox command + */ +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp) +{ + int i, ret; + u32 cmd_req, cmd_resp; + + /* Initialized zeros for responses */ + resp->cmd_resp_status = 0; + for (i = 0; i < NUM_CMD_RESPONSE_DATA; i++) + resp->cmd_resp_data[i] = 0; + + /* Ensure CMD_REQ is cleared before write any command request */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET), + GENMASK(31, 0), 0, TIMEOUT, false); + if (ret) { + printf("%s: CMD_REQ not ready\n", __func__); + + return ret; + } + + /* Write CMD_PARAM_* */ + for (i = 0; i < NUM_CMD_PARAM ; i++) { + switch (i) { + case 0: + if (req.cmd_param[0]) + writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET); + break; + case 1: + if (req.cmd_param[1]) + writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET); + break; + case 2: + if (req.cmd_param[2]) + writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET); + break; + case 3: + if (req.cmd_param[3]) + writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET); + break; + case 4: + if (req.cmd_param[4]) + writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET); + break; + case 5: + if (req.cmd_param[5]) + writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET); + break; + case 6: + if (req.cmd_param[6]) + writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET); + break; + default: + printf("%s: Invalid command parameter\n", __func__); + } + } + + /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) | + FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) | + FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode); + writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, + io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY, 1, TIMEOUT, false); + if (ret) { + printf("%s: CMD_RESPONSE ERROR:\n", __func__); + + cmd_resp = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_GENERAL_ERROR(cmd_resp)); + printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(cmd_resp)); + } + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* read CMD_RESPONSE_DATA_* */ + for (i = 0; i < resp_data_len; i++) { + switch (i) { + case 0: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET, + resp->cmd_resp_data[i]); + break; + case 1: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET, + resp->cmd_resp_data[i]); + break; + case 2: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET, + resp->cmd_resp_data[i]); + break; + default: + printf("%s: Invalid response data\n", __func__); + } + } + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* write CMD_RESPONSE_READY = 0 */ + clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY); + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_READY 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + return 0; +} + +/* + * Initial function to be called to set memory interface IP type and instance ID + * IP type and instance ID need to be determined before sending mailbox command + */ +void io96b_mb_init(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + u8 ip_type_ret, instance_id_ret; + int i, j, k, n; + + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + debug("%s: get memory interface IO96B %d\n", __func__, i); + + IO96B_MB_REQ_SETUP(0, + 0, + CMD_GET_SYS_INFO, + GET_MEM_INTF_INFO, + 0); + + /* Get memory interface IP type and instance ID (IP identifier) */ + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 2, &usr_resp); + + debug("%s: get response from memory interface IO96B %d\n", __func__, i); + + /* Retrieve number of memory interface(s) */ + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3; + + debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i, + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface); + + /* Retrieve memory interface IP type and instance ID (IP identifier) */ + j = 0; + for (k = 0; k < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; k++) { + ip_type_ret = FIELD_GET(INTF_IP_TYPE_MASK, usr_resp.cmd_resp_data[k]); + instance_id_ret = FIELD_GET(INTF_INSTANCE_ID_MASK, + usr_resp.cmd_resp_data[k]); + + if (ip_type_ret) { + io96b_ctrl->io96b[i].mb_ctrl.ip_type[j] = ip_type_ret; + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j] = instance_id_ret; + + debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n", + __func__, i, j, ip_type_ret); + debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n", + __func__, i, j, instance_id_ret); + + j++; + } + } + } +} + +int io96b_cal_status(phys_addr_t addr) +{ + int ret; + u32 cal_success, cal_fail; + phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET; + + /* Ensure calibration completed */ + ret = wait_for_bit_le32((const void *)status_addr, IOSSM_STATUS_CAL_BUSY, false, + TIMEOUT, false); + if (ret) { + printf("%s: SDRAM calibration IO96b instance 0x%llx timeout\n", __func__, + status_addr); + + hang(); + } + + /* Calibration status */ + cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS; + cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL; + + if (cal_success && !cal_fail) + return 0; + else + return -EPERM; +} + +void init_mem_cal(struct io96b_info *io96b_ctrl) +{ + int count, i, ret; + + /* Initialize overall calibration status */ + io96b_ctrl->overall_cal_status = false; + + if (io96b_ctrl->ckgen_lock) { + ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll); + if (ret) { + printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__); + hang(); + } + } + + /* Check initial calibration status for the assigned IO96B */ + count = 0; + for (i = 0; i < io96b_ctrl->num_instance; i++) { + ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b[i].cal_status = false; + + printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__, + i, ret); + + hang(); + } + + io96b_ctrl->io96b[i].cal_status = true; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + + if (count == io96b_ctrl->num_instance) + io96b_ctrl->overall_cal_status = true; +} + +/* Trying 3 times re-calibration if initial calibration failed */ +int trig_mem_cal(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + bool recal_success; + int i, j, k, n; + u32 cal_stat_offset; + u8 cal_stat, trig_cal_stat; + int count = 0; + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + if (!io96b_ctrl->io96b[i].cal_status) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + /* Get the memory calibration status for memory interface */ + IO96B_MB_REQ_SETUP(0, + 0, + CMD_TRIG_MEM_CAL_OP, + GET_MEM_CAL_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + recal_success = false; + + /* Re-calibration first memory interface with failed calibration */ + for (k = 0; k < MAX_RETRY_COUNT; k++) { + cal_stat_offset = usr_resp.cmd_resp_data[j]; + cal_stat = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + cal_stat_offset); + if (cal_stat == INTF_MEM_CAL_STATUS_SUCCESS) { + recal_success = true; + break; + } + + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_MEM_CAL_OP, + TRIG_MEM_CAL, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + trig_cal_stat = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & + BIT(0); + + debug("%s: Memory calibration triggered status = %d\n", + __func__, trig_cal_stat); + + udelay(1); + + IO96B_MB_REQ_SETUP(0, + 0, + CMD_TRIG_MEM_CAL_OP, + GET_MEM_CAL_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + + hang(); + } + } + + io96b_ctrl->io96b[i].cal_status = true; + io96b_ctrl->overall_cal_status = io96b_ctrl->io96b[i].cal_status; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + } + + if (io96b_ctrl->overall_cal_status) + debug("%s: Overall SDRAM calibration success\n", __func__); + + return 0; +} + +int get_mem_technology(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + u8 ddr_type_ret; + + /* Initialize ddr type */ + io96b_ctrl->ddr_type = ddr_type_list[6]; + + /* Get and ensure all memory interface(s) same DDR type */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, + GET_MEM_TECHNOLOGY, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + ddr_type_ret = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 0); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i); + + return -EINVAL; + } + } + } + + return 0; +} + +int get_mem_width_info(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + u16 memory_size; + u16 total_memory_size = 0; + + /* Get all memory interface(s) total memory size on all instance(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, + GET_MEM_WIDTH_INFO, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + memory_size = memory_size + + (usr_resp.cmd_resp_data[1] & GENMASK(7, 0)); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + + return -EINVAL; + } + + io96b_ctrl->io96b[i].size = memory_size; + + total_memory_size = total_memory_size + memory_size; + } + + if (!total_memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + + return -EINVAL; + } + + io96b_ctrl->overall_size = total_memory_size; + + return 0; +} + +int ecc_enable_status(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + bool ecc_stat_set = false; + bool ecc_stat; + + /* Initialize ECC status */ + io96b_ctrl->ecc_status = false; + + /* Get and ensure all memory interface(s) same ECC status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + ECC_ENABLE_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + ecc_stat = (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(1, 0)) == 0 ? false : true; + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); + + return -EINVAL; + } + } + } + + debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status); + + return 0; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + bool bist_start, bist_success; + u32 start; + + /* Full memory initialization BIST performed on all memory interface(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + BIST_MEM_INIT_START, + BIST_FULL_MEM); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + i); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + return -EINVAL; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + BIST_MEM_INIT_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, + &usr_resp); + + bist_success = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, i); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + return -ETIMEDOUT; + } + + udelay(1); + } + } + + debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i); + } + return 0; +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h new file mode 100644 index 0000000000..2a10b0dba6 --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT TIMEOUT_120000MS +#define IOSSM_STATUS_CAL_SUCCESS BIT(0) +#define IOSSM_STATUS_CAL_FAIL BIT(1) +#define IOSSM_STATUS_CAL_BUSY BIT(2) +#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0) +#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C +#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 +#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 +#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 +#define IOSSM_CMD_REQ_OFFSET 0x43C +#define IOSSM_CMD_PARAM_0_OFFSET 0x438 +#define IOSSM_CMD_PARAM_1_OFFSET 0x434 +#define IOSSM_CMD_PARAM_2_OFFSET 0x430 +#define IOSSM_CMD_PARAM_3_OFFSET 0x42C +#define IOSSM_CMD_PARAM_4_OFFSET 0x428 +#define IOSSM_CMD_PARAM_5_OFFSET 0x424 +#define IOSSM_CMD_PARAM_6_OFFSET 0x420 +#define IOSSM_STATUS_OFFSET 0x400 +#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define IOSSM_CMD_RESPONSE_DATA_SHORT(n) FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) +#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) +#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define MAX_IO96B_SUPPORTED 2 +#define NUM_CMD_RESPONSE_DATA 3 +#define NUM_CMD_PARAM 6 + +/* supported mailbox command type */ +enum iossm_mailbox_cmd_type { + CMD_NOP, + CMD_GET_SYS_INFO, + CMD_GET_MEM_INFO, + CMD_GET_MEM_CAL_INFO, + CMD_TRIG_CONTROLLER_OP, + CMD_TRIG_MEM_CAL_OP +}; + +/* supported mailbox command opcode */ +enum iossm_mailbox_cmd_opcode { + GET_MEM_INTF_INFO = 0x0001, + GET_MEM_TECHNOLOGY, + GET_MEMCLK_FREQ_KHZ, + GET_MEM_WIDTH_INFO, + ECC_ENABLE_SET = 0x0101, + ECC_ENABLE_STATUS, + ECC_INTERRUPT_STATUS, + ECC_INTERRUPT_ACK, + ECC_INTERRUPT_MASK, + ECC_WRITEBACK_ENABLE, + ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, + ECC_SCRUB_MODE_0_START, + ECC_SCRUB_MODE_1_START, + BIST_STANDARD_MODE_START = 0x0301, + BIST_RESULTS_STATUS, + BIST_MEM_INIT_START, + BIST_MEM_INIT_STATUS, + BIST_SET_DATA_PATTERN_UPPER, + BIST_SET_DATA_PATTERN_LOWER, + TRIG_MEM_CAL = 0x000a, + GET_MEM_CAL_STATUS +}; + +/* response data of cmd opcode GET_MEM_INTF_INFO */ +#define INTF_IP_TYPE_MASK GENMASK(31, 29) +#define INTF_INSTANCE_ID_MASK GENMASK(28, 24) + +/* response data of cmd opcode GET_MEM_CAL_STATUS */ +#define INTF_UNUSED 0x0 +#define INTF_MEM_CAL_STATUS_SUCCESS 0x1 +#define INTF_MEM_CAL_STATUS_FAIL 0x2 +#define INTF_MEM_CAL_STATUS_ONGOING 0x4 + +/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ +#define BIST_FULL_MEM BIT(6) + +/* + * IOSSM mailbox required information + * + * @num_mem_interface: Number of memory interfaces instantiated + * @ip_type: IP type implemented on the IO96B + * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + */ +struct io96b_mb_ctrl { + u32 num_mem_interface; + u32 ip_type[2]; + u32 ip_id[2]; +}; + +/* CMD_REQ Register Definition */ +#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) +#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* + * IOSSM mailbox request + * @ip_type: IP type for the specified memory interface + * @ip_id: IP instance ID for the specified memory interface + * @usr_cmd_type: User desire IOSSM mailbox command type + * @usr_cmd_opcode: User desire IOSSM mailbox command opcode + * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command + */ +struct io96b_mb_req { + u32 ip_type; + u32 ip_id; + u32 usr_cmd_type; + u32 usr_cmd_opcode; + u32 cmd_param[NUM_CMD_PARAM]; +}; + +/* + * IOSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + * @cmd_resp_data_*: More spaces for command response + */ +struct io96b_mb_resp { + u32 cmd_resp_status; + u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA]; +}; + +/* + * IO96B instance specific information + * + * @size: Memory size + * @io96b_csr_addr: IO96B instance CSR address + * @cal_status: IO96B instance calibration status + * @mb_ctrl: IOSSM mailbox required information + */ +struct io96b_instance { + u16 size; + phys_addr_t io96b_csr_addr; + bool cal_status; + struct io96b_mb_ctrl mb_ctrl; +}; + +/* + * Overall IO96B instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all IO96B instance(s) + * @ddr_type: DDR memory type + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total DDR memory size + * @io96b[]: IO96B instance specific information + * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) + * @num_port: Number of IO96B port. Example bit 0 represent port 0, bit 1 represent port 1, and so on + * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected, + * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected, + * bit 3: EMIF1 PLL B selected + */ +struct io96b_info { + u8 num_instance; + bool overall_cal_status; + const char *ddr_type; + bool ecc_status; + u16 overall_size; + struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; + bool ckgen_lock; + u8 num_port; + u8 io96b_pll; +}; + +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp); + +/* Supported IOSSM mailbox function */ +void io96b_mb_init(struct io96b_info *io96b_ctrl); +int io96b_cal_status(phys_addr_t addr); +void init_mem_cal(struct io96b_info *io96b_ctrl); +int trig_mem_cal(struct io96b_info *io96b_ctrl); +int get_mem_technology(struct io96b_info *io96b_ctrl); +int get_mem_width_info(struct io96b_info *io96b_ctrl); +int ecc_enable_status(struct io96b_info *io96b_ctrl); +int bist_mem_init_start(struct io96b_info *io96b_ctrl);

From: Wan Yee Lau wan.yee.lau@intel.com

This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- .../include/mach/base_addr_soc64.h | 6 +- .../include/mach/system_manager_soc64.h | 7 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex7m.c | 527 ++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 15 +- drivers/ddr/altera/sdram_soc64.h | 15 +- 6 files changed, 565 insertions(+), 8 deletions(-) create mode 100644 drivers/ddr/altera/sdram_agilex7m.c

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2..1f935fcdec 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -45,12 +45,15 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -74,6 +77,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fe..815bdf8ce1 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2024 Intel Corporation <www.intel.com> */

#ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -103,6 +103,11 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28

+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC

#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27..1dac088b39 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2010, Thomas Chou thomas@wytron.com.tw -# Copyright (C) 2014-2021 Altera Corporation <www.altera.com> +# Copyright (C) 2014-2024 Altera Corporation <www.altera.com>

ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o @@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c new file mode 100644 index 0000000000..4d585501e6 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include <dm.h> +#include <hang.h> +#include <log.h> +#include <ram.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/arch/system_manager.h> +#include <linux/bitfield.h> +#include "iossm_mailbox.h" +#include "uibssm_mailbox.h" +#include "sdram_soc64.h" + +/* NOCPLL register */ +#define SYSMGR_HMC_CLK 0xB4 +#define SYSMGR_HMC_CLK_NOCPLL BIT(8) + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 + +#define SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL BIT(4) +#define SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING BIT(5) + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +phys_addr_t io96b_csr_reg_addr[] = { + 0xf8400000, /* IO96B_0 CSR registers address */ + 0xf8800000 /* IO96B_1 CSR registers address */ +}; + +phys_addr_t uib_csr_reg_addr[] = { + 0xf8400000, /* UIB_0 CSR registers address */ + 0xf8410000, /* UIB_1 CSR registers address */ + 0xf8420000, /* UIB_2 CSR registers address */ + 0xf8430000, /* UIB_3 CSR registers address */ + 0xf8440000, /* UIB_4 CSR registers address */ + 0xf8450000, /* UIB_5 CSR registers address */ + 0xf8460000, /* UIB_6 CSR registers address */ + 0xf8470000 /* UIB_7 CSR registers address */ +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK, reg); +} + +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + debug("%s: 0x%x\n", __func__, reg); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK) + return true; + + return false; +} + +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); +} + +static const char *memory_type_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? "DDR" : "HBM"); +} + +static bool is_ddr_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? true : false); +} + +void update_uib_assigned_to_hps(u8 num_uib_instance) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + reg = reg & ~ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK; + + writel(reg | FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK, num_uib_instance), + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); +} + +void update_io96b_assigned_to_hps(u8 num_io96b_instance) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + reg = reg & ~ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK; + + writel(reg | FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK, num_io96b_instance), + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); +} + +int populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl, + struct uib_info *uib_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + int i; + u8 count = 0; + u32 len = SOC64_HANDOFF_DDR_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_DDR_BASE, handoff_table, len); + + /* Interleaving Mode */ + if (handoff_table[0] & SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK) + plat->multichannel_interleaving = true; + else + plat->multichannel_interleaving = false; + + debug("%s: MPFE-EMIF is in %s mode\n", __func__, + plat->multichannel_interleaving ? "interleaving" : "multichannel"); + + /* Memory type */ + if (handoff_table[2] & SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK) + plat->mem_type = HBM_MEMORY; + else + plat->mem_type = DDR_MEMORY; + + debug("%s: Memory type is %s\n", __func__, plat->mem_type ? "HBM" : "DDR"); + + if (plat->mem_type == HBM_MEMORY) { + /* Assign UIB CSR base address if it is valid */ + for (i = 0; i < MAX_UIB_SUPPORTED; i++) { + if (handoff_table[3] & BIT(i)) { + uib_ctrl->uib[i].uib_csr_addr = uib_csr_reg_addr[i]; + + debug("%s: UIB 0x%llx CSR enabled\n", __func__, + uib_ctrl->uib[i].uib_csr_addr); + + count++; + } + } + + uib_ctrl->num_instance = count; + update_uib_assigned_to_hps(count); + + debug("%s: returned num_instance 0x%x\n", __func__, uib_ctrl->num_instance); + + /* + * HBM memory size + * 1 UIB channel has 2 pseudo channels + * 1 pseudo channel is 1GB, hence 1 UIB channel is 2GB + */ + uib_ctrl->overall_size = uib_ctrl->num_instance * SZ_2G; + + /* UIB ECC status */ + uib_ctrl->ecc_status = handoff_table[4]; + + debug("%s: ECC status 0x%x\n", __func__, uib_ctrl->ecc_status); + } else { + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < MAX_IO96B_SUPPORTED; i++) { + if (handoff_table[1] & BIT(i)) { + io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i]; + + debug("%s: IO96B 0x%llx CSR enabled\n", __func__, + io96b_ctrl->io96b[i].io96b_csr_addr); + + count++; + } + } + + io96b_ctrl->num_instance = count; + + update_io96b_assigned_to_hps(count); + + debug("%s: returned num_instance 0x%x\n", __func__, io96b_ctrl->num_instance); + } + + return 0; +} + +int config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + u32 reg, mask; + int ret = 0; + + if (plat->multichannel_interleaving) { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } else { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } + + reg = readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG); + + debug("%s: F2SDRAM_SIDEBAND_FLAGOUTSTATUS0: 0x%x\n", __func__, reg); + + if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING) + debug("%s: Interleaving bit is set\n", __func__); + else if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL) + debug("%s: Multichannel bit is set\n", __func__); + else + ret = -EINVAL; + + return ret; +} + +bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK) + return true; + + return false; +} + +bool ddr_ecc_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + struct uib_info *uib_ctrl = malloc(sizeof(*uib_ctrl)); + struct bd_info bd = {0}; + bool full_mem_init = false; + phys_size_t hw_size; + int ret = 0; + int i; + u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + enum reset_type reset_t = get_reset_type(reg); + + /* Populating DDR handoff data */ + debug("DDR: Populating DDR handoff\n"); + + ret = populate_ddr_handoff(dev, io96b_ctrl, uib_ctrl); + if (ret) { + printf("DDR: Failed to populate DDR handoff\n"); + + goto err; + } + + debug("%s: Address MPFE 0x%llx\n", memory_type_in_use(dev), plat->mpfe_base_addr); + + /* DDR initialization progress status tracking */ + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); + + printf("%s: SDRAM init in progress ...\n", memory_type_in_use(dev)); + + ddr_init_inprogress(true); + + if (is_ddr_in_use(dev)) { + /* Configure if polling is needed for IO96B GEN PLL locked */ + io96b_ctrl->ckgen_lock = false; + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + } + + /* Configuring MPFE sideband manager registers - multichannel or interleaving */ + debug("%s: MPFE configuration in progress ...\n", memory_type_in_use(dev)); + + ret = config_mpfe_sideband_mgr(dev); + if (ret) { + printf("%s: Failed to configure multichannel/interleaving mode\n", + memory_type_in_use(dev)); + + goto err; + } + + debug("%s: MPFE configuration completed\n", memory_type_in_use(dev)); + + debug("%s: Waiting for NOCPLL locked ...\n", memory_type_in_use(dev)); + + /* Ensure NOCPLL locked */ + ret = wait_for_bit_le32((const void *)socfpga_get_sysmgr_addr() + SYSMGR_HMC_CLK + , SYSMGR_HMC_CLK_NOCPLL, true, TIMEOUT, false); + if (ret) { + printf("%s: NOCPLL is not locked\n", memory_type_in_use(dev)); + + goto err; + } + + debug("%s: NOCPLL locked\n", memory_type_in_use(dev)); + + debug("%s: Checking calibration...\n", memory_type_in_use(dev)); + + if (is_ddr_in_use(dev)) { + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* Need to trigger re-calibration for DDR DBE */ + if (ddr_ecc_dbe_status()) { + for (i = 0; i < io96b_ctrl->num_instance; i++) + io96b_ctrl->io96b[i].cal_status = false; + + io96b_ctrl->overall_cal_status &= io96b_ctrl->io96b[i].cal_status; + } + + /* Trigger re-calibration if calibration failed */ + if (!(io96b_ctrl->overall_cal_status)) { + printf("DDR: Re-calibration in progress...\n"); + + trig_mem_cal(io96b_ctrl); + } + + printf("DDR: Calibration success\n"); + + /* DDR type */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + + goto err; + } + + /* DDR size */ + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + + goto err; + } + } else { + /* Ensure calibration status passing */ + uib_init_mem_cal(uib_ctrl); + + /* Need to trigger re-calibration for HBM DBE */ + if (ddr_ecc_dbe_status()) { + for (i = 0; i < uib_ctrl->num_instance; i++) + uib_ctrl->uib[i].cal_status = false; + + uib_ctrl->overall_cal_status = false; + } + + /* Trigger re-calibration if calibration failed */ + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Re-calibration in progress...\n"); + + uib_trig_mem_cal(uib_ctrl); + } + + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Retry calibration failed & not able to re-calibrate\n"); + + ret = -EINVAL; + goto err; + } + + debug("HBM: Setting Error Mask Register\n"); + + /* Responder Error Mask Register */ + for (i = 0; i < uib_ctrl->num_instance; i++) { + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH0 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET); + + debug("HBM: Error Mask Pseudo CH0 value: 0x%x\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET)); + + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH1 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET); + + debug("HBM: Error Mask Pseudo CH1 value: 0x%x\n\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET)); + } + + printf("HBM: Calibration success\n"); + } + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); + + goto err; + } + + if (!is_ddr_in_use(dev)) + hw_size = uib_ctrl->overall_size; + else + hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + + if (gd->ram_size != hw_size) { + printf("%s: Warning: DRAM size from device tree (%lld MiB)\n", + memory_type_in_use(dev), gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("%s: Error: DRAM size from device tree is greater\n", + memory_type_in_use(dev)); + printf(" than hardware size.\n"); + + hang(); + } + + printf("%s: %lld MiB\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM"), + gd->ram_size >> 20); + + if (is_ddr_in_use(dev)) { + /* ECC status */ + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR ECC status\n"); + + goto err; + } + + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("%s: Needed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("%s: Failed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + goto err; + } + } + } + } else { + debug("HBM: ECC enable status: %d\n", uib_ctrl->ecc_status); + + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (uib_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("HBM: Needed to fully initialize HBM memory\n"); + + ret = uib_bist_mem_init_start(uib_ctrl); + if (ret) { + printf("HBM: Failed to fully initialize HBM memory\n"); + + goto err; + } + } + } + } + + /* Ensure sanity memory test passing */ + sdram_size_check(&bd); + + printf("%s: size check success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + sdram_set_firewall(&bd); + + printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("%s init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + +err: + free(io96b_ctrl); + free(uib_ctrl); + + return ret; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 4716abfc9a..a0cc9be25e 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> - * + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> */

#include <common.h> @@ -28,6 +27,7 @@

#define PGTABLE_OFF 0x4000

+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -99,6 +99,7 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: %s triggered successly\n", __func__); return 0; } +#endif

#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) int poll_hmc_clock_status(void) @@ -322,7 +323,12 @@ static int altera_sdram_of_to_plat(struct udevice *dev) /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#endif +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->mpfe_base_addr = addr; +#else

addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) @@ -338,7 +344,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->hmc = (void __iomem *)addr; - +#endif return 0; }

@@ -385,6 +391,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "altr,sdr-ctl-s10" }, { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, + { .compatible = "intel,sdr-ctl-agilex7m" }, { /* sentinel */ } };

diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 87a70a861b..02019ac9e5 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> */

#ifndef _SDRAM_SOC64_H_ @@ -13,11 +13,24 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; };

+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +enum memory_type { + DDR_MEMORY = 0, + HBM_MEMORY +}; + +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool multichannel_interleaving; + enum memory_type mem_type; +}; +#else struct altera_sdram_plat { void __iomem *hmc; void __iomem *ddr_sch; void __iomem *iomhc; }; +#endif

/* ECC HMC registers */ #define DDRIOCTRL 0x8

From: Teik Heng Chong teik.heng.chong@intel.com

Clean up bit-shift by zero bit

Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- drivers/ddr/altera/sdram_soc64.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 02019ac9e5..add7df01a5 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -92,7 +92,7 @@ struct altera_sdram_plat { #define NIOSRESERVED2 0x118

#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ (((x) >> 5) & 0x1F) #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ @@ -103,7 +103,7 @@ struct altera_sdram_plat { (((x) >> 16) & 0x7)

#define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) + ((x) & 0xF) #define CTRLCFG0_CFG_DIMM_TYPE(x) \ (((x) >> 4) & 0x7) #define CTRLCFG0_CFG_AC_POS(x) \ @@ -112,17 +112,17 @@ struct altera_sdram_plat { (((x) >> 9) & 0x1F)

#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define CTRLCFG1_CFG_ADDR_ORDER(x) \ (((x) >> 5) & 0x3) #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1)

#define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) + ((x) & 0x7F)

#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING0_CFG_ACT_TO_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING0_CFG_ACT_TO_ACT(x) \ @@ -131,7 +131,7 @@ struct altera_sdram_plat { (((x) >> 18) & 0x3F)

#define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ (((x) >> 6) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ @@ -142,7 +142,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)

#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ @@ -153,7 +153,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)

#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD(x) \ (((x) >> 6) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ @@ -164,7 +164,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)

#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING4_CFG_PCH_TO_VALID(x) \ (((x) >> 6) & 0x3F) #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ @@ -175,7 +175,7 @@ struct altera_sdram_plat { (((x) >> 26) & 0x3F)

#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) + ((x) & 0xFF)

/* Firewall DDR scheduler MPFE */ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004

From: Wan Yee Lau wan.yee.lau@intel.com

Update Kconfig for new platform Agilex7 M-series.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- arch/arm/Kconfig | 4 +++- arch/arm/mach-socfpga/Kconfig | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 56e190adf6..f68b680d82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -32,7 +32,9 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 400000000 if ARCH_SOCFPGA && ARM64 && !TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232cac..2ca6336f21 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -59,6 +59,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64

+config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -139,6 +151,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX

+config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -216,6 +232,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice

config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -238,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA

config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -261,6 +279,7 @@ config SYS_SOC default "socfpga"

config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1

From: Wan Yee Lau wan.yee.lau@intel.com

Add defconfig for Agilex7 M-series.

Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- ...onfig => socfpga_agilex7m_sdmmc_defconfig} | 110 +++++++++--------- 1 file changed, 54 insertions(+), 56 deletions(-) copy configs/{socfpga_agilex5_defconfig => socfpga_agilex7m_sdmmc_defconfig} (56%)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex7m_sdmmc_defconfig similarity index 56% copy from configs/socfpga_agilex5_defconfig copy to configs/socfpga_agilex7m_sdmmc_defconfig index f39954aea8..12414e2e5f 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex7m_sdmmc_defconfig @@ -1,50 +1,69 @@ CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x80200000 +CONFIG_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_NR_DRAM_BANKS=2 +CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x04100000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" -CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex7m_socdk" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_AGILEX7M_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex7m" CONFIG_SPL_FS_FAT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 +CONFIG_SYS_LOAD_ADDR=0x02000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_QSPI_BOOT=y +# CONFIG_NAND_BOOT is not set +# CONFIG_QSPI_BOOT is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" -CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTARGS="earlycon panic=-1" # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SPL_SYS_MALLOC_ADDR=0x3fa00000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_CRC32=y +CONFIG_SPL_MTD_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX7M # " CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_DOS_PARTITION=y -CONFIG_SPL_DOS_PARTITION=y -CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y +CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_CMD_NAND_TRIMFFS is not set +# CONFIG_CMD_NAND_LOCK_UNLOCK is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPI_FLASH_MTD=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_CMD_UBI=y CONFIG_CMD_UBIFS=y CONFIG_MTD_UBI=y @@ -53,9 +72,8 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_LIST="" -CONFIG_ENV_IS_IN_UBI=y -CONFIG_ENV_UBI_PART="root" -CONFIG_ENV_UBI_VOLUME="env" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -65,52 +83,32 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MTD=y CONFIG_DM_MTD=y +# CONFIG_NAND_DENALI_DT is not set +# CONFIG_SYS_NAND_U_BOOT_LOCATIONS is not set +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_UBI_SILENCE_MSG=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_RGMII=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y +# CONFIG_CADENCE_QSPI is not set +# CONFIG_DESIGNWARE_SPI is not set CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_XHCI_HCD=y -CONFIG_UBIFS_SILENCE_MSG=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_WDT=y -CONFIG_CMD_WDT=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_SPL_WDT=y -CONFIG_WATCHDOG_AUTOSTART=n -CONFIG_TIMER=y -CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xbff00000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x7f000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -# CONFIG_EFI_LOADER is not set -CONFIG_I3C=y -CONFIG_DW_I3C_MASTER=y -CONFIG_CMD_I3C=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_TIMER=y -# CONFIG_BOOTFILE="Image" is not set for CONFIG_SPL_ATF=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb"