[U-Boot-Users] PPC assembler question for mpc8548cds
Hi all,
I'm porting u-boot to my board. There's the mpc8548cds that matches close to my board in u-boot 1.1.6. My board, however, has 1 Gigabit of flash, 128MB. So this section is the cds code init.S :
/* * TLB 0: 16M Non-cacheable, guarded * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
And the LAW code is commented as: * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
My board has only the boot bank - no 2nd bank.
What's confusing me is there is no constant BOOKE_PAGESZ_128M. For example, the cds board has 128MB of SDRAM (my board has no SDRAM) . So the way the cds code allocates the 128MB for sdram is:
/* * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
With LAW comments:
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
I'm thinking this is because the TLB size can be allocated as 64MB for the 128MB of flash, and then the LAW code needs to allocate the full 128MB for flash. So in preparation for my boards arrival, I'm thinking I can do this for the flash:
/* * TLB 0: 64M Non-cacheable, guarded * 0xff000000 64M FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
* 0xff00_0000 0xf7ff_ffff FLASH (boot bank) 128M
Yet the LAW comments say this:
* If flash is 8M at default position (last 8M), no LAW needed.
So since my board has no SDRAM, I'm thinking I can do this:
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_FLASH_BASE>>12) & 0xfffff) #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
I've been staring at this code for days so I thought I'd ask here. Any ideas? Robert
On 6/26/07, robert lazarski robertlazarski@gmail.com wrote:
Hi all,
What's confusing me is there is no constant BOOKE_PAGESZ_128M. For example, the cds board has 128MB of SDRAM (my board has no SDRAM) . So the way the cds code allocates the 128MB for sdram is:
/* * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE),0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
With LAW comments:
- 0xf000_0000 0xf7ff_ffff SDRAM 128M
Ugh, that's awful. It's a bug, and needs to be fixed.
I'm thinking this is because the TLB size can be allocated as 64MB for the 128MB of flash, and then the LAW code needs to allocate the full 128MB for flash. So in preparation for my boards arrival, I'm thinking I can do this for the flash:
The TLB size is wrong. It can't be 128M, because Book E only allows specifying powers of 4 for the size. So to do 128M, you need to use two TLB entries to specify 128M.
The LAWs *also* need to have full 128M, but they can do any power of two.
Andy
On 7/2/07, Andy Fleming afleming@gmail.com wrote:
On 6/26/07, robert lazarski robertlazarski@gmail.com wrote:
Hi all,
What's confusing me is there is no constant BOOKE_PAGESZ_128M. For
example,
the cds board has 128MB of SDRAM (my board has no SDRAM) . So the way
the
cds code allocates the 128MB for sdram is:
/* * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE),0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
With LAW comments:
- 0xf000_0000 0xf7ff_ffff SDRAM 128M
Ugh, that's awful. It's a bug, and needs to be fixed.
I'm thinking this is because the TLB size can be allocated as 64MB for
the
128MB of flash, and then the LAW code needs to allocate the full 128MB
for
flash. So in preparation for my boards arrival, I'm thinking I can do
this
for the flash:
The TLB size is wrong. It can't be 128M, because Book E only allows specifying powers of 4 for the size. So to do 128M, you need to use two TLB entries to specify 128M.
The LAWs *also* need to have full 128M, but they can do any power of two.
Andy
Thanks Andy, things are getting clearer. I found another example that seems to have a bad comment, from the board/tqm85xx/init.S out of u-boot 1.2.0 . TLB 0, 1 does this which seems to be a good example:
/* * TLB 0, 1: 128M Non-cacheable, guarded * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
But then the LAW comments say this, is this wrong?
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
The actual LAW macros looks right though, doesn't it?
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
Robert
participants (2)
-
Andy Fleming -
robert lazarski