From: Suman Anna s-anna@ti.com

Define a macro for the DSP GEM power domain id number and use it instead of a hard-coded number in the code that disables all the DSPs on various Keystone2 SoCs.

Signed-off-by: Suman Anna s-anna@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-keystone/include/mach/hardware.h | 1 + arch/arm/mach-keystone/keystone.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index edebcd7bc587..8ca19bbcdbe9 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -160,6 +160,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_LPSC_GEM_0 15 #define KS2_LPSC_TETRIS 52 #define KS2_TETRIS_PWR_DOMAIN 31 +#define KS2_GEM_0_PWR_DOMAIN 8

/* Chip configuration unlock codes and registers */ #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 11a9357db414..a8071270e9bf 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -54,7 +54,7 @@ static void turn_off_all_dsps(int num_dsps) if (psc_disable_module(i + KS2_LPSC_GEM_0)) printf("Cannot disable module for #%d DSP", i);

- if (psc_disable_domain(i + 8)) + if (psc_disable_domain(i + KS2_GEM_0_PWR_DOMAIN)) printf("Cannot disable domain for #%d DSP", i); } }

From: Suman Anna s-anna@ti.com

The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs.

Signed-off-by: Suman Anna s-anna@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index fa4162fe9964..ca2a119d3901 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARCH_HARDWARE_K2G_H #define __ASM_ARCH_HARDWARE_K2G_H

-#define KS2_NUM_DSPS 0 +#define KS2_NUM_DSPS 1

/* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_ALWAYSON 0 @@ -30,7 +30,10 @@ #define KS2_LPSC_MCASP 15 #define KS2_LPSC_SR 16 #define KS2_LPSC_MSMC 17 -#define KS2_LPSC_GEM 18 +#ifdef KS2_LPSC_GEM_0 +#undef KS2_LPSC_GEM_0 +#endif +#define KS2_LPSC_GEM_0 18 #define KS2_LPSC_ARM 19 #define KS2_LPSC_ASRC 20 #define KS2_LPSC_ICSS 21

From: Lokesh Vutla lokeshvutla@ti.com

Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific speed definitions.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-keystone/clock.c | 12 ++++++------ arch/arm/mach-keystone/include/mach/clock.h | 4 ++-- board/ti/ks2_evm/board_k2e.c | 2 +- board/ti/ks2_evm/board_k2hk.c | 4 ++-- board/ti/ks2_evm/board_k2l.c | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 5c6051e76db8..1ae3baf982a1 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -228,14 +228,14 @@ void init_plls(void) } }

-static int get_max_speed(u32 val, u32 speed_supported) +static int get_max_speed(u32 val, u32 speed_supported, int *spds) { int speed;

/* Left most setbit gives the speed */ for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { if ((val & BIT(speed)) & speed_supported) - return speeds[speed]; + return spds[speed]; }

/* If no bit is set, use SPD800 */ @@ -250,24 +250,24 @@ static inline u32 read_efuse_bootrom(void) return __raw_readl(KS2_EFUSE_BOOTROM); }

-int get_max_arm_speed(void) +int get_max_arm_speed(int *spds) { u32 armspeed = read_efuse_bootrom();

armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> DEVSPEED_ARMSPEED_SHIFT;

- return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); + return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds); }

-int get_max_dev_speed(void) +int get_max_dev_speed(int *spds) { u32 devspeed = read_efuse_bootrom();

devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> DEVSPEED_DEVSPEED_SHIFT;

- return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); + return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds); }

/** diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index cdcff3baee36..dfebcb03ea57 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -124,8 +124,8 @@ struct pll_init_data *get_pll_init_data(int pll); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); -int get_max_dev_speed(void); -int get_max_arm_speed(void); +int get_max_dev_speed(int *spds); +int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void);

#endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index f58f62358d3e..cbb3077bc36c 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -61,7 +61,7 @@ struct pll_init_data *get_pll_init_data(int pll)

switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case PASS_PLL: diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 0bd6b86e2573..e217beaed5e4 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -51,11 +51,11 @@ struct pll_init_data *get_pll_init_data(int pll)

switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case TETRIS_PLL: - speed = get_max_arm_speed(); + speed = get_max_arm_speed(speeds); data = &tetris_pll_config[speed]; break; case PASS_PLL: diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index d750ad3c0b05..2a2e0057e24e 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -50,11 +50,11 @@ struct pll_init_data *get_pll_init_data(int pll)

switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case TETRIS_PLL: - speed = get_max_arm_speed(); + speed = get_max_arm_speed(speeds); data = &tetris_pll_config[speed]; break; case PASS_PLL:

From: Lokesh Vutla lokeshvutla@ti.com

The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-keystone/clock.c | 7 +++- arch/arm/mach-keystone/include/mach/clock-k2g.h | 4 +- arch/arm/mach-keystone/include/mach/clock.h | 4 ++ board/ti/ks2_evm/board_k2g.c | 50 +++++++++++++++++++++++-- 4 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 1ae3baf982a1..b25db1e3fede 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -238,8 +238,11 @@ static int get_max_speed(u32 val, u32 speed_supported, int *spds) return spds[speed]; }

- /* If no bit is set, use SPD800 */ - return SPD800; + /* If no bit is set, return minimum speed */ + if (cpu_is_k2g()) + return SPD200; + else + return SPD800; }

static inline u32 read_efuse_bootrom(void) diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h index 214c1d3a8360..74de6202fe50 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2g.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -12,8 +12,8 @@

#define PLLSET_CMD_LIST "<pa|arm|ddr3>"

-#define DEV_SUPPORTED_SPEEDS 0xfff -#define ARM_SUPPORTED_SPEEDS 0xfff +#define DEV_SUPPORTED_SPEEDS 0x1ff +#define ARM_SUPPORTED_SPEEDS 0xff

#define KS2_CLK1_6 sys_clk0_6_clk

diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index dfebcb03ea57..72724aa4a912 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -63,8 +63,12 @@ #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)

enum { + SPD200, + SPD400, + SPD600, SPD800, SPD850, + SPD900, SPD1000, SPD1200, SPD1250, diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index cdeb056a76c4..b62c41225039 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -23,22 +23,64 @@ unsigned int external_clk[ext_clk_count] = { [uart_clk] = SYS_CLK, };

-static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; -static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; +static int arm_speeds[DEVSPEED_NUMSPDS] = { + SPD400, + SPD600, + SPD800, + SPD900, + SPD1000, + SPD900, + SPD800, + SPD600, + SPD400, + SPD200, +}; + +static int dev_speeds[DEVSPEED_NUMSPDS] = { + SPD600, + SPD800, + SPD900, + SPD1000, + SPD900, + SPD800, + SPD600, + SPD400, +}; + +static struct pll_init_data main_pll_config[NUM_SPDS] = { + [SPD400] = {MAIN_PLL, 100, 3, 2}, + [SPD600] = {MAIN_PLL, 300, 6, 2}, + [SPD800] = {MAIN_PLL, 200, 3, 2}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +}; + +static struct pll_init_data tetris_pll_config[NUM_SPDS] = { + [SPD200] = {TETRIS_PLL, 250, 3, 10}, + [SPD400] = {TETRIS_PLL, 100, 1, 6}, + [SPD600] = {TETRIS_PLL, 100, 1, 4}, + [SPD800] = {TETRIS_PLL, 400, 3, 4}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +}; + static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};

struct pll_init_data *get_pll_init_data(int pll) { + int speed; struct pll_init_data *data = NULL;

switch (pll) { case MAIN_PLL: - data = &main_pll_config; + speed = get_max_dev_speed(dev_speeds); + data = &main_pll_config[speed]; break; case TETRIS_PLL: - data = &tetris_pll_config; + speed = get_max_arm_speed(arm_speeds); + data = &tetris_pll_config[speed]; break; case NSS_PLL: data = &nss_pll_config;

From: Vitaly Andrianov vitalya@ti.com

This commit replaces hard-coded EMIF and PHY DDR3 configurations for predefined SODIMMs to a calculated configuration. The SODIMM parameters are read from SODIMM's SPD and used to calculated the configuration.

The current commit supports calculation for DDR3 with 1600MHz and 1333MHz only.

Signed-off-by: Vitaly Andrianov vitalya@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-keystone/Makefile | 2 + arch/arm/mach-keystone/ddr3_spd.c | 456 +++++++++++++++++++++++++++++ arch/arm/mach-keystone/include/mach/ddr3.h | 8 + board/ti/ks2_evm/Makefile | 4 +- board/ti/ks2_evm/ddr3_cfg.c | 159 +--------- board/ti/ks2_evm/ddr3_cfg.h | 11 +- board/ti/ks2_evm/ddr3_k2e.c | 51 ++-- board/ti/ks2_evm/ddr3_k2hk.c | 97 +++--- include/configs/k2e_evm.h | 2 + include/configs/k2hk_evm.h | 2 + 10 files changed, 532 insertions(+), 260 deletions(-) create mode 100644 arch/arm/mach-keystone/ddr3_spd.c

diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index ffd9eadb0a49..9713fe4d6858 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -13,3 +13,5 @@ obj-y += cmd_mon.o obj-y += msmc.o obj-y += ddr3.o cmd_ddr3.o obj-y += keystone.o +obj-$(CONFIG_K2E_EVM) += ddr3_spd.o +obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c new file mode 100644 index 000000000000..b0768823f2eb --- /dev/null +++ b/arch/arm/mach-keystone/ddr3_spd.c @@ -0,0 +1,456 @@ +/* + * Keystone2: DDR3 SPD configuration + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <i2c.h> +#include <ddr_spd.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +#ifdef DUMP_DDR_CONFIG +static void dump_phy_config(struct ddr3_phy_config *ptr) +{ + printf("\npllcr 0x%08X\n", ptr->pllcr); + printf("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask); + printf("pgcr1_val 0x%08X\n", ptr->pgcr1_val); + printf("ptr0 0x%08X\n", ptr->ptr0); + printf("ptr1 0x%08X\n", ptr->ptr1); + printf("ptr2 0x%08X\n", ptr->ptr2); + printf("ptr3 0x%08X\n", ptr->ptr3); + printf("ptr4 0x%08X\n", ptr->ptr4); + printf("dcr_mask 0x%08X\n", ptr->dcr_mask); + printf("dcr_val 0x%08X\n", ptr->dcr_val); + printf("dtpr0 0x%08X\n", ptr->dtpr0); + printf("dtpr1 0x%08X\n", ptr->dtpr1); + printf("dtpr2 0x%08X\n", ptr->dtpr2); + printf("mr0 0x%08X\n", ptr->mr0); + printf("mr1 0x%08X\n", ptr->mr1); + printf("mr2 0x%08X\n", ptr->mr2); + printf("dtcr 0x%08X\n", ptr->dtcr); + printf("pgcr2 0x%08X\n", ptr->pgcr2); + printf("zq0cr1 0x%08X\n", ptr->zq0cr1); + printf("zq1cr1 0x%08X\n", ptr->zq1cr1); + printf("zq2cr1 0x%08X\n", ptr->zq2cr1); + printf("pir_v1 0x%08X\n", ptr->pir_v1); + printf("pir_v2 0x%08X\n\n", ptr->pir_v2); +}; + +static void dump_emif_config(struct ddr3_emif_config *ptr) +{ + printf("\nsdcfg 0x%08X\n", ptr->sdcfg); + printf("sdtim1 0x%08X\n", ptr->sdtim1); + printf("sdtim2 0x%08X\n", ptr->sdtim2); + printf("sdtim3 0x%08X\n", ptr->sdtim3); + printf("sdtim4 0x%08X\n", ptr->sdtim4); + printf("zqcfg 0x%08X\n", ptr->zqcfg); + printf("sdrfc 0x%08X\n\n", ptr->sdrfc); +}; +#endif + +#define TEMP NORMAL_TEMP +#define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */ +#define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */ +#define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */ +#define PLLLOCK_VAL (100000.0 / VBUS_CLKPERIOD) /* 100 us */ +#define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */ +#define PHYRST_VAL 0x10 +#define DDR_TERM RZQ_4_TERM +#define SDRAM_DRIVE RZQ_7_IMP +#define DYN_ODT ODT_DISABLE + +enum srt { + NORMAL_TEMP, + EXTENDED_TEMP +}; + +enum out_impedance { + RZQ_6_IMP = 0, + RZQ_7_IMP +}; + +enum die_term { + ODT_DISABLE = 0, + RZQ_4_TERM, + RZQ_2_TERM, + RZQ_6_TERM, + RZQ_12_TERM, + RZQ_8_TERM +}; + +struct ddr3_sodimm { + u32 t_ck; + u32 freqsel; + u32 t_xp; + u32 t_cke; + u32 t_pllpd; + u32 t_pllgs; + u32 t_phyrst; + u32 t_plllock; + u32 t_pllrst; + u32 t_rfc; + u32 t_xs; + u32 t_dinit0; + u32 t_dinit1; + u32 t_dinit2; + u32 t_dinit3; + u32 t_rtp; + u32 t_wtr; + u32 t_rp; + u32 t_rcd; + u32 t_ras; + u32 t_rrd; + u32 t_rc; + u32 t_faw; + u32 t_mrd; + u32 t_mod; + u32 t_wlo; + u32 t_wlmrd; + u32 t_xsdll; + u32 t_xpdll; + u32 t_ckesr; + u32 t_dllk; + u32 t_wr; + u32 t_wr_bin; + u32 cas; + u32 cwl; + u32 asr; + u32 pasr; + u32 t_refprd; + u8 sdram_type; + u8 ibank; + u8 pagesize; + u8 t_rrd2; + u8 t_ras_max; + u8 t_zqcs; + u32 refresh_rate; + u8 t_csta; + + u8 rank; + u8 mirrored; + u8 buswidth; +}; + +static u8 cas_latancy(u16 temp) +{ + int loop; + u8 cas_bin = 0; + + for (loop = 0; loop < 32; loop += 2, temp >>= 1) { + if (temp & 0x0001) + cas_bin = (loop > 15) ? loop - 15 : loop; + } + + return cas_bin; +} + +static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf) +{ + return (((buf->organization & 0x38) >> 3) + 1) * + (256 << (buf->density_banks & 0xf)); +} + +static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd, + struct ddr3_spd_cb *spd_cb) +{ + u32 mtb, clk_freq; + + if ((buf->mem_type != 0x0b) || + ((buf->density_banks & 0x70) != 0x00)) + return 1; + + spd->sdram_type = 0x03; + spd->ibank = 0x03; + + mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor; + + spd->t_ck = buf->tck_min * mtb; + + spd_cb->ddrspdclock = 2000000 / spd->t_ck; + clk_freq = spd_cb->ddrspdclock / 2; + + spd->rank = ((buf->organization & 0x38) >> 3) + 1; + if (spd->rank > 2) + return 1; + + spd->pagesize = (buf->addressing & 0x07) + 1; + if (spd->pagesize > 3) + return 1; + + spd->buswidth = 8 << (buf->bus_width & 0x7); + if ((spd->buswidth < 16) || (spd->buswidth > 64)) + return 1; + + spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1; + + if (spd_cb->ddrspdclock == 1333) { + puts("DDR3A Speed will be configured for 1333 Operation.\n"); + + spd->t_xp = ((3 * spd->t_ck) > 6000) ? + 3 : ((5999 / spd->t_ck) + 1); + spd->t_cke = ((3 * spd->t_ck) > 5625) ? + 3 : ((5624 / spd->t_ck) + 1); + } else if (spd_cb->ddrspdclock == 1600) { + puts("DDR3A Speed will be configured for 1600 Operation.\n"); + + spd->t_xp = ((3 * spd->t_ck) > 6000) ? + 3 : ((5999 / spd->t_ck) + 1); + spd->t_cke = ((3 * spd->t_ck) > 5000) ? + 3 : ((4999 / spd->t_ck) + 1); + } else { + printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock); + return 1; + } + + spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck; + spd->t_ckesr = spd->t_cke + 1; + + /* SPD Calculated Values */ + spd->cas = cas_latancy((buf->caslat_msb << 8) | + buf->caslat_lsb); + + spd->t_wr = (buf->twr_min * mtb) / spd->t_ck; + spd->t_wr_bin = (spd->t_wr / 2) & 0x07; + + spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1; + spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1; + spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1; + + spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) * + mtb) / spd->t_ck; + + spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) * + mtb) - 1) / spd->t_ck + 1; + + spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb / + 1000; + spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck; + spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck; + + spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck); + spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1; + + spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck; + spd->t_rrd2 = ((((buf->tfaw_msb << 8) | + buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1; + + /* Hard-coded values */ + spd->t_mrd = 0x00; + spd->t_mod = 0x00; + spd->t_wlo = 0x0C; + spd->t_wlmrd = 0x28; + spd->t_xsdll = 0x200; + spd->t_ras_max = 0x0F; + spd->t_csta = 0x05; + spd->t_dllk = 0x200; + + /* CAS Write Latency */ + if (spd->t_ck >= 2500) + spd->cwl = 0; + else if (spd->t_ck >= 1875) + spd->cwl = 1; + else if (spd->t_ck >= 1500) + spd->cwl = 2; + else if (spd->t_ck >= 1250) + spd->cwl = 3; + else if (spd->t_ck >= 1071) + spd->cwl = 4; + else + spd->cwl = 5; + + /* SD:RAM Thermal and Refresh Options */ + spd->asr = (buf->therm_ref_opt & 0x04) >> 2; + spd->pasr = (buf->therm_ref_opt & 0x80) >> 7; + spd->t_zqcs = 64; + + spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250; + spd->t_refprd = spd->t_refprd / spd->t_ck; + + spd->refresh_rate = spd->t_refprd; + spd->t_refprd = spd->t_refprd * 5; + + /* Set MISC PHY space registers fields */ + if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275)) + spd->freqsel = 0x03; + else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385)) + spd->freqsel = 0x01; + else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534)) + spd->freqsel = 0x00; + + spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */ + spd->t_dinit1 = spd->t_xs; + spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */ + /* Time from ZQ initialization command to first command (1 us) */ + spd->t_dinit3 = 1000000 / spd->t_ck; + + spd->t_pllgs = PLLGS_VAL + 1; + spd->t_pllpd = PLLPD_VAL + 1; + spd->t_plllock = PLLLOCK_VAL + 1; + spd->t_pllrst = PLLRST_VAL; + spd->t_phyrst = PHYRST_VAL; + + spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024; + + return 0; +} + +static void init_ddr3param(struct ddr3_spd_cb *spd_cb, + struct ddr3_sodimm *spd) +{ + spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; + spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK); + spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)); + spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | + ((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f); + spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) | + (spd->t_pllrst & 0x1fff); + spd_cb->phy_cfg.ptr2 = 0; + spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) | + (spd->t_dinit0 & 0xfffff); + spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) | + (spd->t_dinit2 & 0x3ffff); + + spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK; + spd_cb->phy_cfg.dcr_val = 1 << 10; + + if (spd->mirrored) { + spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK; + spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29); + } + + spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | + (spd->t_rrd & 0xf) << 22 | + (spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 | + (spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 | + (spd->t_rtp & 0xf); + spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | + (spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 | + (spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 | + (spd->t_mrd & 0x3); + + spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | + (spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15; + + spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? + spd->t_xp : spd->t_xpdll) & + 0x1f) << 10; + + spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? + spd->t_xs : spd->t_xsdll) & + 0x3ff); + + spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | + 0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 | + (spd->cas & 0x01) << 2; + + spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | + ((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 | + (DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 | + (SDRAM_DRIVE & 1) << 1 | 0 << 0; + + spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | + (spd->cwl & 7) << 3 | (spd->pasr & 7); + + spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; + spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff); + + spd_cb->phy_cfg.zq0cr1 = 0x0000005D; + spd_cb->phy_cfg.zq1cr1 = 0x0000005B; + spd_cb->phy_cfg.zq2cr1 = 0x0000005B; + + spd_cb->phy_cfg.pir_v1 = 0x00000033; + spd_cb->phy_cfg.pir_v2 = 0x0000FF81; + + /* EMIF Registers */ + spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 | + (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | + (spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 | + (spd->buswidth & 3) << 12 | (spd->pagesize & 3); + + if (spd->rank == 2) + spd_cb->emif_cfg.sdcfg |= 1 << 3; + + spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | + ((spd->t_ras - 1) & 0x7f) << 18 | + ((spd->t_rc - 1) & 0xff) << 10 | + (spd->t_rrd2 & 0x3f) << 4 | + ((spd->t_wtr - 1) & 0xf); + + spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 | + ((spd->t_rcd - 1) & 0x1f); + + spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 | + ((spd->t_xs - 1) & 0x3ff) << 18 | + ((spd->t_xsdll - 1) & 0x3ff) << 8 | + ((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf); + + spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 | + ((spd->t_ckesr - 1) & 0xf) << 24 | + ((spd->t_zqcs - 1) & 0xff) << 16 | + ((spd->t_rfc - 1) & 0x3ff) << 4 | + (spd->t_ras_max & 0xf); + + spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff; + + /* TODO zqcfg value fixed ,May be required correction for K2E evm. */ + spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; +} + +static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) +{ + int ret; + int old_bus; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256); + + i2c_set_bus_num(old_bus); + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + if (ddr3_spd_check(spd_params)) + return 1; + + return 0; +} + +int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb) +{ + struct ddr3_sodimm spd; + ddr3_spd_eeprom_t spd_params; + + memset(&spd, 0, sizeof(spd)); + + if (ddr3_read_spd(&spd_params)) + return 1; + + if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) { + puts("Timing caclulation error\n"); + return 1; + } + + strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18); + spd_cb->dimm_name[18] = '\0'; + + init_ddr3param(spd_cb, &spd); + +#ifdef DUMP_DDR_CONFIG + dump_emif_config(&spd_cb->emif_cfg); + dump_phy_config(&spd_cb->phy_cfg); +#endif + + return 0; +} diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h index a22c237c8026..68d3cb4245e9 100644 --- a/arch/arm/mach-keystone/include/mach/ddr3.h +++ b/arch/arm/mach-keystone/include/mach/ddr3.h @@ -48,6 +48,14 @@ struct ddr3_emif_config { unsigned int sdrfc; };

+struct ddr3_spd_cb { + char dimm_name[32]; + struct ddr3_phy_config phy_cfg; + struct ddr3_emif_config emif_cfg; + unsigned int ddrspdclock; + int ddr_size_gbyte; +}; + u32 ddr3_init(void); void ddr3_reset_ddrphy(void); void ddr3_init_ecc(u32 base, u32 ddr3_size); diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index d60496ef2723..7ef2d2bff5a0 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -1,17 +1,17 @@ # # KS2-EVM: board Makefile -# (C) Copyright 2012-2014 +# (C) Copyright 2012-2015 # Texas Instruments Incorporated, <www.ti.com> # SPDX-License-Identifier: GPL-2.0+ #

obj-y += board.o -obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o obj-$(CONFIG_K2G_EVM) += board_k2g.o obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index ab44676793c0..b6b59a4dd5b1 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -9,129 +9,8 @@

#include <common.h>

-#include <i2c.h> #include <asm/arch/ddr3.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* DDR3 PHY configuration data with 1600M rate, 8GB size */ -struct ddr3_phy_config ddr3phy_1600_8g = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ -struct ddr3_emif_config ddr3_1600_8g = { - .sdcfg = 0x6200CE6Aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -#ifdef CONFIG_K2HK_EVM -/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ -struct ddr3_phy_config ddr3phy_1333_2g = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ -struct ddr3_emif_config ddr3_1333_2g = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001457ul, -}; -#endif - -#ifdef CONFIG_K2E_EVM -/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ -struct ddr3_phy_config ddr3phy_1600_4g = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x08861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x9D9CBB66ul, - .dtpr1 = 0x12840300ul, - .dtpr2 = 0x5002D200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ -struct ddr3_emif_config ddr3_1600_4g = { - .sdcfg = 0x6200CE62ul, - .sdtim1 = 0x166C9855ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x421DFF53ul, - .sdtim4 = 0x543F07FFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; -#endif +#include "ddr3_cfg.h"

struct ddr3_phy_config ddr3phy_1600_2g = { .pllcr = 0x0001C000ul, @@ -168,39 +47,3 @@ struct ddr3_emif_config ddr3_1600_2g = { .zqcfg = 0x70073200ul, .sdrfc = 0x00001869ul, }; - -int ddr3_get_dimm_params(char *dimm_name) -{ - int ret; - int old_bus; - u8 spd_params[256]; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index 5bd786cff8e9..f95eddec3308 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -10,18 +10,11 @@ #ifndef __DDR3_CFG_H #define __DDR3_CFG_H

-extern struct ddr3_phy_config ddr3phy_1600_8g; -extern struct ddr3_emif_config ddr3_1600_8g; - -extern struct ddr3_phy_config ddr3phy_1333_2g; -extern struct ddr3_emif_config ddr3_1333_2g; - -extern struct ddr3_phy_config ddr3phy_1600_4g; -extern struct ddr3_emif_config ddr3_1600_4g; +#include <asm/arch/ddr3.h>

extern struct ddr3_phy_config ddr3phy_1600_2g; extern struct ddr3_emif_config ddr3_1600_2g;

-int ddr3_get_dimm_params(char *dimm_name); +int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);

#endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 35ffb4205673..e82aa6699b10 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -1,7 +1,7 @@ /* * Keystone2: DDR3 initialization * - * (C) Copyright 2014 + * (C) Copyright 2014-2015 * Texas Instruments Incorporated, <www.ti.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -12,42 +12,37 @@ #include <asm/arch/ddr3.h>

static struct pll_init_data ddr3_400 = DDR3_PLL_400; +static struct pll_init_data ddr3_333 = DDR3_PLL_333;

u32 ddr3_init(void) { - u32 ddr3_size; - char dimm_name[32]; + struct ddr3_spd_cb spd_cb;

- if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) - init_pll(&ddr3_400); + if (ddr3_get_dimm_params_from_spd(&spd_cb)) { + printf("Sorry, I don't know how to configure DDR3A.\n" + "Bye :(\n"); + for (;;) + ; + }

- ddr3_get_dimm_params(dimm_name); + printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);

- printf("Detected SO-DIMM [%s]\n", dimm_name); + printf("DDR3 speed %d\n", spd_cb.ddrspdclock); + if (spd_cb.ddrspdclock == 1600) + init_pll(&ddr3_400); + else + init_pll(&ddr3_333);

/* Reset DDR3 PHY after PLL enabled */ ddr3_reset_ddrphy();

- if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - /* 8G SO-DIMM */ - ddr3_size = 8; - printf("DRAM: 8 GiB\n"); - ddr3phy_1600_8g.zq0cr1 |= 0x10000; - ddr3phy_1600_8g.zq1cr1 |= 0x10000; - ddr3phy_1600_8g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); - } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { - /* 4G SO-DIMM */ - ddr3_size = 4; - printf("DRAM: 4 GiB\n"); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); - } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; - } + spd_cb.phy_cfg.zq0cr1 |= 0x10000; + spd_cb.phy_cfg.zq1cr1 |= 0x10000; + spd_cb.phy_cfg.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + + printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);

- return ddr3_size; + return (u32)spd_cb.ddr_size_gbyte; } diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index b36eb27bfaa7..f8484221fa1d 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -17,77 +17,48 @@ struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);

u32 ddr3_init(void) { - char dimm_name[32]; u32 ddr3_size; + struct ddr3_spd_cb spd_cb;

- ddr3_get_dimm_params(dimm_name); + if (ddr3_get_dimm_params_from_spd(&spd_cb)) { + printf("Sorry, I don't know how to configure DDR3A.\n" + "Bye :(\n"); + for (;;) + ; + }

- printf("Detected SO-DIMM [%s]\n", dimm_name); + printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);

- if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - init_pll(&ddr3a_400); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3phy_1600_8g.zq0cr1 |= 0x10000; - ddr3phy_1600_8g.zq1cr1 |= 0x10000; - ddr3phy_1600_8g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_8g); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_8g); - } + if ((cpu_revision() > 1) || + (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) { + printf("DDR3 speed %d\n", spd_cb.ddrspdclock); + if (spd_cb.ddrspdclock == 1600) + init_pll(&ddr3a_400); + else + init_pll(&ddr3a_333); + }

- ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_8g); - printf("DRAM: Capacity 8 GiB (includes reported below)\n"); - ddr3_size = 8; - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); - ddr3_1600_8g.sdcfg |= 0x1000; - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_8g); - printf("DRAM: Capacity 4 GiB (includes reported below)\n"); - ddr3_size = 4; - } - } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { - init_pll(&ddr3a_333); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3phy_1333_2g.zq0cr1 |= 0x10000; - ddr3phy_1333_2g.zq1cr1 |= 0x10000; - ddr3phy_1333_2g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_2g); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_2g); - } - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_2g); - ddr3_size = 2; - printf("DRAM: 2 GiB"); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); - ddr3_1333_2g.sdcfg |= 0x1000; - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_2g); - ddr3_size = 1; - printf("DRAM: 1 GiB"); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + spd_cb.phy_cfg.zq0cr1 |= 0x10000; + spd_cb.phy_cfg.zq1cr1 |= 0x10000; + spd_cb.phy_cfg.zq2cr1 |= 0x10000; } + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + + ddr3_size = spd_cb.ddr_size_gbyte; } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + spd_cb.emif_cfg.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + ddr3_size = spd_cb.ddr_size_gbyte / 2; } + printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);

/* Apply the workaround for PG 1.0 and 1.1 Silicons */ if (cpu_revision() <= 1) diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 4f4ebf53ec59..e053a54d4169 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -38,4 +38,6 @@ #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE

+#define CONFIG_DDR_SPD + #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 6c6dcb1e5ed3..3cd2a85a2d11 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,4 +37,6 @@ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5

+#define CONFIG_DDR_SPD + #endif /* __CONFIG_K2HK_EVM_H */