[PATCH v2 0/2] riscv: cpu: Add support for cv1800b SoC
This series add basic support for cv1800b SoC and enable dcache support.
The cv1800b utilizes CSR instructions to manipulate the first and second bits in the MHCR register (0x7C1) to indicate the activation status of icache and dcache. As the icache and dcache are already enabled in the FSBL (first stage bootloader) provided by the vendor, and the U-Boot running in S-Mode is unable to manipulate CSR registers, support for operations related to enabling, disabling, or checking the status of the cache is not provided.
Changes in v2: - Remove duplicate code in function cleanup_before_linux
Kongyang Liu (2): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b
arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 +++++++++ arch/riscv/cpu/cv1800b/Makefile | 7 +++++ arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++ arch/riscv/cpu/cv1800b/cpu.c | 9 +++++++ arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++ board/sophgo/milkv_duo/Kconfig | 4 +-- 7 files changed, 97 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c
Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com
---
Changes in v2: - Remove duplicate code in function cleanup_before_linux
arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 ++++++++++++ arch/riscv/cpu/cv1800b/Makefile | 6 ++++++ arch/riscv/cpu/cv1800b/cpu.c | 9 +++++++++ arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++++++++ board/sophgo/milkv_duo/Kconfig | 4 ++-- 6 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ac52c5e6da..2c92b0d9f6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig"
# platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig new file mode 100644 index 0000000000..7225b1210c --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + +config SOPHGO_CV1800B + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply CMD_CPU diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile new file mode 100644 index 0000000000..da12e0f64e --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c new file mode 100644 index 0000000000..233a6a3d64 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c new file mode 100644 index 0000000000..91007c0a3d --- /dev/null +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig index 2a458f291c..040a7487f1 100644 --- a/board/sophgo/milkv_duo/Kconfig +++ b/board/sophgo/milkv_duo/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "sophgo"
config SYS_CPU - default "generic" + default "cv1800b"
config SYS_CONFIG_NAME default "milkv_duo" @@ -23,6 +23,6 @@ config ENV_SECT_SIZE
config BOARD_SPECIFIC_OPTIONS def_bool y - select GENERIC_RISCV + select SOPHGO_CV1800B
endif
On Sun, Mar 10, 2024 at 12:54:56AM +0800, Kongyang Liu wrote:
Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com
Changes in v2:
- Remove duplicate code in function cleanup_before_linux
arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 ++++++++++++ arch/riscv/cpu/cv1800b/Makefile | 6 ++++++ arch/riscv/cpu/cv1800b/cpu.c | 9 +++++++++ arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++++++++ board/sophgo/milkv_duo/Kconfig | 4 ++-- 6 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
Add dcache operations invalidate_dcache_range and flush_dcache_range for cv1800b.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com ---
(no changes since v1)
arch/riscv/cpu/cv1800b/Makefile | 1 + arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/riscv/cpu/cv1800b/cache.c
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile index da12e0f64e..95beb34b51 100644 --- a/arch/riscv/cpu/cv1800b/Makefile +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -4,3 +4,4 @@
obj-y += dram.o obj-y += cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c new file mode 100644 index 0000000000..b8051e29e0 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cache.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + */ + +#include <cpu_func.h> + +/* + * dcache.ipa rs1 (invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01010 rs1 000 00000 0001011 + * + * dcache.cpa rs1 (clean) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01001 rs1 000 00000 0001011 + * + * dcache.cipa rs1 (clean then invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01011 rs1 000 00000 0001011 + * + * sync.s + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000000 11001 00000 000 00000 0001011 + */ +#define DCACHE_IPA_A0 ".long 0x02a5000b" +#define DCACHE_CPA_A0 ".long 0x0295000b" +#define DCACHE_CIPA_A0 ".long 0x02b5000b" + +#define SYNC_S ".long 0x0190000b" + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_IPA_A0); + __asm__ __volatile__(SYNC_S); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_CPA_A0); + __asm__ __volatile__(SYNC_S); +}
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
Add dcache operations invalidate_dcache_range and flush_dcache_range for cv1800b.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com
(no changes since v1)
arch/riscv/cpu/cv1800b/Makefile | 1 + arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/riscv/cpu/cv1800b/cache.c
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
participants (2)
-
Kongyang Liu -
Leo Liang