[U-Boot] [PATCH 0/4] Enable CPSW on TI814x EVM
This series adds support for CPSW on the PG1.0 TI814x EVM board. The V1 CPSW on TI814x requires minor register changes to the existing driver as well as TI814x-specific pll/clock support. An ET1011C phy driver is added to support the PHY present on the PG1.0 EVM.
It has been tested loading/booting a Linux kernel and regression tested on BeagleBone and EVM-SK AM33XX boards. It has also been MAKEALL tested for all am33xx platforms.
The series applies on top of the following patches: - am33xx: Add required includes to some omap/am33xx code http://patchwork.ozlabs.org/patch/227804/ - Add TI814x EVM Support v4 http://www.mail-archive.com/u-boot@lists.denx.de/msg108356.html
Matt Porter (4): am33xx: add pll and clock support for TI814x CPSW cpsw: add support for TI814x slave_regs differences phy: add support for ET1011C phys ti814x_evm: enable CPSW support
arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 56 +++++++++- arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 1 + board/ti/ti814x/evm.c | 75 +++++++++++++ board/ti/ti814x/evm.h | 1 + board/ti/ti814x/mux.c | 35 +++++++ drivers/net/cpsw.c | 6 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/et1011c.c | 110 ++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/configs/ti814x_evm.h | 21 ++++ include/phy.h | 1 + 11 files changed, 308 insertions(+), 2 deletions(-) create mode 100644 drivers/net/phy/et1011c.c
Enables required PLLs and clocks for CPSW on TI814x.
Signed-off-by: Matt Porter mporter@ti.com --- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 56 +++++++++++++++++++- arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 1 + board/ti/ti814x/evm.c | 3 ++ 3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index cb4210f..69ecf72 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -183,7 +183,7 @@ struct cm_alwon { unsigned int resv5[2]; unsigned int gpmcclkctrl; unsigned int ethernet0clkctrl; - unsigned int resv6[1]; + unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; unsigned int debugssclkctrl; unsigned int l3clkctrl; @@ -203,9 +203,23 @@ struct cm_alwon { unsigned int custefuseclkctrl; };
+#define SATA_PLL_BASE (CTRL_BASE + 0x0720) + +struct sata_pll { + unsigned int pllcfg0; + unsigned int pllcfg1; + unsigned int pllcfg2; + unsigned int pllcfg3; + unsigned int pllcfg4; + unsigned int pllstatus; + unsigned int rxstatus; + unsigned int txstatus; + unsigned int testcfg; +};
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
/* * Enable the peripheral clock for required peripherals @@ -221,6 +235,18 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + while ((readl(&cmalwon->ethernet0clkctrl) & 0x30000) != 0) + ; + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + while ((readl(&cmalwon->ethernet1clkctrl) & 0x30000) != 0) + ; }
/* @@ -365,6 +391,31 @@ void ddr_pll_config(unsigned int ddrpll_m) pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); }
+void sata_pll_config(void) +{ + /* TRM 21.3.1 */ + writel(0xc12c003c, &spll->pllcfg1); + udelay(50); + + writel(0x004008e0, &spll->pllcfg3); + udelay(50); + + writel(0x80000004, &spll->pllcfg0); + udelay(50); + + writel(0x80000014, &spll->pllcfg0); + udelay(50); + + writel(0x80000016, &spll->pllcfg0); + udelay(50); + + writel(0xc0000017, &spll->pllcfg0); + udelay(50); + + while (((readl(&spll->pllstatus) & 0x01) == 0)) + ; +} + void enable_emif_clocks(void) {};
void enable_dmm_clocks(void) @@ -397,9 +448,10 @@ void pll_init() /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+ /* Configure PLLs */ mpu_pll_config(); - l3_pll_config(); + sata_pll_config();
/* Enable the required peripherals */ enable_per_clocks(); diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index a950ac3..8f9315c 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -29,6 +29,7 @@
/* Control Module Base Address */ #define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */ #define PRCM_BASE 0x48180000 diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index acc18fb..8513220 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -151,6 +151,9 @@ void s_init(void) */ wdt_disable();
+ /* Enable timer */ + timer_init(); + /* Setup the PLLs and the clocks for the peripherals */ pll_init();
On Fri, Mar 15, 2013 at 04:58:17PM -0400, Matt Porter wrote:
[snip]
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
;- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- while ((readl(&cmalwon->ethernet0clkctrl) & 0x30000) != 0)
;- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
- while ((readl(&cmalwon->ethernet1clkctrl) & 0x30000) != 0)
Please define away the magic numbers.
[snip]
+void sata_pll_config(void) +{
- /* TRM 21.3.1 */
- writel(0xc12c003c, &spll->pllcfg1);
I'm OK with comments, but please make it a multi-line thing that explains what's going on so that it's clear that yes, really, we shouldn't have defined these.
TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers.
Signed-off-by: Matt Porter mporter@ti.com --- drivers/net/cpsw.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index f5c5b9a..34c9fdd 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -109,7 +109,13 @@ struct cpsw_slave_regs { u32 flow_thresh; u32 port_vlan; u32 tx_pri_map; +#ifdef CONFIG_AM33XX u32 gap_thresh; +#elif defined(CONFIG_TI814X) + u32 ts_ctl; + u32 ts_seq_ltype; + u32 ts_vlan; +#endif u32 sa_lo; u32 sa_hi; };
On Fri, Mar 15, 2013 at 04:58:18PM -0400, Matt Porter wrote:
TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers.
Signed-off-by: Matt Porter mporter@ti.com
Reviewed-by: Tom Rini trini@ti.com
Adds an ET1011C PHY driver which is derived from the current Linux kernel PHY driver. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the TI814x-EVM.
Signed-off-by: Matt Porter mporter@ti.com --- drivers/net/phy/Makefile | 1 + drivers/net/phy/et1011c.c | 110 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 ++ include/phy.h | 1 + 4 files changed, 115 insertions(+) create mode 100644 drivers/net/phy/et1011c.c
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 5e90d70..af5f4b8 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o +COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o COBJS-$(CONFIG_PHY_LXT) += lxt.o COBJS-$(CONFIG_PHY_MARVELL) += marvell.o COBJS-$(CONFIG_PHY_MICREL) += micrel.o diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c new file mode 100644 index 0000000..5e22399 --- /dev/null +++ b/drivers/net/phy/et1011c.c @@ -0,0 +1,110 @@ +/* + * ET1011C PHY driver + * + * Derived from Linux kernel driver by Chaithrika U S + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <config.h> +#include <phy.h> + +#define ET1011C_CONFIG_REG (0x16) +#define ET1011C_TX_FIFO_MASK (0x3 << 12) +#define ET1011C_TX_FIFO_DEPTH_8 (0x0 << 12) +#define ET1011C_TX_FIFO_DEPTH_16 (0x1 << 12) +#define ET1011C_INTERFACE_MASK (0x7 << 0) +#define ET1011C_GMII_INTERFACE (0x2 << 0) +#define ET1011C_SYS_CLK_EN (0x1 << 4) +#define ET1011C_TX_CLK_EN (0x1 << 5) + +#define ET1011C_STATUS_REG (0x1A) +#define ET1011C_DUPLEX_STATUS (0x1 << 7) +#define ET1011C_SPEED_MASK (0x3 << 8) +#define ET1011C_SPEED_1000 (0x2 << 8) +#define ET1011C_SPEED_100 (0x1 << 8) +#define ET1011C_SPEED_10 (0x0 << 8) + +static int et1011c_config(struct phy_device *phydev) +{ + int ctl = 0; + ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + if (ctl < 0) + return ctl; + ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | + BMCR_ANENABLE); + /* First clear the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); + + return genphy_config_aneg(phydev); +} + +static int et1011c_parse_status(struct phy_device *phydev) +{ + int mii_reg; + int speed; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); + + if (mii_reg & ET1011C_DUPLEX_STATUS) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & ET1011C_SPEED_MASK; + switch (speed) { + case ET1011C_SPEED_1000: + phydev->speed = SPEED_1000; + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); + mii_reg &= ~ET1011C_TX_FIFO_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, + mii_reg | + ET1011C_GMII_INTERFACE | + ET1011C_SYS_CLK_EN | +#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX + ET1011C_TX_CLK_EN | +#endif + ET1011C_TX_FIFO_DEPTH_16); + break; + case ET1011C_SPEED_100: + phydev->speed = SPEED_100; + break; + case ET1011C_SPEED_10: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int et1011c_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + et1011c_parse_status(phydev); + return 0; +} + +static struct phy_driver et1011c_driver = { + .name = "ET1011C", + .uid = 0x0282f014, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &et1011c_config, + .startup = &et1011c_startup, +}; + +int phy_et1011c_init(void) +{ + phy_register(&et1011c_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d0ed766..f8c5481 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -430,6 +430,9 @@ int phy_init(void) #ifdef CONFIG_PHY_DAVICOM phy_davicom_init(); #endif +#ifdef CONFIG_PHY_ET1011C + phy_et1011c_init(); +#endif #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif diff --git a/include/phy.h b/include/phy.h index 58ca273..7b4ce74 100644 --- a/include/phy.h +++ b/include/phy.h @@ -223,6 +223,7 @@ int gen10g_discover_mmds(struct phy_device *phydev); int phy_atheros_init(void); int phy_broadcom_init(void); int phy_davicom_init(void); +int phy_et1011c_init(void); int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_init(void);
On Fri, Mar 15, 2013 at 04:58:19PM -0400, Matt Porter wrote:
Adds an ET1011C PHY driver which is derived from the current Linux kernel PHY driver. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the TI814x-EVM.
You need to specify the git hash or tag, not just "current".
The code itself is fine, so
Reviewed-by: Tom Rini trini@ti.com
Adds CPSW support to the TI814X EVM configured with an ET1011C PHY in GMII mode.
Signed-off-by: Matt Porter mporter@ti.com --- board/ti/ti814x/evm.c | 72 ++++++++++++++++++++++++++++++++++++++++++ board/ti/ti814x/evm.h | 1 + board/ti/ti814x/mux.c | 35 ++++++++++++++++++++ include/configs/ti814x_evm.h | 21 ++++++++++++ 4 files changed, 129 insertions(+)
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 8513220..d6c19f5 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -17,6 +17,7 @@ */
#include <common.h> +#include <cpsw.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> @@ -39,6 +40,8 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #endif
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + /* UART Defines */ #ifdef CONFIG_SPL_BUILD #define UART_RESET (0x1 << 1) @@ -166,6 +169,9 @@ void s_init(void) /* Set MMC pins */ enable_mmc1_pin_mux();
+ /* Set Ethernet pins */ + enable_enet_pin_mux(); + /* Enable UART */ uart_enable();
@@ -199,3 +205,69 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x50, + .sliver_reg_ofs = 0x700, + .phy_id = 1, + }, + { + .slave_reg_ofs = 0x90, + .sliver_reg_ofs = 0x740, + .phy_id = 0, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x100, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0x600, + .ale_entries = 1024, + .host_port_reg_ofs = 0x28, + .hw_stats_reg_ofs = 0x400, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_1, +}; +#endif + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + printf("Unable to read MAC address. Set <ethaddr>\n"); + } + + return cpsw_register(&cpsw_data); +} diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h index 40f8710..6aebec6 100644 --- a/board/ti/ti814x/evm.h +++ b/board/ti/ti814x/evm.h @@ -3,5 +3,6 @@
void enable_uart0_pin_mux(void); void enable_mmc1_pin_mux(void); +void enable_enet_pin_mux(void);
#endif /* _EVM_H */ diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c index 137acb4..fd9f364 100644 --- a/board/ti/ti814x/mux.c +++ b/board/ti/ti814x/mux.c @@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = { {-1}, };
+static struct module_pin_mux enet_pin_mux[] = { + {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */ + {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */ + {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */ + {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */ + {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */ + {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */ + {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */ + {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */ + {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */ + {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */ + {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */ + {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */ + {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */ + {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */ + {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */ + {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */ + {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */ + {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */ + {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */ + {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */ + {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */ + {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */ + {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */ + {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */ + {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */ + {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */ + {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */ +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -49,3 +79,8 @@ void enable_mmc1_pin_mux(void) { configure_module_pin_mux(mmc1_pin_mux); } + +void enable_enet_pin_mux(void) +{ + configure_module_pin_mux(enet_pin_mux); +} diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 4cbd789..ce0541a 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -217,4 +217,25 @@ /* Unsupported features */ #undef CONFIG_USE_IRQ
+/* Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_ET1011C +#define CONFIG_PHY_ET1011C_TX_CLK_FIX + #endif /* ! __CONFIG_TI814X_EVM_H */
On Fri, Mar 15, 2013 at 04:58:20PM -0400, Matt Porter wrote:
Adds CPSW support to the TI814X EVM configured with an ET1011C PHY in GMII mode.
Signed-off-by: Matt Porter mporter@ti.com
Reviewed-by: Tom Rini trini@ti.com
participants (2)
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Matt Porter -
Tom Rini