[PATCH 00/11] cache operation cleanups for Andes AE350 platform
This patchset is intended to enable L2-cache in U-boot SPL, along with cache operations cleanup for AE350 platforms.
Leo Yu-Chi Liang (1): riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
Yu Chien Peter Lin (10): riscv: global_data.h: Correct the comment for PLICSW board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() riscv: ae350: dts: Update L2 cache compatible string riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL configs: ae350: Enable v5l2 cache for AE350 platforms configs: ae350: Increase maximum retry count for AE350 platforms configs: ae350: Display CPU and board info for AE350 platforms driver: cache-v5l2: Fix type casting warning on RV32
arch/riscv/cpu/ax25/Kconfig | 10 -- arch/riscv/cpu/ax25/cache.c | 120 ++++++++---------------- arch/riscv/cpu/ax25/cpu.c | 46 +++------ arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++ arch/riscv/include/asm/global_data.h | 2 +- board/AndesTech/ax25-ae350/ax25-ae350.c | 17 ++-- configs/ae350_rv32_defconfig | 4 + configs/ae350_rv32_spl_defconfig | 6 ++ configs/ae350_rv32_spl_xip_defconfig | 6 ++ configs/ae350_rv32_xip_defconfig | 4 + configs/ae350_rv64_defconfig | 4 + configs/ae350_rv64_spl_defconfig | 6 ++ configs/ae350_rv64_spl_xip_defconfig | 6 ++ configs/ae350_rv64_xip_defconfig | 4 + drivers/cache/Kconfig | 1 - drivers/cache/cache-v5l2.c | 36 +++++-- 18 files changed, 158 insertions(+), 147 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h
PLIC is used for external interrupt, while PLICSW is an Andes-specific design for software interrupt.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 6fdc86dd8b..31ba72693d 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -22,7 +22,7 @@ struct arch_global_data { void __iomem *clint; /* clint base address */ #endif #ifdef CONFIG_ANDES_PLICSW - void __iomem *plicsw; /* plic base address */ + void __iomem *plicsw; /* andes plicsw base address */ #endif #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS];
On Thu, Jan 19, 2023 at 03:05:34PM +0800, Yu Chien Peter Lin wrote:
PLIC is used for external interrupt, while PLICSW is an Andes-specific design for software interrupt.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
From: Leo Yu-Chi Liang ycliang@andestech.com
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang ycliang@andestech.com Reviewed-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/cpu/ax25/Kconfig | 10 ----- arch/riscv/cpu/ax25/cache.c | 84 +------------------------------------ drivers/cache/Kconfig | 1 - 3 files changed, 2 insertions(+), 93 deletions(-)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 4a7295d30c..eca68ea2a7 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -12,13 +12,3 @@ config RISCV_NDS help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. - -if RISCV_NDS - -config RISCV_NDS_CACHE - bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - Provide Andes Technology AndeStar V5 families specific cache support. - -endif diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 35f23c748d..1c0c3772a1 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
void icache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif }
void icache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "fence.i\n\t" - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif }
void dcache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_enable(); -#endif -#endif -#endif }
void dcache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_disable(); -#endif -#endif -#endif }
int icache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; }
int dcache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; } diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 40f41a817c..6cb8c3e980 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -25,7 +25,6 @@ config L2X0_CACHE config V5L2_CACHE bool "Andes V5L2 cache driver" select CACHE - depends on RISCV_NDS_CACHE help Support Andes V5L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the
On Thu, Jan 19, 2023 at 03:05:35PM +0800, Yu Chien Peter Lin wrote:
From: Leo Yu-Chi Liang ycliang@andestech.com
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang ycliang@andestech.com Reviewed-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/cpu/ax25/Kconfig | 10 ----- arch/riscv/cpu/ax25/cache.c | 84 +------------------------------------ drivers/cache/Kconfig | 1 - 3 files changed, 2 insertions(+), 93 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
The L2-cache is not enabled currently, the enbale_caches() will call the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 63a966e092..1c2288b6ce 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <flash.h> #include <image.h> #include <init.h> @@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err) return NULL; }
+#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init() +{ + /* enable v5l2 cache */ + enable_caches(); +} +#endif + int smc_init(void) { int node = -1; @@ -96,18 +105,10 @@ int smc_init(void) return 0; }
-static void v5l2_init(void) -{ - struct udevice *dev; - - uclass_get_device(UCLASS_CACHE, 0, &dev); -} - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); - v5l2_init();
return 0; }
On Thu, Jan 19, 2023 at 03:05:36PM +0800, Yu Chien Peter Lin wrote:
The L2-cache is not enabled currently, the enbale_caches() will call the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index bbdb76bd57..e782430c57 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -34,6 +34,14 @@ struct l2cache { volatile u64 cctl_status; };
+/* Configuration register */ +#define MEM_MAP_OFF 20 +#define MEM_MAP_MSK BIT(MEM_MAP_OFF) +/* offset of v0 memory map (Gen1) */ +static u32 cmd_stride = 0x10; +static u32 status_stride = 0x0; +static u32 status_bit_offset = 0x4; + /* Control Register */ #define L2_ENABLE 0x1 /* prefetch */ @@ -53,14 +61,15 @@ struct l2cache { #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
/* CCTL Command Register */ -#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride)) #define L2_WBINVAL_ALL 0x12
/* CCTL Status Register */ -#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) -#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) -#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) -#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) +#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride)) +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset)))
DECLARE_GLOBAL_DATA_PTR;
@@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev) { struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs = plat->regs; - u32 ctl_val; + u32 cfg_val, ctl_val;
+ cfg_val = readl(®s->configure); ctl_val = readl(®s->control);
- if (!(ctl_val & L2_ENABLE)) - ctl_val |= L2_ENABLE; + /* If true, v1 memory map (Gen2) */ + if (cfg_val & MEM_MAP_MSK) { + cmd_stride = 0x1000; + status_stride = 0x1000; + status_bit_offset = 0x0; + } + + ctl_val |= L2_ENABLE;
if (plat->iprefetch != -EINVAL) { ctl_val &= ~(IPREPETCH_MSK);
On Thu, Jan 19, 2023 at 03:05:37PM +0800, Yu Chien Peter Lin wrote:
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
This patch improves the cache enabling operation in harts_early_init(), also moves the CSR definition to include/asm/arch-andes/csr.h and drops unnecessary i/d-cache disable functions from cleanup_before_linux().
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/cpu/ax25/cpu.c | 46 +++++++------------------ arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef0..d335b8d0a8 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Andes Technology Corporation + * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation rick@andestech.com */
@@ -10,21 +10,7 @@ #include <irq_func.h> #include <asm/cache.h> #include <asm/csr.h> - -#define CSR_MCACHE_CTL 0x7ca -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 - -#define V5_MCACHE_CTL_IC_EN_OFFSET 0 -#define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 -#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) - +#include <asm/arch-andes/csr.h>
/* * cleanup_before_linux() is called just before we call linux @@ -36,36 +22,30 @@ int cleanup_before_linux(void) { disable_interrupts();
- /* turn off I/D-cache */ cache_flush(); - icache_disable(); - dcache_disable();
return 0; }
void harts_early_init(void) { + /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + + mcache_ctl_val |= MCACHE_CTL_DC_COHEN; + mcache_ctl_val |= MCACHE_CTL_IC_EN; + mcache_ctl_val |= MCACHE_CTL_DC_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/* - * Check DC_COHEN_EN, if cannot write to mcache_ctl, - * we assume this bitmap not support L2 CM + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. */ - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { - /* Wait for DC_COHSTA bit be set */ - while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA)); } } } diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h new file mode 100644 index 0000000000..a03ccd5b3e --- /dev/null +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ + +#ifndef _ASM_ANDES_CSR_H +#define _ASM_ANDES_CSR_H + +#include <asm/asm.h> +#include <linux/const.h> + +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 +#define CSR_MCCTLCOMMAND 0x7cc + +#define MCACHE_CTL_IC_EN_OFFSET 0 +#define MCACHE_CTL_DC_EN_OFFSET 1 +#define MCACHE_CTL_DC_COHEN_OFFSET 19 +#define MCACHE_CTL_DC_COHSTA_OFFSET 20 + +#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) +#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) +#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) +#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) + +#define CCTL_L1D_WBINVAL_ALL 6 + +#endif /* _ASM_ANDES_CSR_H */
Hi Peter, On Thu, Jan 19, 2023 at 03:05:38PM +0800, Yu Chien Peter Lin wrote:
This patch improves the cache enabling operation in harts_early_init(), also moves the CSR definition to include/asm/arch-andes/csr.h and drops unnecessary i/d-cache disable functions from cleanup_before_linux().
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/cpu/ax25/cpu.c | 46 +++++++------------------ arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef0..d335b8d0a8 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -1,6 +1,6 @@ void harts_early_init(void) {
- /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);mcache_ctl_val |= MCACHE_CTL_DC_COHEN;mcache_ctl_val |= MCACHE_CTL_IC_EN;mcache_ctl_val |= MCACHE_CTL_DC_EN;
These three could be combined into one statement. With your consent, I could modify this when applying to u-boot-riscv/master.
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
* Check DC_COHEN_EN, if cannot write to mcache_ctl,* we assume this bitmap not support L2 CM
* Check mcache_ctl.DC_COHEN, we assume this platform does* not support CM if the bit is hard-wired to 0.
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {/* Wait for DC_COHSTA bit be set */while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {/* Wait for DC_COHSTA bit to be set */while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA));}
Best regards, Leo
Hi Leo,
On Tue, Jan 31, 2023 at 07:07:02AM +0000, Leo Liang wrote:
Hi Peter, On Thu, Jan 19, 2023 at 03:05:38PM +0800, Yu Chien Peter Lin wrote:
This patch improves the cache enabling operation in harts_early_init(), also moves the CSR definition to include/asm/arch-andes/csr.h and drops unnecessary i/d-cache disable functions from cleanup_before_linux().
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/cpu/ax25/cpu.c | 46 +++++++------------------ arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef0..d335b8d0a8 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -1,6 +1,6 @@ void harts_early_init(void) {
- /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);mcache_ctl_val |= MCACHE_CTL_DC_COHEN;mcache_ctl_val |= MCACHE_CTL_IC_EN;mcache_ctl_val |= MCACHE_CTL_DC_EN;These three could be combined into one statement. With your consent, I could modify this when applying to u-boot-riscv/master.
Thanks, I also want to improve the comment, I'll update this along with the next patch.
Best regards, Peter Lin
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
* Check DC_COHEN_EN, if cannot write to mcache_ctl,* we assume this bitmap not support L2 CM
* Check mcache_ctl.DC_COHEN, we assume this platform does* not support CM if the bit is hard-wired to 0.
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {/* Wait for DC_COHSTA bit be set */while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {/* Wait for DC_COHSTA bit to be set */while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA));}
Best regards, Leo
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- drivers/cache/cache-v5l2.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 96ef8bd8dd..61af6d5465 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -112,7 +112,7 @@ };
L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0xe0500000 0x40000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index cddbaec98a..8c7db29b4f 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -112,7 +112,7 @@ };
L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index e782430c57..c6d3a8f893 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -184,7 +184,7 @@ static int v5l2_probe(struct udevice *dev) }
static const struct udevice_id v5l2_cache_ids[] = { - { .compatible = "v5l2cache" }, + { .compatible = "cache" }, {} };
On Thu, Jan 19, 2023 at 03:05:39PM +0800, Yu Chien Peter Lin wrote:
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- drivers/cache/cache-v5l2.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
This patch refines L1 cache enable/disable and v5l2-cache enable functions.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/cpu/ax25/cache.c | 100 ++++++++++++++++++++++++------------ 1 file changed, 68 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 1c0c3772a1..ed12c83e7e 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -1,57 +1,49 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Andes Technology Corporation + * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation rick@andestech.com */
+#include <asm/csr.h> +#include <asm/asm.h> #include <common.h> +#include <cache.h> #include <cpu_func.h> #include <dm.h> -#include <asm/cache.h> #include <dm/uclass-internal.h> -#include <cache.h> -#include <asm/csr.h> - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) -/* mcctlcommand */ -#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc +#include <asm/arch-andes/csr.h>
-/* D-cache operation */ -#define CCTL_L1D_WBINVAL_ALL 6 -#endif -#endif - -#ifdef CONFIG_V5L2_CACHE -static void _cache_enable(void) +void enable_caches(void) { - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_enable(dev); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(v5l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable v5l2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("v5l2 cache enable failed\n"); + } }
-static void _cache_disable(void) +static void cache_ops(int (*ops)(struct udevice *dev)) { struct udevice *dev = NULL;
uclass_find_first_device(UCLASS_CACHE, &dev);
if (dev) - cache_disable(dev); + ops(dev); } -#endif
void flush_dcache_all(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE #if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); -#endif -#endif + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); #endif }
@@ -67,26 +59,70 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
void icache_enable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif }
void icache_disable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif }
void dcache_enable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_enable); +#endif }
void dcache_disable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_disable); +#endif }
int icache_status(void) { - return 0; + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; }
int dcache_status(void) { - return 0; + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; }
On Thu, Jan 19, 2023 at 03:05:40PM +0800, Yu Chien Peter Lin wrote:
This patch refines L1 cache enable/disable and v5l2-cache enable functions.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
arch/riscv/cpu/ax25/cache.c | 100 ++++++++++++++++++++++++------------ 1 file changed, 68 insertions(+), 32 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
Enable cache-v5l2 driver for each AE350 defconfig.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 3 +++ configs/ae350_rv32_spl_xip_defconfig | 3 +++ configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 3 +++ configs/ae350_rv64_spl_xip_defconfig | 3 +++ configs/ae350_rv64_xip_defconfig | 1 + 8 files changed, 16 insertions(+)
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index e5c8358e54..5bcc7b9526 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index a66db65621..688c2c15cd 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -34,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 606962c0a7..07bef47e42 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -35,6 +37,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 069a9d3982..235a496c58 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index c373b99b95..af23f27ade 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index f235db7990..295b56835f 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -34,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4cbfd52fb1..497e6c0155 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -35,6 +37,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 4fed2ead1d..5bc45932a8 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_V5L2_CACHE=y CONFIG_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y
On Thu, Jan 19, 2023 at 03:05:41PM +0800, Yu Chien Peter Lin wrote:
Enable cache-v5l2 driver for each AE350 defconfig.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 3 +++ configs/ae350_rv32_spl_xip_defconfig | 3 +++ configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 3 +++ configs/ae350_rv64_spl_xip_defconfig | 3 +++ configs/ae350_rv64_xip_defconfig | 1 + 8 files changed, 16 insertions(+)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
Loading image over TFTP is often interrupted since it does more than 10 times retries, increase the number of retries so it will not easily stop the transmission.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + configs/ae350_rv64_xip_defconfig | 1 + 8 files changed, 8 insertions(+)
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 5bcc7b9526..74170544e9 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 688c2c15cd..f2bdea1096 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 07bef47e42..e1d9ce09d3 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 235a496c58..b844abb699 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index af23f27ade..4e3091d5f4 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 295b56835f..8b7a7b4061 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 497e6c0155..0346ca7b9d 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 5bc45932a8..f1017c8212 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_V5L2_CACHE=y
On Thu, Jan 19, 2023 at 03:05:42PM +0800, Yu Chien Peter Lin wrote:
Loading image over TFTP is often interrupted since it does more than 10 times retries, increase the number of retries so it will not easily stop the transmission.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + configs/ae350_rv64_xip_defconfig | 1 + 8 files changed, 8 insertions(+)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
Display information about CPU and board during start up.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- configs/ae350_rv32_defconfig | 2 ++ configs/ae350_rv32_spl_defconfig | 2 ++ configs/ae350_rv32_spl_xip_defconfig | 2 ++ configs/ae350_rv32_xip_defconfig | 2 ++ configs/ae350_rv64_defconfig | 2 ++ configs/ae350_rv64_spl_defconfig | 2 ++ configs/ae350_rv64_spl_xip_defconfig | 2 ++ configs/ae350_rv64_xip_defconfig | 2 ++ 8 files changed, 16 insertions(+)
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 74170544e9..d09f33ddc7 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f2bdea1096..db14f7db27 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -19,6 +19,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e1d9ce09d3..28f3e69db6 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -20,6 +20,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b844abb699..7c42f1da9f 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 4e3091d5f4..fefb553355 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -14,6 +14,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 8b7a7b4061..2c2f002be7 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -19,6 +19,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 0346ca7b9d..aa16d2fb1a 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -20,6 +20,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index f1017c8212..e59ca82a02 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -15,6 +15,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000
On Thu, Jan 19, 2023 at 03:05:43PM +0800, Yu Chien Peter Lin wrote:
Display information about CPU and board during start up.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
configs/ae350_rv32_defconfig | 2 ++ configs/ae350_rv32_spl_defconfig | 2 ++ configs/ae350_rv32_spl_xip_defconfig | 2 ++ configs/ae350_rv32_xip_defconfig | 2 ++ configs/ae350_rv64_defconfig | 2 ++ configs/ae350_rv64_spl_defconfig | 2 ++ configs/ae350_rv64_spl_xip_defconfig | 2 ++ configs/ae350_rv64_xip_defconfig | 2 ++ 8 files changed, 16 insertions(+)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
This patch fixes following warning for riscv32 compilation.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- drivers/cache/cache-v5l2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index c6d3a8f893..eda07d3f29 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev) struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs;
- regs = (struct l2cache *)dev_read_addr(dev); + regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev); plat->regs = regs;
plat->iprefetch = -EINVAL;
On Thu, Jan 19, 2023 at 03:05:44PM +0800, Yu Chien Peter Lin wrote:
This patch fixes following warning for riscv32 compilation.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com
drivers/cache/cache-v5l2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com
participants (3)
-
Leo Liang -
Yu Chien Peter Lin -
Yu-Chien Peter Lin