[PATCH 1/4] phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com --- drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-imx8mq-usb.c | 197 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/phy/phy-imx8mq-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a..09cb744 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -268,5 +268,12 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout.
+config PHY_IMX8MQ_USB + bool "NXP i.MX8MQ USB PHY Driver" + depends on PHY + depends on IMX8MQ + help + Support the USB3.0 PHY in NXP i.MX8MQ SoC + source "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673..c6ad3b1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c new file mode 100644 index 0000000..afbc7ad --- /dev/null +++ b/drivers/phy/phy-imx8mq-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <clk.h> + +#define PHY_CTRL0 0x0 +#define PHY_CTRL0_REF_SSP_EN BIT(2) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) +#define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) + +#define PHY_CTRL1 0x4 +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_COMMONONN BIT(1) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2 0x8 +#define PHY_CTRL2_TXENABLEN0 BIT(8) +#define PHY_CTRL2_OTG_DISABLE BIT(9) + +#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29 + +#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15 + +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0) + +#define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) +#define PHY_CTRL6_ALT_CLK_EN BIT(1) +#define PHY_CTRL6_ALT_CLK_SEL BIT(0) + +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + +struct imx8mq_usb_phy { +#if CONFIG_IS_ENABLED(CLK) + struct clk phy_clk; +#endif + void __iomem *base; +}; + +static const struct udevice_id imx8mq_usb_phy_of_match[] = { + { + .compatible = "fsl,imx8mq-usb-phy", + }, + {}, +}; + +static int imx8mq_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_COMMONONN); + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(value, imx_phy->base + PHY_CTRL1); + + value = readl(imx_phy->base + PHY_CTRL0); + value |= PHY_CTRL0_REF_SSP_EN; + value &= ~PHY_CTRL0_SSC_RANGE_MASK; + value |= PHY_CTRL0_SSC_RANGE_4003PPM; + writel(value, imx_phy->base + PHY_CTRL0); + + value = readl(imx_phy->base + PHY_CTRL2); + value |= PHY_CTRL2_TXENABLEN0; + writel(value, imx_phy->base + PHY_CTRL2); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(value, imx_phy->base + PHY_CTRL1); + + return 0; +} + +static int imx8mq_usb_phy_power_on(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + ret = clk_enable(&imx_phy->phy_clk); + if (ret) { + printf("Failed to enable usb phy clock\n"); + return ret; + } +#endif + + /* Disable rx term override */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + + return 0; +} + +static int imx8mq_usb_phy_power_off(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + /* Override rx term to be 0 */ + value = readl(imx_phy->base + PHY_CTRL6); + value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imx_phy->phy_clk); +#endif + + return 0; +} + +static int imx8mq_usb_phy_exit(struct phy *usb_phy) +{ + return imx8mq_usb_phy_power_off(usb_phy); +} + +struct phy_ops imx8mq_usb_phy_ops = { + .init = imx8mq_usb_phy_init, + .power_on = imx8mq_usb_phy_power_on, + .power_off = imx8mq_usb_phy_power_off, + .exit = imx8mq_usb_phy_exit, +}; + +int imx8mq_usb_phy_probe(struct udevice *dev) +{ + struct imx8mq_usb_phy *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + if (!priv->base) + return -EINVAL; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + /* Assigned clock already set clock */ + ret = clk_get_by_name(dev, "phy", &priv->phy_clk); + if (ret) { + printf("Failed to get usb phy clock\n"); + return ret; + } +#endif + + return 0; +} + +U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = { + .name = "nxp_imx8mq_usb_phy", + .id = UCLASS_PHY, + .of_match = imx8mq_usb_phy_of_match, + .probe = imx8mq_usb_phy_probe, + .ops = &imx8mq_usb_phy_ops, + .priv_auto = sizeof(struct imx8mq_usb_phy), +};
Add alias for two DWC3 usb controllers to fix the seq index.
Signed-off-by: Ye Li ye.li@nxp.com --- arch/arm/dts/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index a841a02..a44f729 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -39,6 +39,8 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + usb0 = &usb_dwc3_0; + usb1 = &usb_dwc3_1; };
ckil: clock-ckil {
Am Sun, Feb 21, 2021 at 08:26:22AM -0800 schrieb Ye Li:
Add alias for two DWC3 usb controllers to fix the seq index.
Signed-off-by: Ye Li ye.li@nxp.com
arch/arm/dts/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index a841a02..a44f729 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -39,6 +39,8 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3;
usb0 = &usb_dwc3_0;usb1 = &usb_dwc3_1;
I'm not sure what the policy is. Should changes to the device tree be put into the u-boot.dtsi? At least it isn't part of torvald's master branch. In any case:
Tested-by: Patrick Wildt patrick@blueri.se
};
ckil: clock-ckil {
2.7.4
Add clock function to setup relevant clocks for USB3.0 controllers and PHYs on i.MX8MQ
Signed-off-by: Ye Li ye.li@nxp.com --- arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c545eb8..e806552 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -257,6 +257,7 @@ u32 imx_get_uartclk(void); int clock_init(void); void init_clk_usdhc(u32 index); void init_uart_clk(u32 index); +void init_usb_clk(void); void init_wdog_clk(void); unsigned int mxc_get_clock(enum mxc_clock clk); int clock_enable(enum clk_ccgr_index index, bool enable); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 759ec6d..cccd645 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -393,6 +393,28 @@ void init_wdog_clk(void) clock_enable(CCGR_WDOG3, 1); }
+void init_usb_clk(void) +{ + if (!is_usb_boot()) { + clock_enable(CCGR_USB_CTRL1, 0); + clock_enable(CCGR_USB_CTRL2, 0); + clock_enable(CCGR_USB_PHY1, 0); + clock_enable(CCGR_USB_PHY2, 0); + /* 500MHz */ + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_USB_CTRL1, 1); + clock_enable(CCGR_USB_CTRL2, 1); + clock_enable(CCGR_USB_PHY1, 1); + clock_enable(CCGR_USB_PHY2, 1); + } +}
void init_nand_clk(void) {
Am Sun, Feb 21, 2021 at 08:26:23AM -0800 schrieb Ye Li:
Add clock function to setup relevant clocks for USB3.0 controllers and PHYs on i.MX8MQ
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c545eb8..e806552 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -257,6 +257,7 @@ u32 imx_get_uartclk(void); int clock_init(void); void init_clk_usdhc(u32 index); void init_uart_clk(u32 index); +void init_usb_clk(void); void init_wdog_clk(void); unsigned int mxc_get_clock(enum mxc_clock clk); int clock_enable(enum clk_ccgr_index index, bool enable); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 759ec6d..cccd645 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -393,6 +393,28 @@ void init_wdog_clk(void) clock_enable(CCGR_WDOG3, 1); }
+void init_usb_clk(void) +{
- if (!is_usb_boot()) {
clock_enable(CCGR_USB_CTRL1, 0);clock_enable(CCGR_USB_CTRL2, 0);clock_enable(CCGR_USB_PHY1, 0);clock_enable(CCGR_USB_PHY2, 0);/* 500MHz */clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1));/* 100MHz */clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1));/* 100MHz */clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1));clock_enable(CCGR_USB_CTRL1, 1);clock_enable(CCGR_USB_CTRL2, 1);clock_enable(CCGR_USB_PHY1, 1);clock_enable(CCGR_USB_PHY2, 1);- }
+}
void init_nand_clk(void) { -- 2.7.4
Setup USB clock in board codes, and enable the DWC3 XHCI and PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
Signed-off-by: Ye Li ye.li@nxp.com --- board/freescale/imx8mq_evk/imx8mq_evk.c | 4 ++++ configs/imx8mq_evk_defconfig | 9 +++++++++ 2 files changed, 13 insertions(+)
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 93da67d..e394805 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -86,6 +86,10 @@ int board_init(void) setup_fec(); #endif
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) + init_usb_clk(); +#endif + return 0; }
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index a149c1a..a644862 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -54,3 +54,12 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y
Hi Ye Li,
On Thu, Feb 25, 2021 at 3:36 AM Ye Li ye.li@nxp.com wrote:
Setup USB clock in board codes, and enable the DWC3 XHCI and PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
Signed-off-by: Ye Li ye.li@nxp.com
Thanks for the patch.
Have you tested it in the imx8mq-evk using the latest U-Boot master branch?
The reason I am asking is that imx8mq-evk does not even boot for me unless I apply the following two patches:
https://lists.denx.de/pipermail/u-boot/2021-February/441971.html
https://lists.denx.de/pipermail/u-boot/2021-February/441988.html
Please advise.
Hi Fabio,
On Thu, 2021-02-25 at 08:01 -0300, Fabio Estevam wrote:
Caution: EXT Email
Hi Ye Li,
On Thu, Feb 25, 2021 at 3:36 AM Ye Li ye.li@nxp.com wrote:
Setup USB clock in board codes, and enable the DWC3 XHCI and PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
Signed-off-by: Ye Li ye.li@nxp.com
Thanks for the patch.
Have you tested it in the imx8mq-evk using the latest U-Boot master branch?
The reason I am asking is that imx8mq-evk does not even boot for me unless I apply the following two patches:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis ts.denx.de%2Fpipermail%2Fu-boot%2F2021- February%2F441971.html&data=04%7C01%7Cye.li%40nxp.com%7C16ed6adce 72548e2c57e08d8d97cbf71%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C 637498477099446700%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=10PTxobzvXV UaVhn1Rv1yM5xe0uZk3aluha81cPAK%2Fc%3D&reserved=0
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis ts.denx.de%2Fpipermail%2Fu-boot%2F2021- February%2F441988.html&data=04%7C01%7Cye.li%40nxp.com%7C16ed6adce 72548e2c57e08d8d97cbf71%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C 637498477099446700%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=lyG6qFbrKVf vMjii3vS5fZ3DQTbxinqms%2FO4D1yX4l4%3D&reserved=0
Please advise.
Sure, I have tested it on 8mq evk. I can reproduce the two issues you met. The first issue is caused by the ALIGN. The implementation of standard ALIGN requires the aligned size to be power of 2. But the ALIGN in imx8mimage does not have this requirement. So below result is wrong by using the standard ALIGN. Your fix should be OK for this issue.
file_off += ALIGN(sbuf.st_size, HDMI_FW_SIZE + 0x2000 + 0x1000);
For the second issue, I did not debug into it. But our vendor tree also uses off-on-delay-us in both u-boot and kernel. So it is likely caused by other change.
Attach the log of usb host test.
U-Boot SPL 2021.04-rc2-00059-g1784e9b (Feb 21 2021 - 14:35:00 -0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 E/TC:0 0 caam_mp_init:364 ************************************* E/TC:0 0 caam_mp_init:365 * Warning: Manufacturing protection * E/TC:0 0 caam_mp_init:366 * is not supported * E/TC:0 0 caam_mp_init:367 *************************************
U-Boot 2021.04-rc2-00059-g1784e9b (Feb 21 2021 - 14:35:00 -0800)
CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - No block device, using default environment
In: serial Out: serial Err: serial Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> usb start starting USB... Bus usb@38200000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@38200000 for devices... cannot reset port 1!? 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found u-boot=> usb dev
IDE device 0: Vendor: Kingston Rev: Prod: DataTraveler 3.0 Type: Removable Hard Disk Capacity: 14755.2 MB = 14.4 GB (30218842 x 512) u-boot=> usb read 0x40480000 0x0 0x1000
usb read: device 0 block # 0, count 4096 ... 4096 blocks read: OK
Best regards, Ye Li
Hi Ye Li,
On Thu, Feb 25, 2021 at 10:34 AM Ye Li ye.li@nxp.com wrote:
Sure, I have tested it on 8mq evk. I can reproduce the two issues you met. The first issue is caused by the ALIGN. The implementation of standard ALIGN requires the aligned size to be power of 2. But the ALIGN in imx8mimage does not have this requirement. So below result is wrong by using the standard ALIGN. Your fix should be OK for this issue.
Good, could you please reply to my ALIGN macro patch with your Tested-by tag then?
For the second issue, I did not debug into it. But our vendor tree also uses off-on-delay-us in both u-boot and kernel. So it is likely caused by other change.
Considering we are already at 2021.04-rc2, I think it would be safer to go with my patch that removes off-on-delay-us.
What do you think?
Thanks
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
Caution: EXT Email
Hi Ye Li,
On Thu, Feb 25, 2021 at 10:34 AM Ye Li ye.li@nxp.com wrote:
Sure, I have tested it on 8mq evk. I can reproduce the two issues you met. The first issue is caused by the ALIGN. The implementation of standard ALIGN requires the aligned size to be power of 2. But the ALIGN in imx8mimage does not have this requirement. So below result is wrong by using the standard ALIGN. Your fix should be OK for this issue.
Good, could you please reply to my ALIGN macro patch with your Tested-by tag then?
Replied it.
For the second issue, I did not debug into it. But our vendor tree also uses off-on-delay-us in both u-boot and kernel. So it is likely caused by other change.
Considering we are already at 2021.04-rc2, I think it would be safer to go with my patch that removes off-on-delay-us.
What do you think?
Thanks
My debug shows the issue is triggered by below commit:
commit 9098682200e6cca4b776638a51200dafa16f50fb Author: Haibo Chen haibo.chen@nxp.com Date: Tue Sep 22 18:11:43 2020 +0800
mmc: fsl_esdhc_imx: remove the 1ms delay before sending command This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data. Signed-off-by: Haibo Chen haibo.chen@nxp.com
The first "go idle" command in mmc_get_op_cond seems not put SD card to idle status, but if adding a delay before it (like 1ms delay), then everything works. This commit removed 1ms delay in sending command, so the issue is triggered. The root cause might be "startup-delay-us" needed for this regulator to reach a threshold voltage for SD working. Below change also can fix the issue.
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) ®_usdhc2_vmmc { + startup-delay-us = <1000>; u-boot,off-on-delay-us = <20000>; };
@Haibo, Could you help looking into the issue. What's your opinion to add the startup-delay-us or revert your commit?
Best regards, Ye Li
Hi Ye Li,
On Sat, Feb 27, 2021 at 3:04 AM Ye Li ye.li@nxp.com wrote:
My debug shows the issue is triggered by below commit:
Thanks for investigating this issue. Appreciate it.
commit 9098682200e6cca4b776638a51200dafa16f50fb Author: Haibo Chen haibo.chen@nxp.com Date: Tue Sep 22 18:11:43 2020 +0800
mmc: fsl_esdhc_imx: remove the 1ms delay before sending command This 1ms delay before sending command already exist from thebeginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>The first "go idle" command in mmc_get_op_cond seems not put SD card to idle status, but if adding a delay before it (like 1ms delay), then everything works. This commit removed 1ms delay in sending command, so the issue is triggered. The root cause might be "startup-delay-us" needed for this regulator to reach a threshold voltage for SD working. Below change also can fix the issue.
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
®_usdhc2_vmmc {
startup-delay-us = <1000>; u-boot,off-on-delay-us = <20000>;};
@Haibo, Could you help looking into the issue. What's your opinion to add the startup-delay-us or revert your commit?
As the 1ms delay in the driver has been present since 2008, I prefer to go with the revert for the following reasons:
1) We would need to fix all the esdhc users in devicetree. 2) By adding startup-delay-us only to the U-Boot dts we are deviating from the Linux devicetree once again, which we should avoid.
Thanks,
Fabio Estevam
-----Original Message----- From: Ye Li Sent: 2021年2月27日 14:05 To: festevam@gmail.com; Bough Chen haibo.chen@nxp.com Cc: Peng Fan peng.fan@nxp.com; u-boot@lists.denx.de; dl-uboot-imx uboot-imx@nxp.com; sbabic@denx.de Subject: Re: [EXT] Re: [PATCH 4/4] imx8mq_evk: Enable the USB3.0 host port
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
Caution: EXT Email
Hi Ye Li,
On Thu, Feb 25, 2021 at 10:34 AM Ye Li ye.li@nxp.com wrote:
Sure, I have tested it on 8mq evk. I can reproduce the two issues you met. The first issue is caused by the ALIGN. The implementation of standard ALIGN requires the aligned size to be power of 2. But the ALIGN in imx8mimage does not have this requirement. So below result is wrong by using the standard ALIGN. Your fix should be OK for this issue.
Good, could you please reply to my ALIGN macro patch with your Tested-by tag then?
Replied it.
For the second issue, I did not debug into it. But our vendor tree also uses off-on-delay-us in both u-boot and kernel. So it is likely caused by other change.
Considering we are already at 2021.04-rc2, I think it would be safer to go with my patch that removes off-on-delay-us.
What do you think?
Thanks
My debug shows the issue is triggered by below commit:
commit 9098682200e6cca4b776638a51200dafa16f50fb Author: Haibo Chen haibo.chen@nxp.com Date: Tue Sep 22 18:11:43 2020 +0800
mmc: fsl_esdhc_imx: remove the 1ms delay before sending command This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c.fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>The first "go idle" command in mmc_get_op_cond seems not put SD card to idle status, but if adding a delay before it (like 1ms delay), then everything works. This commit removed 1ms delay in sending command, so the issue is triggered. The root cause might be "startup-delay-us" needed for this regulator to reach a threshold voltage for SD working. Below change also can fix the issue.
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
®_usdhc2_vmmc {
startup-delay-us = <1000>; u-boot,off-on-delay-us = <20000>;};
@Haibo, Could you help looking into the issue. What's your opinion to add the startup-delay-us or revert your commit?
Hi Fabio,
I co-debug with Ye, and find the issue is also related with clock enable/disable. For current logic on imx usdhc, hardware automatically gate off the card clock when idle. So before the first command "go idle", there is no clock on the clock line, which not align with the sd spec. Refer to SD3.0 spec 6.4.1 Power UP The host shall supply power to the card so that the voltage is reached to Vdd_min within 250ms and start to supply at least 74 SD clocks to the SD card with keeping CMD line to high. In case of SPI mode, CS shall be held to high during 74 clock cycles
if we give the card the correct clock rate before the first "go idle" command, this issue gone. Please try to apply the patch I send on 2021/1/27 [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Best regards, Ye Li
Am Wed, Mar 03, 2021 at 08:53:52AM +0000 schrieb Bough Chen:
-----Original Message----- From: Ye Li Sent: 2021年2月27日 14:05 To: festevam@gmail.com; Bough Chen haibo.chen@nxp.com Cc: Peng Fan peng.fan@nxp.com; u-boot@lists.denx.de; dl-uboot-imx uboot-imx@nxp.com; sbabic@denx.de Subject: Re: [EXT] Re: [PATCH 4/4] imx8mq_evk: Enable the USB3.0 host port
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
Caution: EXT Email
Hi Ye Li,
On Thu, Feb 25, 2021 at 10:34 AM Ye Li ye.li@nxp.com wrote:
Sure, I have tested it on 8mq evk. I can reproduce the two issues you met. The first issue is caused by the ALIGN. The implementation of standard ALIGN requires the aligned size to be power of 2. But the ALIGN in imx8mimage does not have this requirement. So below result is wrong by using the standard ALIGN. Your fix should be OK for this issue.
Good, could you please reply to my ALIGN macro patch with your Tested-by tag then?
Replied it.
For the second issue, I did not debug into it. But our vendor tree also uses off-on-delay-us in both u-boot and kernel. So it is likely caused by other change.
Considering we are already at 2021.04-rc2, I think it would be safer to go with my patch that removes off-on-delay-us.
What do you think?
Thanks
My debug shows the issue is triggered by below commit:
commit 9098682200e6cca4b776638a51200dafa16f50fb Author: Haibo Chen haibo.chen@nxp.com Date: Tue Sep 22 18:11:43 2020 +0800
mmc: fsl_esdhc_imx: remove the 1ms delay before sending command This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c.fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>The first "go idle" command in mmc_get_op_cond seems not put SD card to idle status, but if adding a delay before it (like 1ms delay), then everything works. This commit removed 1ms delay in sending command, so the issue is triggered. The root cause might be "startup-delay-us" needed for this regulator to reach a threshold voltage for SD working. Below change also can fix the issue.
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
®_usdhc2_vmmc {
startup-delay-us = <1000>; u-boot,off-on-delay-us = <20000>;};
@Haibo, Could you help looking into the issue. What's your opinion to add the startup-delay-us or revert your commit?
Hi Fabio,
I co-debug with Ye, and find the issue is also related with clock enable/disable. For current logic on imx usdhc, hardware automatically gate off the card clock when idle. So before the first command "go idle", there is no clock on the clock line, which not align with the sd spec. Refer to SD3.0 spec 6.4.1 Power UP The host shall supply power to the card so that the voltage is reached to Vdd_min within 250ms and start to supply at least 74 SD clocks to the SD card with keeping CMD line to high. In case of SPI mode, CS shall be held to high during 74 clock cycles
if we give the card the correct clock rate before the first "go idle" command, this issue gone. Please try to apply the patch I send on 2021/1/27 [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Best regards, Ye Li
Hi,
is this patchset still being reviewed? I think the discussion has moved to some SD card problem, which is fixed now? Would be nice if USB 3.0 worked on i.MX8MQ platforms.
I can also have a look at reviewing the functionality, but I don't think I can spot U-Boot coding style issues.
Best regards, Patrick
Hi Patrick,
On Sat, Jul 10, 2021 at 8:35 PM Patrick Wildt patrick@blueri.se wrote:
is this patchset still being reviewed? I think the discussion has moved to some SD card problem, which is fixed now? Would be nice if USB 3.0
I think you are referring to https://source.denx.de/u-boot/u-boot/-/commit/63756575b42b8b4fb3f59cbbf0cedf...
If so, I had to revert it as it caused boot time regression (10s in SPL + 10 s in U-Boot proper) in several i.MX boards:
https://source.denx.de/u-boot/u-boot/-/commit/f132aab403271ff00c0cfdd3af6504...
I haven't tested USB 3.0 in mainline U-Boot on imx8mq-evk. Maybe Peng or Ye Li can comment.
Regards,
Fabio Estevam
worked on i.MX8MQ platforms.
I can also have a look at reviewing the functionality, but I don't think I can spot U-Boot coding style issues.
Best regards, Patrick
Am Mon, Jul 12, 2021 at 10:28:25AM -0300 schrieb Fabio Estevam:
Hi Patrick,
On Sat, Jul 10, 2021 at 8:35 PM Patrick Wildt patrick@blueri.se wrote:
is this patchset still being reviewed? I think the discussion has moved to some SD card problem, which is fixed now? Would be nice if USB 3.0
I think you are referring to https://source.denx.de/u-boot/u-boot/-/commit/63756575b42b8b4fb3f59cbbf0cedf...
If so, I had to revert it as it caused boot time regression (10s in SPL + 10 s in U-Boot proper) in several i.MX boards:
https://source.denx.de/u-boot/u-boot/-/commit/f132aab403271ff00c0cfdd3af6504...
I haven't tested USB 3.0 in mainline U-Boot on imx8mq-evk. Maybe Peng or Ye Li can comment.
Hi Fabio,
I cherry-picked this USB 3.0 series from Ye Ling on to the MNT Reform2 patchset I sent out, and I'm happy with the results.
Best regards, Patrick
Am Sun, Feb 21, 2021 at 08:26:24AM -0800 schrieb Ye Li:
Setup USB clock in board codes, and enable the DWC3 XHCI and PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
Signed-off-by: Ye Li ye.li@nxp.com
The same change works on the MNT Reform 2 as well.
Reviewed-by: Patrick Wildt patrick@blueri.se
board/freescale/imx8mq_evk/imx8mq_evk.c | 4 ++++ configs/imx8mq_evk_defconfig | 9 +++++++++ 2 files changed, 13 insertions(+)
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 93da67d..e394805 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -86,6 +86,10 @@ int board_init(void) setup_fec(); #endif
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
- init_usb_clk();
+#endif
- return 0;
}
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index a149c1a..a644862 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -54,3 +54,12 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
2.7.4
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-imx8mq-usb.c | 197 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/phy/phy-imx8mq-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a..09cb744 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -268,5 +268,12 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout.
+config PHY_IMX8MQ_USB
- bool "NXP i.MX8MQ USB PHY Driver"
- depends on PHY
- depends on IMX8MQ
- help
Support the USB3.0 PHY in NXP i.MX8MQ SoCsource "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673..c6ad3b1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c new file mode 100644 index 0000000..afbc7ad --- /dev/null +++ b/drivers/phy/phy-imx8mq-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2021 NXP
- */
+#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <clk.h>
+#define PHY_CTRL0 0x0 +#define PHY_CTRL0_REF_SSP_EN BIT(2) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) +#define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21)
+#define PHY_CTRL1 0x4 +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_COMMONONN BIT(1) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20)
+#define PHY_CTRL2 0x8 +#define PHY_CTRL2_TXENABLEN0 BIT(8) +#define PHY_CTRL2_OTG_DISABLE BIT(9)
+#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29
+#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15
+#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0)
+#define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) +#define PHY_CTRL6_ALT_CLK_EN BIT(1) +#define PHY_CTRL6_ALT_CLK_SEL BIT(0)
+#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2)
+struct imx8mq_usb_phy { +#if CONFIG_IS_ENABLED(CLK)
- struct clk phy_clk;
+#endif
- void __iomem *base;
+};
+static const struct udevice_id imx8mq_usb_phy_of_match[] = {
- {
.compatible = "fsl,imx8mq-usb-phy",- },
- {},
+};
+static int imx8mq_usb_phy_init(struct phy *usb_phy) +{
- struct udevice *dev = usb_phy->dev;
- struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
- u32 value;
- value = readl(imx_phy->base + PHY_CTRL1);
- value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
PHY_CTRL1_COMMONONN);- value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
- writel(value, imx_phy->base + PHY_CTRL1);
- value = readl(imx_phy->base + PHY_CTRL0);
- value |= PHY_CTRL0_REF_SSP_EN;
- value &= ~PHY_CTRL0_SSC_RANGE_MASK;
- value |= PHY_CTRL0_SSC_RANGE_4003PPM;
- writel(value, imx_phy->base + PHY_CTRL0);
- value = readl(imx_phy->base + PHY_CTRL2);
- value |= PHY_CTRL2_TXENABLEN0;
- writel(value, imx_phy->base + PHY_CTRL2);
- value = readl(imx_phy->base + PHY_CTRL1);
- value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
- writel(value, imx_phy->base + PHY_CTRL1);
- return 0;
+}
+static int imx8mq_usb_phy_power_on(struct phy *usb_phy) +{
- struct udevice *dev = usb_phy->dev;
- struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
- u32 value;
+#if CONFIG_IS_ENABLED(CLK)
- int ret;
- ret = clk_enable(&imx_phy->phy_clk);
- if (ret) {
printf("Failed to enable usb phy clock\n");return ret;- }
+#endif
- /* Disable rx term override */
- value = readl(imx_phy->base + PHY_CTRL6);
- value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
- writel(value, imx_phy->base + PHY_CTRL6);
- return 0;
+}
+static int imx8mq_usb_phy_power_off(struct phy *usb_phy) +{
- struct udevice *dev = usb_phy->dev;
- struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
- u32 value;
- /* Override rx term to be 0 */
- value = readl(imx_phy->base + PHY_CTRL6);
- value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL;
- writel(value, imx_phy->base + PHY_CTRL6);
+#if CONFIG_IS_ENABLED(CLK)
- clk_disable(&imx_phy->phy_clk);
+#endif
- return 0;
+}
+static int imx8mq_usb_phy_exit(struct phy *usb_phy) +{
- return imx8mq_usb_phy_power_off(usb_phy);
+}
+struct phy_ops imx8mq_usb_phy_ops = {
- .init = imx8mq_usb_phy_init,
- .power_on = imx8mq_usb_phy_power_on,
- .power_off = imx8mq_usb_phy_power_off,
- .exit = imx8mq_usb_phy_exit,
+};
+int imx8mq_usb_phy_probe(struct udevice *dev) +{
- struct imx8mq_usb_phy *priv = dev_get_priv(dev);
- priv->base = dev_read_addr_ptr(dev);
- if (!priv->base)
return -EINVAL;+#if CONFIG_IS_ENABLED(CLK)
- int ret;
- /* Assigned clock already set clock */
- ret = clk_get_by_name(dev, "phy", &priv->phy_clk);
- if (ret) {
printf("Failed to get usb phy clock\n");return ret;- }
+#endif
- return 0;
+}
+U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = {
- .name = "nxp_imx8mq_usb_phy",
- .id = UCLASS_PHY,
- .of_match = imx8mq_usb_phy_of_match,
- .probe = imx8mq_usb_phy_probe,
- .ops = &imx8mq_usb_phy_ops,
- .priv_auto = sizeof(struct imx8mq_usb_phy),
+};
2.7.4
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
Thanks
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
Regards, Stefano
Thanks
On 7/13/21 7:53 AM, Stefano Babic wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
USB3 is Bin.
On 13.07.21 12:39, Marek Vasut wrote:
On 7/13/21 7:53 AM, Stefano Babic wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
USB3 is Bin.
Then delegate on patchwork is wrong as the patches are assigned to you.
Regards, Stefano
Am Tue, Jul 13, 2021 at 12:46:04PM +0200 schrieb Stefano Babic:
On 13.07.21 12:39, Marek Vasut wrote:
On 7/13/21 7:53 AM, Stefano Babic wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
USB3 is Bin.
Then delegate on patchwork is wrong as the patches are assigned to you.
The patches contain a new PHY driver, i.MX8MQ clock init code and device tree change. So it's not really USB, it's just some work in the i.MX8MQ stuff to *enable* USB.
On 7/13/21 1:22 PM, Patrick Wildt wrote:
Am Tue, Jul 13, 2021 at 12:46:04PM +0200 schrieb Stefano Babic:
On 13.07.21 12:39, Marek Vasut wrote:
On 7/13/21 7:53 AM, Stefano Babic wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li: > Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. > > Signed-off-by: Ye Li ye.li@nxp.com
Reviewed-by: Patrick Wildt patrick@blueri.se Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
USB3 is Bin.
Then delegate on patchwork is wrong as the patches are assigned to you.
The patches contain a new PHY driver, i.MX8MQ clock init code and device tree change. So it's not really USB, it's just some work in the i.MX8MQ stuff to *enable* USB.
Then just lets have Stefano pick it all, since its imx anyway, and be done with it.
On 13.07.21 13:53, Marek Vasut wrote:
On 7/13/21 1:22 PM, Patrick Wildt wrote:
Am Tue, Jul 13, 2021 at 12:46:04PM +0200 schrieb Stefano Babic:
On 13.07.21 12:39, Marek Vasut wrote:
On 7/13/21 7:53 AM, Stefano Babic wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt patrick@blueri.se wrote: > > Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li: >> Add the USB PHY driver for i.MX8MQ to work with DWC3 USB >> controller. >> >> Signed-off-by: Ye Li ye.li@nxp.com > > Reviewed-by: Patrick Wildt patrick@blueri.se > Tested-by: Patrick Wildt patrick@blueri.se
It seems Ye Li missed adding Marek on Cc.
Could you please resend the series with Marek on Cc?
I see that the series is already assigned to Marek:
http://patchwork.ozlabs.org/project/uboot/list/?series=230965
So I guess it is enough to inform Marek (in CC) about this and he can review / apply the patches without reposting.
USB3 is Bin.
Then delegate on patchwork is wrong as the patches are assigned to you.
The patches contain a new PHY driver, i.MX8MQ clock init code and device tree change. So it's not really USB, it's just some work in the i.MX8MQ stuff to *enable* USB.
Then just lets have Stefano pick it all, since its imx anyway, and be done with it.
Right, it looks like I took advantage that patches were not assigned to me and I have simply ignored...
I set myself as delegate and I will pick them up.
Regards, Stefano
participants (6)
-
Bough Chen -
Fabio Estevam -
Marek Vasut -
Patrick Wildt -
Stefano Babic -
Ye Li