Hi Tom,

Please pull some riscv updates: 1. Improve cache implementation. 2. Fix and improve standalone applications

https://travis-ci.org/rickchen36/u-boot-riscv/builds/479684449

Thanks

Rick

The following changes since commit d3689267f92c5956e09cc7d1baa4700141662bff:

Prepare v2019.01 (2019-01-14 17:02:36 -0500)

are available in the Git repository at:

git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 91882c472d8c0aef4db699d3f2de55bf43d4ae4b:

riscv: qemu: define standalone load address (2019-01-15 09:36:31 +0800)

---------------------------------------------------------------- Lukas Auer (7): riscv: clarify error message on undefined exceptions riscv: move the AX25-specific implementation of flush_dcache_all riscv: use invalidate/flush_*cache_range functions in cache.c riscv: remove RISC-V standalone linker script riscv: replace use of callee-saved register in standalone riscv: support standalone applications on RV64I systems riscv: qemu: define standalone load address

arch/riscv/config.mk | 3 +-- arch/riscv/cpu/ax25/cache.c | 22 ++++++++++++++++++++++ arch/riscv/lib/cache.c | 14 ++++++-------- arch/riscv/lib/interrupts.c | 3 ++- examples/standalone/riscv.lds | 40 ---------------------------------------- examples/standalone/stubs.c | 21 ++++++++++++++++----- include/configs/qemu-riscv.h | 2 ++ 7 files changed, 49 insertions(+), 56 deletions(-) delete mode 100644 examples/standalone/riscv.lds