[U-Boot] [PATCH 1/2] openrisc: update SPR registers definition
The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register.
Signed-off-by: Franck Jullien franck.jullien@gmail.com --- arch/openrisc/include/asm/spr-defs.h | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h index cb0cdfa..b3b08db 100644 --- a/arch/openrisc/include/asm/spr-defs.h +++ b/arch/openrisc/include/asm/spr-defs.h @@ -49,6 +49,11 @@ #define SPR_ICCFGR (SPRGROUP_SYS + 6) #define SPR_DCFGR (SPRGROUP_SYS + 7) #define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_VR2 (SPRGROUP_SYS + 9) +#define SPR_AVR (SPRGROUP_SYS + 10) +#define SPR_EVBAR (SPRGROUP_SYS + 11) +#define SPR_AECR (SPRGROUP_SYS + 12) +#define SPR_AESR (SPRGROUP_SYS + 13) #define SPR_NPC (SPRGROUP_SYS + 16) #define SPR_SR (SPRGROUP_SYS + 17) #define SPR_PPC (SPRGROUP_SYS + 18) @@ -164,7 +169,13 @@ #define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ #define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ -#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ +#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */ +#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */ +#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */ +#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */ +#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */ + /* Arithmetic Exception Status Register (AESR) presents */ +#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
/* * Bit definitions for the Debug configuration register and other
The relocation code can now relocate from anywhere to the RAM.
The old code assumed that the binary was copied to the RAM by some PBL and then it just relocated the .text section from the loaded address to the linked address.
Now, it first checks if vectors are somewhere else than the linked address. If yes, there are copied to address 0 (or to the exception vector base address if register EVBAR is present).
Then, the .text section is relocated from its current location to the RAM.
Signed-off-by: Franck Jullien franck.jullien@gmail.com --- arch/openrisc/cpu/start.S | 55 +++++++++++++++++++++++++++++++++----------- 1 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S index 39c80e1..148242b 100644 --- a/arch/openrisc/cpu/start.S +++ b/arch/openrisc/cpu/start.S @@ -1,6 +1,7 @@ /* * (C) Copyright 2011, Stefan Kristiansson stefan.kristiansson@saunalahti.fi * (C) Copyright 2011, Julius Baxter julius@opencores.org + * (C) Copyright 2014, Franck Jullien franck.jullien@gmail.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,9 +54,48 @@ __reset: l.ori r3,r0,SPR_SR_SM l.mtspr r0,r3,SPR_SR
+ l.jal _cur + l.nop +_cur: + l.ori r8, r9, 0 /* Get _cur current address */ + + l.movhi r3, hi(_cur) + l.ori r3, r3, lo(_cur) + l.sfeq r8, r3 /* If we are running at the linked address */ + l.bf _no_vector_reloc /* there is not need for relocation */ + l.sub r8, r8, r3 + + l.mfspr r4, r0, SPR_CPUCFGR + l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */ + l.sfnei r4,0 + l.bnf _reloc_vectors + l.movhi r5, 0 /* Destination */ + + l.mfspr r4, r0, SPR_EVBAR + l.add r5, r5, r4 + +_reloc_vectors: + /* Relocate vectors*/ + l.movhi r5, 0 /* Destination */ + l.movhi r6, hi(__start) /* Length */ + l.ori r6, r6, lo(__start) + l.ori r3, r8, 0 + +.L_relocvectors: + l.lwz r7, 0(r3) + l.sw 0(r5), r7 + l.addi r5, r5, 4 + l.sfeq r5, r6 + l.bnf .L_relocvectors + l.addi r3, r3, 4 + +_no_vector_reloc: + /* Relocate u-boot */ - l.movhi r3,hi(__start) /* source start address */ + l.movhi r3,hi(__start) /* source start offset */ l.ori r3,r3,lo(__start) + l.add r3,r8,r3 + l.movhi r4,hi(_stext) /* dest start address */ l.ori r4,r4,lo(_stext) l.movhi r5,hi(__end) /* dest end address */ @@ -69,19 +109,6 @@ __reset: l.bf .L_reloc l.addi r4,r4,4 /* delay slot */
-#ifdef CONFIG_SYS_RELOCATE_VECTORS - /* Relocate vectors from 0xf0000000 to 0x00000000 */ - l.movhi r4, 0xf000 /* source */ - l.movhi r5, 0 /* destination */ - l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */ -.L_relocvectors: - l.lwz r7, 0(r4) - l.sw 0(r5), r7 - l.addi r5, r5, 4 - l.sfeq r5,r6 - l.bnf .L_relocvectors - l.addi r4,r4, 4 -#endif l.movhi r4,hi(_start) l.ori r4,r4,lo(_start) l.jr r4
On Wed, May 21, 2014 at 10:43:50PM +0200, Franck Jullien wrote:
The relocation code can now relocate from anywhere to the RAM.
The old code assumed that the binary was copied to the RAM by some PBL and then it just relocated the .text section from the loaded address to the linked address.
Now, it first checks if vectors are somewhere else than the linked address. If yes, there are copied to address 0 (or to the exception vector base address if register EVBAR is present).
Then, the .text section is relocated from its current location to the RAM.
Signed-off-by: Franck Jullien franck.jullien@gmail.com
Applied to u-boot/master, thanks!
On Wed, May 21, 2014 at 10:43:49PM +0200, Franck Jullien wrote:
The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register.
Signed-off-by: Franck Jullien franck.jullien@gmail.com
Applied to u-boot/master, thanks!
participants (2)
-
Franck Jullien -
Tom Rini