[U-Boot] [PATCH] clock_am43xx:Set the MAC clock to /5 for OPP100
From: Steve Kipisz s-kipisz2@ti.com
When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz s-kipisz2@ti.com --- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 3 +++ arch/arm/include/asm/arch-am33xx/cpu.h | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 31188c8..529a119 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -118,4 +118,7 @@ void enable_basic_clocks(void)
/* Select the Master osc clk as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); + + /* For OPP100 the mac clock should be /5. */ + writel(0x4, &cmdpll->clkselmacclk); } diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index b94b56c..523d22e 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -400,6 +400,8 @@ struct prm_device_inst { struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ + unsigned int resv2[11]; + unsigned int clkselmacclk; /* offset 0x34 */ }; #endif /* CONFIG_AM43XX */
From: Ravi Babu ravibabu@ti.com
This patch enables QUAD read mode for qspi to improve the read performace while loading the binaries from qspi.
Signed-off-by: Ravi Babu ravibabu@ti.com --- drivers/spi/ti_qspi.c | 7 +++++++ include/configs/dra7xx_evm.h | 1 + 2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 857b604..3356c0f 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -109,10 +109,17 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->op_mode_rx = 8; #endif
+#ifdef CONFIG_QSPI_QUAD_SUPPORT + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); +#else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; +#endif
writel(memval, &qslave->base->setup0); } diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index dee2b11..8fe0e6c 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -77,6 +77,7 @@ #define CONFIG_TI_SPI_MMAP #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_QSPI_QUAD_SUPPORT
/* * Default to using SPI for environment, etc.
On 12 February 2015 at 05:24, Tom Rini trini@ti.com wrote:
From: Ravi Babu ravibabu@ti.com
This patch enables QUAD read mode for qspi to improve the read performace while loading the binaries from qspi.
Signed-off-by: Ravi Babu ravibabu@ti.com
drivers/spi/ti_qspi.c | 7 +++++++ include/configs/dra7xx_evm.h | 1 + 2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 857b604..3356c0f 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -109,10 +109,17 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->op_mode_rx = 8; #endif
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |QSPI_SETUP0_NUM_D_BYTES_8_BITS |QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |QSPI_NUM_DUMMY_BITS);+#else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; +#endif
writel(memval, &qslave->base->setup0);} diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index dee2b11..8fe0e6c 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -77,6 +77,7 @@ #define CONFIG_TI_SPI_MMAP #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_QSPI_QUAD_SUPPORT
/*
- Default to using SPI for environment, etc.
-- 1.7.9.5
Applied to u-boot-spi/master
thanks!
On Wed, Feb 11, 2015 at 06:54:28PM -0500, Tom Rini wrote:
From: Steve Kipisz s-kipisz2@ti.com
When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz s-kipisz2@ti.com
Applied to u-boot/master, thanks!
participants (2)
-
Jagan Teki -
Tom Rini