[PATCH 1/3] arm64: renesas: Split R-Car Gen3 and Gen4 common board code
Split common board code for R-Car Gen3 and Gen4 into separate files. The R-Car Gen3 board code contains fixups specific to TFA which are no longer required on R-Car Gen4, keep those fixups in its own file so they would not interfere with Gen4.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Adam Ford aford173@gmail.com Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Simon Glass sjg@chromium.org Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- board/beacon/beacon-rzg2m/Makefile | 2 +- board/hoperun/hihope-rzg2/Makefile | 2 +- board/renesas/condor/Makefile | 2 +- board/renesas/draak/Makefile | 2 +- board/renesas/eagle/Makefile | 2 +- board/renesas/ebisu/Makefile | 2 +- board/renesas/rcar-common/common.c | 174 ---------------------- board/renesas/rcar-common/gen3-common.c | 185 ++++++++++++++++++++++++ board/renesas/rcar-common/gen4-common.c | 14 ++ board/renesas/salvator-x/Makefile | 2 +- board/renesas/ulcb/Makefile | 2 +- board/renesas/v3hsk/Makefile | 2 +- board/renesas/v3msk/Makefile | 2 +- board/silinux/ek874/Makefile | 2 +- 14 files changed, 210 insertions(+), 185 deletions(-) create mode 100644 board/renesas/rcar-common/gen3-common.c
diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile index 9131a92efae..332b41f35c0 100644 --- a/board/beacon/beacon-rzg2m/Makefile +++ b/board/beacon/beacon-rzg2m/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y := beacon-rzg2m.o ../../renesas/rcar-common/common.o +obj-y := beacon-rzg2m.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile index e989e7aacc5..700e26daa2b 100644 --- a/board/hoperun/hihope-rzg2/Makefile +++ b/board/hoperun/hihope-rzg2/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o +obj-y := hihope-rzg2.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile index cb965cde35f..fe3a2fd3b7a 100644 --- a/board/renesas/condor/Makefile +++ b/board/renesas/condor/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ../rcar-common/common.o +obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile index 8859cf902ca..3ed7800b0e9 100644 --- a/board/renesas/draak/Makefile +++ b/board/renesas/draak/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := draak.o ../rcar-common/common.o +obj-y := draak.o ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile index 98164b5ea29..3f5fdab1bc2 100644 --- a/board/renesas/eagle/Makefile +++ b/board/renesas/eagle/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile index 283d3a4ae36..8139391029d 100644 --- a/board/renesas/ebisu/Makefile +++ b/board/renesas/ebisu/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ../rcar-common/common.o +obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 499c31408f6..4e35e0151c9 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -21,26 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ -extern u64 rcar_atf_boot_args[]; - -#define FDT_RPC_PATH "/soc/spi@ee200000" - -static void apply_atf_overlay(void *fdt_blob) -{ - void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); -} - -int fdtdec_board_setup(const void *fdt_blob) -{ - apply_atf_overlay((void *)fdt_blob); - - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -58,158 +38,4 @@ int __weak board_init(void) return 0; }
-#if defined(CONFIG_RCAR_GEN3) -#define RST_BASE 0xE6160000 -#define RST_CA57RESCNT (RST_BASE + 0x40) -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_RSTOUTCR (RST_BASE + 0x58) -#define RST_CA57_CODE 0xA5A5000F -#define RST_CA53_CODE 0x5A5A000F - -void __weak reset_cpu(void) -{ - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) - writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) - writel(RST_CA57_CODE, RST_CA57RESCNT); - else - hang(); -} -#elif defined(CONFIG_RCAR_GEN4) -#define RST_BASE 0xE6160000 /* Domain0 */ -#define RST_SRESCR0 (RST_BASE + 0x18) -#define RST_SPRES 0x5AA58000 - -void __weak reset_cpu(void) -{ - writel(RST_SPRES, RST_SRESCR0); -} -#else -#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) -{ - struct fdt_resource first_mem_res, curr_mem_res; - int curr_mem_reg, first_mem_reg = 0; - int ret; - - for (;;) { - ret = fdt_get_resource(blob, first_mem_node, "reg", - first_mem_reg++, &first_mem_res); - if (ret) /* No more entries, no overlap found */ - return 0; - - curr_mem_reg = 0; - for (;;) { - ret = fdt_get_resource(blob, curr_mem_node, "reg", - curr_mem_reg++, &curr_mem_res); - if (ret) /* No more entries, check next tuple */ - break; - - if (curr_mem_res.end < first_mem_res.start) - continue; - - if (curr_mem_res.start >= first_mem_res.end) - continue; - - log_debug("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n", - first_mem_res.start, first_mem_res.end, - curr_mem_res.start, curr_mem_res.end); - - return 1; - } - } - - return 0; -} - -static void scrub_duplicate_memory(void *blob) -{ - /* - * Scrub duplicate /memory@* node entries here. Some R-Car DTs might - * contain multiple /memory@* nodes, however fdt_fixup_memory_banks() - * either generates single /memory node or updates the first /memory - * node. Any remaining memory nodes are thus potential duplicates. - * - * However, it is not possible to delete all the memory nodes right - * away, since some of those might not be DRAM memory nodes, but some - * sort of other memory. Thus, delete only the memory nodes which are - * in the R-Car3 DBSC ranges. - */ - int mem = 0, first_mem_node = 0; - - for (;;) { - mem = fdt_node_offset_by_prop_value(blob, mem, - "device_type", "memory", 7); - if (mem < 0) - break; - if (!fdtdec_get_is_enabled(blob, mem)) - continue; - - /* First memory node, patched by U-Boot */ - if (!first_mem_node) { - first_mem_node = mem; - continue; - } - - /* Check the remaining nodes and delete duplicates */ - if (!is_mem_overlap(blob, first_mem_node, mem)) - continue; - - /* Delete duplicate node, start again */ - fdt_del_node(blob, mem); - first_mem_node = 0; - mem = 0; - } -} - -static void update_rpc_status(void *blob) -{ - void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - int offset, enabled; - - /* - * Check if the DT fragment received from TF-A had its RPC-IF device node - * enabled. - */ - if (fdt_magic(atf_fdt_blob) != FDT_MAGIC) - return; - - offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH); - if (offset < 0) - return; - - enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset); - if (!enabled) - return; - - /* - * Find the RPC-IF device node, and enable it if it has a flash subnode. - */ - offset = fdt_path_offset(blob, FDT_RPC_PATH); - if (offset < 0) - return; - - if (fdt_subnode_offset(blob, offset, "flash") < 0) - return; - - fdt_status_okay(blob, offset); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - apply_atf_overlay(blob); - scrub_duplicate_memory(blob); - update_rpc_status(blob); - - return 0; -} -#endif #endif diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/rcar-common/gen3-common.c new file mode 100644 index 00000000000..4291e1d5bcb --- /dev/null +++ b/board/renesas/rcar-common/gen3-common.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * board/renesas/rcar-common/gen3-common.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com + * Copyright (C) 2015 Nobuhiro Iwamatsu iwamatsu@nigauri.org + */ + +#include <dm.h> +#include <fdt_support.h> +#include <hang.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <dm/uclass-internal.h> +#include <asm/arch/renesas.h> +#include <linux/libfdt.h> + +#ifdef CONFIG_RCAR_64 + +DECLARE_GLOBAL_DATA_PTR; + +/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ +extern u64 rcar_atf_boot_args[]; + +#define FDT_RPC_PATH "/soc/spi@ee200000" + +static void apply_atf_overlay(void *fdt_blob) +{ + void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); + + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); +} + +int fdtdec_board_setup(const void *fdt_blob) +{ + apply_atf_overlay((void *)fdt_blob); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void __weak reset_cpu(void) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) +{ + struct fdt_resource first_mem_res, curr_mem_res; + int curr_mem_reg, first_mem_reg = 0; + int ret; + + for (;;) { + ret = fdt_get_resource(blob, first_mem_node, "reg", + first_mem_reg++, &first_mem_res); + if (ret) /* No more entries, no overlap found */ + return 0; + + curr_mem_reg = 0; + for (;;) { + ret = fdt_get_resource(blob, curr_mem_node, "reg", + curr_mem_reg++, &curr_mem_res); + if (ret) /* No more entries, check next tuple */ + break; + + if (curr_mem_res.end < first_mem_res.start) + continue; + + if (curr_mem_res.start >= first_mem_res.end) + continue; + + log_debug("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n", + first_mem_res.start, first_mem_res.end, + curr_mem_res.start, curr_mem_res.end); + + return 1; + } + } + + return 0; +} + +static void scrub_duplicate_memory(void *blob) +{ + /* + * Scrub duplicate /memory@* node entries here. Some R-Car DTs might + * contain multiple /memory@* nodes, however fdt_fixup_memory_banks() + * either generates single /memory node or updates the first /memory + * node. Any remaining memory nodes are thus potential duplicates. + * + * However, it is not possible to delete all the memory nodes right + * away, since some of those might not be DRAM memory nodes, but some + * sort of other memory. Thus, delete only the memory nodes which are + * in the R-Car3 DBSC ranges. + */ + int mem = 0, first_mem_node = 0; + + for (;;) { + mem = fdt_node_offset_by_prop_value(blob, mem, + "device_type", "memory", 7); + if (mem < 0) + break; + if (!fdtdec_get_is_enabled(blob, mem)) + continue; + + /* First memory node, patched by U-Boot */ + if (!first_mem_node) { + first_mem_node = mem; + continue; + } + + /* Check the remaining nodes and delete duplicates */ + if (!is_mem_overlap(blob, first_mem_node, mem)) + continue; + + /* Delete duplicate node, start again */ + fdt_del_node(blob, mem); + first_mem_node = 0; + mem = 0; + } +} + +static void update_rpc_status(void *blob) +{ + void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); + int offset, enabled; + + /* + * Check if the DT fragment received from TF-A had its RPC-IF device node + * enabled. + */ + if (fdt_magic(atf_fdt_blob) != FDT_MAGIC) + return; + + offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH); + if (offset < 0) + return; + + enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset); + if (!enabled) + return; + + /* + * Find the RPC-IF device node, and enable it if it has a flash subnode. + */ + offset = fdt_path_offset(blob, FDT_RPC_PATH); + if (offset < 0) + return; + + if (fdt_subnode_offset(blob, offset, "flash") < 0) + return; + + fdt_status_okay(blob, offset); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + apply_atf_overlay(blob); + scrub_duplicate_memory(blob); + update_rpc_status(blob); + + return 0; +} +#endif +#endif diff --git a/board/renesas/rcar-common/gen4-common.c b/board/renesas/rcar-common/gen4-common.c index 36a51bc4190..2abe9660cf8 100644 --- a/board/renesas/rcar-common/gen4-common.c +++ b/board/renesas/rcar-common/gen4-common.c @@ -74,3 +74,17 @@ int board_init(void)
return 0; } + +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __weak reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index 0fc69ba9de6..fe7c78ef2ff 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := salvator-x.o ../rcar-common/common.o +obj-y := salvator-x.o ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index ec2f161feae..c3c2f391e55 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ulcb.o cpld.o ../rcar-common/common.o +obj-y := ulcb.o cpld.o ../rcar-common/gen3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile index b29114c7239..ee04f67d986 100644 --- a/board/renesas/v3hsk/Makefile +++ b/board/renesas/v3hsk/Makefile @@ -10,6 +10,6 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile index f8c4bcdcf9f..63e06a4b5fd 100644 --- a/board/renesas/v3msk/Makefile +++ b/board/renesas/v3msk/Makefile @@ -10,6 +10,6 @@ ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile index 6917a2418ca..879da9edacf 100644 --- a/board/silinux/ek874/Makefile +++ b/board/silinux/ek874/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_XPL_BUILD obj-y := ../../renesas/rcar-common/gen3-spl.o else -obj-y := ek874.o ../../renesas/rcar-common/common.o +obj-y := ek874.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o endif
In case U-Boot runs in EL3, which is the highest privilege level on ARM64, there can be no firmware running that would restrict access to the bottom 128 MiB of DRAM. In fact, it is likely that U-Boot would have to load that firmware into those bottom 128 MiB of DRAM and start that firmware.
Make those bottom 128 MiB of DRAM available in case U-Boot runs in EL3 to allow loading the firmware to that area.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Adam Ford aford173@gmail.com Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Simon Glass sjg@chromium.org Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- board/renesas/rcar-common/common.c | 36 +++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 4e35e0151c9..95a64ab9cec 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <dm/uclass-internal.h> #include <asm/arch/renesas.h> +#include <asm/system.h> #include <linux/libfdt.h>
#ifdef CONFIG_RCAR_64 @@ -23,13 +24,46 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - return fdtdec_setup_mem_size_base(); + int ret = fdtdec_setup_mem_size_base(); + + if (IS_ENABLED(CONFIG_RCAR_GEN4) && current_el() == 3 && + gd->ram_base == 0x48000000) { + /* + * If this U-Boot runs in EL3, make the bottom 128 MiB + * available for loading of follow up firmware blobs. + */ + gd->ram_base -= 0x8000000; + gd->ram_size += 0x8000000; + } + + return ret; }
int dram_init_banksize(void) { + int bank; + fdtdec_setup_memory_banksize();
+ if (!IS_ENABLED(CONFIG_RCAR_GEN4)) + return 0; + + if (current_el() != 3) + return 0; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (gd->bd->bi_dram[bank].start != 0x48000000) + continue; + + /* + * If this U-Boot runs in EL3, make the bottom 128 MiB + * available for loading of follow up firmware blobs. + */ + gd->bd->bi_dram[bank].start -= 0x8000000; + gd->bd->bi_dram[bank].size += 0x8000000; + break; + } + return 0; }
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC. The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts on the CR52 core which immediately brings up the CA76 core, which in turn starts executing the actual SPL. This is achieved by placing a tiny bit of precompiled Aarch32 code at the very beginning of the SPL. The code consists of some 32 instructions, uses APMU to configure CA76 start address to offset 0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80 Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per instruction is 32 instructions. The 32 instructions turned out to be enough to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper. The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and a DT for R8A779G0 V4H White Hawk board and is generated by binman. The u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board, build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin switches according to the R8A779G0 V4H White Hawk board documentation for 40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Adam Ford aford173@gmail.com Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Simon Glass sjg@chromium.org Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- arch/arm/dts/r8a779g0-u-boot.dtsi | 150 ++++++++++++++++++- arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi | 6 + arch/arm/mach-renesas/Kconfig.rcar4 | 10 ++ arch/arm/mach-renesas/include/mach/boot0.h | 58 +++++++ board/renesas/rcar-common/gen4-spl.c | 119 +++++++++++++++ board/renesas/whitehawk/Makefile | 4 + configs/r8a779g0_whitehawk_defconfig | 38 +++++ 7 files changed, 384 insertions(+), 1 deletion(-) create mode 100644 board/renesas/rcar-common/gen4-spl.c
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 42df321178b..90f021299c5 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -7,12 +7,160 @@
#include "r8a779x-u-boot.dtsi"
+/ { + binman: binman { + multiple-images; + + section { + filename = "flash.bin"; + pad-byte = <0xff>; + + /* Offset 0x0000 set to 0x0000_0000 */ + fill@0 { + offset = <0x0>; + size = <0x4>; + fill-byte = [00]; + }; + + /* Offset 0x300c set to 0x0000_0000 */ + fill@300c { + offset = <0x300c>; + size = <0x4>; + fill-byte = [00]; + }; + + /* Offset 0x3154 set to 0xeb21_0000 */ + fill@3154 { + offset = <0x3154>; + size = <0x2>; + fill-byte = [00]; + }; + + fill@3156 { + offset = <0x3156>; + size = <0x1>; + fill-byte = [21]; + }; + + fill@3157 { + offset = <0x3157>; + size = <0x1>; + fill-byte = [eb]; + }; + + /* Offset 0x3264 set to 0x0003_b000 */ + fill@3264 { + offset = <0x3264>; + size = <0x1>; + fill-byte = [00]; + }; + + fill@3265 { + offset = <0x3265>; + size = <0x1>; + fill-byte = [b0]; + }; + + fill@3266 { + offset = <0x3266>; + size = <0x1>; + fill-byte = [03]; + }; + + fill@3267 { + offset = <0x3267>; + size = <0x1>; + fill-byte = [00]; + }; + + u-boot-spl { + offset = <0x40000>; + align-end = <4>; + }; + + u-boot { + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + filename = "u-boot.itb"; + + fit { + description = "U-Boot mainline"; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + type = "standalone"; + /* + * This is in DRAM. We cannot + * use TEXT_BASE here because + * this system uses PIE build + * and TEXT_BASE=0x0 . + */ + entry = <0x44100000>; + load = <0x44100000>; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; + }; + }; + }; + }; + }; + }; +}; + +&cpg { + bootph-all; +}; + +&extalr_clk { + bootph-all; +}; + +&hscif0 { + bootph-all; +}; + +&hscif0_pins { + bootph-all; +}; + +&pfc { + bootph-all; +}; + &rpc { bank-width = <2>; num-cs = <1>; };
-&extalr_clk { +&rst { bootph-all; };
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index 531767cfdb2..85e32208b29 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -22,8 +22,14 @@ };
&rpc { + bootph-all; flash@0 { + bootph-all; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; + +&qspi0_pins { + bootph-all; +}; diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index e80dce11f54..c2812fd75e4 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -17,6 +17,16 @@ config R8A779F0 config R8A779G0 bool "Renesas SoC R8A779G0" select GICV3 + select BINMAN + select SUPPORT_SPL + imply SPL + imply SPL_BOARD_INIT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_SERIAL + imply SPL_SYS_MALLOC_SIMPLE + imply SPL_TINY_MEMSET + imply SPL_USE_TINY_PRINTF imply CLK_R8A779G0 imply PINCTRL_PFC_R8A779G0
diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index fe88a2e0373..9cc0b819e4d 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -6,6 +6,7 @@ #ifndef __BOOT0_H #define __BOOT0_H
+#if IS_ENABLED(CONFIG_RCAR_GEN2) _start: ARM_VECTORS
@@ -19,5 +20,62 @@ _start: .word 0x0badc0d3; .word 0x0badc0d3; #endif +#endif + +#if IS_ENABLED(CONFIG_R8A779G0) + +#ifdef CONFIG_XPL_BUILD + /* r1=0xe6170800 */ + .inst 0xe3a004e6 /* mov r0, #0xe6000000 */ + .inst 0xe3801817 /* orr r1, r0, #0x170000 */ + .inst 0xe3811b02 /* orr r1, r1, #0x800 */ + + /* r0=0xe6280000 */ + .inst 0xe380070a /* orr r0, r0, #0x280000 */ + + /* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */ + .inst 0xe28f3068 /* add r3, pc, #0x68 */ + .inst 0xe3833001 /* orr r3, r3, #1 */ + .inst 0xe5813038 /* str r3, [r1, #56] @ 0x38 */ + + /* APMU_RVBARPHC0 = 0 */ + .inst 0xe3a03000 /* mov r3, #0 */ + .inst 0xe581303c /* str r3, [r1, #60] @ 0x3c */ + + /* PRR & 0xff00 ?= 0x5c00, test if this is V4H or V4M */ + .inst 0xe3a024ff /* mov r2, #0xff000000 */ + .inst 0xe382260f /* orr r2, r2, #0xf00000 */ + .inst 0xe5923044 /* ldr r3, [r2, #68] @ 0x44 */ + .inst 0xe2033cff /* and r3, r3, #0xff00 */ + .inst 0xe3530b17 /* cmp r3, #0x5c00 */ + .inst 0x1a00000a /* bne 68 <reset-0x18> */ + /* if (SoC is V4H) { */ + /* AP_CORE_APSREG_AP_CLUSTER_N_AUX0 |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT */ + .inst 0xe5903010 /* ldr r3, [r0, #16] */ + .inst 0xe3833003 /* orr r3, r3, #3 */ + .inst 0xe5803010 /* str r3, [r0, #16] */ + /* AP_CORE_APSREG_CCI500_AUX |= AP_CORE_APSREG_CCI500_AUX_ACTDIS */ + .inst 0xe3800a09 /* orr r0, r0, #36864 @ 0x9000 */ + .inst 0xe5903010 /* ldr r3, [r0, #16] */ + .inst 0xe3833001 /* orr r3, r3, #1 */ + .inst 0xe5803010 /* str r3, [r0, #16] */ + /* AP_CORE_APSREG_P_CCI500_AUX |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM */ + .inst 0xe3800802 /* orr r0, r0, #131072 @ 0x20000 */ + .inst 0xe5903010 /* ldr r3, [r0, #16] */ + .inst 0xe3833002 /* orr r3, r3, #2 */ + .inst 0xe5803010 /* str r3, [r0, #16] */ + /* } */ + /* APMU_PWRCTRLC0 = CA_CORE0_WUP_REQ */ + .inst 0xe3a03001 /* mov r3, #1 */ + .inst 0xe5813000 /* str r3, [r1] */ + /* Endless loop */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xeafffffd /* b 70 <reset-0x10> */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + /* Offset 0x80 */ +#endif + b reset +#endif
#endif /* __BOOT0_H */ diff --git a/board/renesas/rcar-common/gen4-spl.c b/board/renesas/rcar-common/gen4-spl.c new file mode 100644 index 00000000000..2aca8baf3dd --- /dev/null +++ b/board/renesas/rcar-common/gen4-spl.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen4 Cortex-R52 SPL + * + * Copyright (C) 2024 Marek Vasut marek.vasut+renesas@mailbox.org + */ + +#include <asm/arch/renesas.h> +#include <asm/io.h> +#include <cpu_func.h> +#include <dm/uclass.h> +#include <dm/util.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <linux/bitops.h> +#include <log.h> +#include <mapmem.h> +#include <spl.h> + +#define CNTCR_EN BIT(0) + +#ifdef CONFIG_SPL_BUILD +void board_debug_uart_init(void) +{ +} +#endif + +static void init_generic_timer(void) +{ + const u32 freq = CONFIG_SYS_CLK_FREQ; + + /* Update memory mapped and register based freqency */ + if (IS_ENABLED(CONFIG_ARM64)) + asm volatile("msr cntfrq_el0, %0" :: "r" (freq)); + else + asm volatile("mcr p15, 0, %0, c14, c0, 0" :: "r" (freq)); + + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + if (CONFIG_IS_ENABLED(OF_CONTROL)) { + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + } + + preloader_console_init(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e6780000", &dev); + if (ret) + printf("DBSC5 init failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_RAM, "ram@ffec0000", &dev); + if (ret) + printf("RTVRAM init failed: %d\n", ret); +}; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_SPI; +} + +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + debug("image entry point: 0x%lx\n", spl_image->entry_point); + if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { + typedef void (*image_entry_arg_t)(int, int, int, int) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t)(uintptr_t) spl_image->entry_point; + image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0); + } else { + typedef void __noreturn (*image_entry_noargs_t)(void); + image_entry_noargs_t image_entry = + (image_entry_noargs_t)spl_image->entry_point; + image_entry(); + } +} + +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + +void s_init(void) +{ + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); +} + +void reset_cpu(void) +{ +} diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile index 38726cd79f3..80f92e6b041 100644 --- a/board/renesas/whitehawk/Makefile +++ b/board/renesas/whitehawk/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ #
+ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen4-spl.o +else obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o +endif diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index 758b0ff5c97..dc6fd6333f7 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_WHITEHAWK=y CONFIG_SYS_CLK_FREQ=16666666 CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BARGSIZE=2048 +CONFIG_BINMAN=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779g0-white-hawk.dtb && booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a779g0-white-hawk.dtb" CONFIG_SYS_CBSIZE=2048 @@ -21,3 +22,40 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y CONFIG_BAUDRATE=921600 + +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xeb300000 +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0xeb210000 +CONFIG_SPL_STACK_R_ADDR=0x44000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x48000000 +# CONFIG_SPL_BOARD_INIT is not set +# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set +# CONFIG_SPL_SEPARATE_BSS is not set +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCONF=y +CONFIG_SPL_RAM=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_RAM=y +CONFIG_RAM_RENESAS_DBSC5=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SF_DEFAULT_SPEED=40000000 +# CONFIG_SPL_PARTITIONS is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_SPL_DM_MMC is not set
participants (1)
-
Marek Vasut