[U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Patch 1 of this series moves the GPU initialization code to a more generic place, since newer chips like T210 require extra steps to initialize the GPU (e.g. WPR setup). It also performs VPR initialization at a later time of the bootloader life, so that we can check the status variable right before booting the kernel and patch the DT accordingly.
Patch 2 performs the DT patching using the ft_board_setup() hook.
Alexandre Courbot (2): ARM: tegra: move VPR configuration to a later stage ARM: tegra: enable GPU DT node when appropriate
arch/arm/include/asm/arch-tegra/ap.h | 9 ----- arch/arm/include/asm/arch-tegra/gpu.h | 43 +++++++++++++++++++++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/ap.c | 3 -- arch/arm/mach-tegra/board2.c | 3 ++ arch/arm/mach-tegra/gpu.c | 66 +++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/vpr.c | 35 ------------------- board/nvidia/jetson-tk1/jetson-tk1.c | 8 +++++ board/nvidia/venice2/venice2.c | 8 +++++ include/configs/jetson-tk1.h | 2 ++ include/configs/tegra124-common.h | 3 ++ include/configs/venice2.h | 2 ++ 12 files changed, 136 insertions(+), 48 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/gpu.h create mode 100644 arch/arm/mach-tegra/gpu.c delete mode 100644 arch/arm/mach-tegra/vpr.c
U-boot is responsible for enabling the GPU DT node after all necessary configuration (VPR setup for T124) is performed. In order to be able to check whether this configuration has been performed right before booting the kernel, make it happen during board_init().
Also move VPR configuration into the more generic gpu.c file, which will also host other GPU-related functions, and let boards specify individually whether they need VPR setup or not.
Signed-off-by: Alexandre Courbot acourbot@nvidia.com Cc: Stephen Warren swarren@nvidia.com Cc: Tom Warren twarren@nvidia.com --- arch/arm/include/asm/arch-tegra/ap.h | 9 ------- arch/arm/include/asm/arch-tegra/gpu.h | 27 ++++++++++++++++++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/ap.c | 3 --- arch/arm/mach-tegra/board2.c | 3 +++ arch/arm/mach-tegra/gpu.c | 47 +++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/vpr.c | 35 -------------------------- include/configs/tegra124-common.h | 3 +++ 8 files changed, 81 insertions(+), 48 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/gpu.h create mode 100644 arch/arm/mach-tegra/gpu.c delete mode 100644 arch/arm/mach-tegra/vpr.c
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index ca40e4e0bce6..2d58271e39f9 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -66,15 +66,6 @@ int tegra_get_sku_info(void); /* Do any chip-specific cache config */ void config_cache(void);
-#if defined(CONFIG_TEGRA124) -/* Do chip-specific vpr config */ -void config_vpr(void); -#else -static inline void config_vpr(void) -{ -} -#endif - #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) bool tegra_cpu_is_non_secure(void); #endif diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h new file mode 100644 index 000000000000..b347a21835f5 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/gpu.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TEGRA_GPU_H +#define __ASM_ARCH_TEGRA_GPU_H + +#if defined(CONFIG_TEGRA_GPU) + +void config_gpu(void); +bool gpu_configured(void); + +#else /* CONFIG_TEGRA_GPU */ + +static inline void config_gpu(void) +{ +} + +static inline bool gpu_configured(void) +{ + return false; +} + +#endif /* CONFIG_TEGRA_GPU */ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fefc180b130e..f6f5583d6dd1 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -24,7 +24,7 @@ obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -obj-$(CONFIG_TEGRA124) += vpr.o +obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 0b94e8aaf9c3..70613f9c3649 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -218,7 +218,4 @@ void s_init(void)
/* enable SMMU */ smmu_enable(); - - /* init vpr */ - config_vpr(); } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index ce9b6959efb1..1d7c5eff5587 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -29,6 +29,7 @@ #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/uart.h> #include <asm/arch-tegra/warmboot.h> +#include <asm/arch-tegra/gpu.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif @@ -125,6 +126,8 @@ int board_init(void) clock_init(); clock_verify();
+ config_gpu(); + #ifdef CONFIG_TEGRA_SPI pin_mux_spi(); #endif diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c new file mode 100644 index 000000000000..b2fa50b5400e --- /dev/null +++ b/arch/arm/mach-tegra/gpu.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* Tegra vpr routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra.h> +#include <asm/arch/mc.h> + +#include <fdt_support.h> + +static bool _configured; + +void config_gpu(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + + /* Turn VPR off */ + writel(0, &mc->mc_video_protect_size_mb); + writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, + &mc->mc_video_protect_reg_ctrl); + /* read back to ensure the write went through */ + readl(&mc->mc_video_protect_reg_ctrl); + + debug("configured VPR\n"); + + _configured = true; +} + +bool vpr_configured(void) +{ + return _configured; +} diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/vpr.c deleted file mode 100644 index f695811c9b6d..000000000000 --- a/arch/arm/mach-tegra/vpr.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see http://www.gnu.org/licenses/. - */ - -/* Tegra vpr routines */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/mc.h> - -/* Configures VPR. Right now, all we do is turn it off. */ -void config_vpr(void) -{ - struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; - - /* Turn VPR off */ - writel(0, &mc->mc_video_protect_size_mb); - writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, - &mc->mc_video_protect_reg_ctrl); - /* read back to ensure the write went through */ - readl(&mc->mc_video_protect_reg_ctrl); -} diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 1aee5c89f4c4..a05d2b53c8bf 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -70,4 +70,7 @@ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* GPU needs setup */ +#define CONFIG_TEGRA_GPU + #endif /* _TEGRA124_COMMON_H_ */
T124 requires some specific configuration (VPR setup) to be performed by the bootloader before the GPU can be used. For this reason, the GPU node in the device tree is disabled by default. This patch enables the node if U-boot has performed VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice 2.
Signed-off-by: Alexandre Courbot acourbot@nvidia.com Cc: Stephen Warren swarren@nvidia.com Cc: Tom Warren twarren@nvidia.com --- arch/arm/include/asm/arch-tegra/gpu.h | 16 ++++++++++++++++ arch/arm/mach-tegra/gpu.c | 19 +++++++++++++++++++ board/nvidia/jetson-tk1/jetson-tk1.c | 8 ++++++++ board/nvidia/venice2/venice2.c | 8 ++++++++ include/configs/jetson-tk1.h | 2 ++ include/configs/venice2.h | 2 ++ 6 files changed, 55 insertions(+)
diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h index b347a21835f5..eac73ed5fddf 100644 --- a/arch/arm/include/asm/arch-tegra/gpu.h +++ b/arch/arm/include/asm/arch-tegra/gpu.h @@ -25,3 +25,19 @@ static inline bool gpu_configured(void) }
#endif /* CONFIG_TEGRA_GPU */ + + +#if defined(CONFIG_OF_LIBFDT) + +int gpu_enable_node(void *blob, const char *gpupath); + +#else /* CONFIG_OF_LIBFDT */ + +static inline int gpu_enable_node(void *blob, const char *gpupath) +{ + return 0; +} + +#endif /* CONFIG_OF_LIBFDT */ + +#endif diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index b2fa50b5400e..4ea046d3e5b6 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -45,3 +45,22 @@ bool vpr_configured(void) { return _configured; } + +#if defined(CONFIG_OF_LIBFDT) + +int gpu_enable_node(void *blob, const char *gpupath) +{ + int offset; + + if (vpr_configured()) { + offset = fdt_path_offset(blob, gpupath); + if (offset > 0) { + fdt_status_okay(blob, offset); + debug("enabled GPU node %s\n", gpupath); + } + } + + return 0; +} + +#endif diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 52425a8f6dea..3c21767ce4da 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -11,6 +11,7 @@
#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch-tegra/gpu.h>
#include "pinmux-config-jetson-tk1.h"
@@ -79,3 +80,10 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } #endif /* PCI */ + +int ft_board_setup(void *blob, bd_t *bd) +{ + gpu_enable_node(blob, "/gpu@0,57000000"); + + return 0; +} diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index c56ef129d6c7..3e2b9a7745e9 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch-tegra/gpu.h> #include "pinmux-config-venice2.h"
/* @@ -27,3 +28,10 @@ void pinmux_init(void) pinmux_config_drvgrp_table(venice2_drvgrps, ARRAY_SIZE(venice2_drvgrps)); } + +int ft_board_setup(void *blob, bd_t *bd) +{ + gpu_enable_node(blob, "/gpu@0,57000000"); + + return 0; +} diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 3bbff282df27..b3e649664508 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -82,4 +82,6 @@ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
+#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 1d9d053b3566..bc5080aa27f0 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -64,4 +64,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h"
+#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */
Salut Alexandre,
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
However, I'm still having trouble with X11... Should that be working with linux.git? (haven't tried linux-next.git yet)
Among other errors, it seems that nouveau is looking for firmware nouveau/nvea_fuc409c and nouveau/fuc409c - who should be providing that? It's not in linux-firmware.git [1], and I see no /dev/mmcblk0p* to check whether the original system has such a file (which I doubt, given the nouveau naming). It then falls back to the tegra drm iiuc.
With -rc2 I've seen the system freeze, with -rc3 just not behaving as expected when starting X (with ssh/serial remaining usable).
[ 2.841626] [drm] Initialized drm 1.1.0 20060810 [ 2.846621] 57000000.gpu supply vdd not found, using dummy regulator [ 2.853089] nouveau 57000000.gpu: cannot initialize IOMMU MM [ 2.860518] [drm] not a PCI device; no HDMI [ 2.864814] nouveau [ DEVICE][57000000.gpu] BOOT0 : 0x0ea000a1 [ 2.870932] nouveau [ DEVICE][57000000.gpu] Chipset: GK20A (NVEA) [ 2.877211] nouveau [ DEVICE][57000000.gpu] Family : NVE0 [ 2.916829] nouveau [ INSTMEM][57000000.gpu] using DMA API [ 2.923392] nouveau [ VOLT][57000000.gpu] The default voltage is -22uV [ 2.930297] nouveau [ CLK][57000000.gpu] parent clock rate: 12 Mhz [ 2.938662] nouveau [ CLK][57000000.gpu] --: core 198 MHz [ 3.037837] nouveau [ PGRAPH][57000000.gpu] using external firmware [ 3.044493] nouveau 57000000.gpu: Direct firmware load for nouveau/nvea_fuc409c failed with error -2 [ 3.053843] nouveau 57000000.gpu: Direct firmware load for nouveau/fuc409c failed with error -2 [ 3.062549] nouveau E[ PGRAPH][57000000.gpu] failed to load fuc409c [ 3.069497] [TTM] Zone kernel: Available graphics memory: 373624 kiB [ 3.075927] [TTM] Zone highmem: Available graphics memory: 1032568 kiB [ 3.082480] [TTM] Initializing pool allocator [ 3.086923] [TTM] Initializing DMA pool allocator [ 3.091737] nouveau [ DRM] VRAM: 0 MiB [ 3.095914] nouveau [ DRM] GART: 1048576 MiB [ 3.191777] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000030 [ 3.269831] nouveau E[ DRM] failed to create ce channel, -22 [ 3.365874] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000001 [ 3.443902] nouveau E[ DRM] failed to create kernel channel, -22 [ 3.452322] tegra-hdmi 54280000.hdmi: failed to get HDMI regulator [...] [ 6.817669] +5V_HDMI_CON: supplied by +5V_SYS [ 6.822215] +1.05V_RUN_AVDD_HDMI_PLL: supplied by +1.05V_RUN [ 6.828102] +3.3V_RUN: supplied by +3.3V_SYS [ 6.832438] +3.3V_AVDD_HDMI_AP_GATED: supplied by +3.3V_RUN [ 6.841657] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 6.848317] [drm] No driver support for vblank timestamp query. [ 6.926989] Console: switching to colour frame buffer device 160x64 [ 6.945437] drm drm: fb0: frame buffer device [ 6.949894] drm drm: registered panic notifier [ 6.976420] [drm] Initialized tegra 0.0.0 20120330 on minor 1
Regards, Andreas
[1] https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tre...
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Salut Alexandre,
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
However, I'm still having trouble with X11... Should that be working with linux.git? (haven't tried linux-next.git yet)
Not much better with next-20150723, it finds the IOMMU now but otherwise mostly unchanged:
[ 2.843264] [drm] Initialized drm 1.1.0 20060810 [ 2.850224] tegra-hdmi 54280000.hdmi: failed to get HDMI regulator [...] [ 6.310099] [drm] not a PCI device; no HDMI [ 6.314401] nouveau [ DEVICE][57000000.gpu] BOOT0 : 0x0ea000a1 [ 6.320540] nouveau [ DEVICE][57000000.gpu] Chipset: GK20A (NVEA) [ 6.326847] nouveau [ DEVICE][57000000.gpu] Family : NVE0 [ 6.366513] nouveau [ INSTMEM][57000000.gpu] using IOMMU [ 6.372805] nouveau [ VOLT][57000000.gpu] The default voltage is 1000000uV [ 6.380046] nouveau [ VOLT][57000000.gpu] GPU voltage: 1015000uv [ 6.386400] nouveau [ CLK][57000000.gpu] parent clock rate: 12 Mhz [ 6.394768] nouveau [ CLK][57000000.gpu] --: core 198 MHz [ 6.494884] nouveau [ PGRAPH][57000000.gpu] using external firmware [ 6.501553] nouveau 57000000.gpu: Direct firmware load for nouveau/nvea_fuc409c failed with error -2 [ 6.510923] nouveau 57000000.gpu: Direct firmware load for nouveau/fuc409c failed with error -2 [ 6.519661] nouveau E[ PGRAPH][57000000.gpu] failed to load fuc409c [ 6.526664] [TTM] Zone kernel: Available graphics memory: 373640 kiB [ 6.533201] [TTM] Zone highmem: Available graphics memory: 1032584 kiB [ 6.539797] [TTM] Initializing pool allocator [ 6.544232] [TTM] Initializing DMA pool allocator [ 6.549118] nouveau [ DRM] VRAM: 0 MiB [ 6.553295] nouveau [ DRM] GART: 1048576 MiB [ 6.649608] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000030 [ 6.729044] nouveau E[ DRM] failed to create ce channel, -22 [ 6.825300] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000001 [ 6.904234] nouveau E[ DRM] failed to create kernel channel, -22 [ 6.910976] +5V_HDMI_CON: supplied by +5V_SYS [ 6.915525] +1.05V_RUN_AVDD_HDMI_PLL: supplied by +1.05V_RUN [ 6.921424] +3.3V_RUN: supplied by +3.3V_SYS [ 6.925762] +3.3V_AVDD_HDMI_AP_GATED: supplied by +3.3V_RUN [ 6.934748] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 6.941397] [drm] No driver support for vblank timestamp query. [ 7.020224] Console: switching to colour frame buffer device 160x64 [ 7.038895] drm drm: fb0: frame buffer device [ 7.066961] [drm] Initialized tegra 0.0.0 20120330 on minor 1
Regards, Andreas
On 07/23/2015 02:46 PM, Andreas Färber wrote:
Salut Alexandre,
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
However, I'm still having trouble with X11... Should that be working with linux.git? (haven't tried linux-next.git yet)
X11 with nouveau shouldn't be working (unless there has been significant work I'm not aware of since the last time I tested). However, it should work with the modesetting driver, just without acceleration. To test if nouveau works, you'll want to use something that allows buffer sharing between tegradrm and nouveau like http://github.com/gnurou/kmscube.
Among other errors, it seems that nouveau is looking for firmware nouveau/nvea_fuc409c and nouveau/fuc409c - who should be providing that? It's not in linux-firmware.git [1], and I see no /dev/mmcblk0p* to check whether the original system has such a file (which I doubt, given the nouveau naming). It then falls back to the tegra drm iiuc.
Based on a quick google search, looks like you'll have to pick these files up from this commit: http://git.baserock.org/cgi-bin/cgit.cgi/delta/linux.git/commit/?h=baserock/...
a strange state of things, indeed.. :)
I guess you could also extract them from the files in linux-firmware.
Mikko
With -rc2 I've seen the system freeze, with -rc3 just not behaving as expected when starting X (with ssh/serial remaining usable).
[ 2.841626] [drm] Initialized drm 1.1.0 20060810 [ 2.846621] 57000000.gpu supply vdd not found, using dummy regulator [ 2.853089] nouveau 57000000.gpu: cannot initialize IOMMU MM [ 2.860518] [drm] not a PCI device; no HDMI [ 2.864814] nouveau [ DEVICE][57000000.gpu] BOOT0 : 0x0ea000a1 [ 2.870932] nouveau [ DEVICE][57000000.gpu] Chipset: GK20A (NVEA) [ 2.877211] nouveau [ DEVICE][57000000.gpu] Family : NVE0 [ 2.916829] nouveau [ INSTMEM][57000000.gpu] using DMA API [ 2.923392] nouveau [ VOLT][57000000.gpu] The default voltage is -22uV [ 2.930297] nouveau [ CLK][57000000.gpu] parent clock rate: 12 Mhz [ 2.938662] nouveau [ CLK][57000000.gpu] --: core 198 MHz [ 3.037837] nouveau [ PGRAPH][57000000.gpu] using external firmware [ 3.044493] nouveau 57000000.gpu: Direct firmware load for nouveau/nvea_fuc409c failed with error -2 [ 3.053843] nouveau 57000000.gpu: Direct firmware load for nouveau/fuc409c failed with error -2 [ 3.062549] nouveau E[ PGRAPH][57000000.gpu] failed to load fuc409c [ 3.069497] [TTM] Zone kernel: Available graphics memory: 373624 kiB [ 3.075927] [TTM] Zone highmem: Available graphics memory: 1032568 kiB [ 3.082480] [TTM] Initializing pool allocator [ 3.086923] [TTM] Initializing DMA pool allocator [ 3.091737] nouveau [ DRM] VRAM: 0 MiB [ 3.095914] nouveau [ DRM] GART: 1048576 MiB [ 3.191777] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000030 [ 3.269831] nouveau E[ DRM] failed to create ce channel, -22 [ 3.365874] nouveau E[ PFIFO][57000000.gpu] unsupported engines 0x00000001 [ 3.443902] nouveau E[ DRM] failed to create kernel channel, -22 [ 3.452322] tegra-hdmi 54280000.hdmi: failed to get HDMI regulator [...] [ 6.817669] +5V_HDMI_CON: supplied by +5V_SYS [ 6.822215] +1.05V_RUN_AVDD_HDMI_PLL: supplied by +1.05V_RUN [ 6.828102] +3.3V_RUN: supplied by +3.3V_SYS [ 6.832438] +3.3V_AVDD_HDMI_AP_GATED: supplied by +3.3V_RUN [ 6.841657] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 6.848317] [drm] No driver support for vblank timestamp query. [ 6.926989] Console: switching to colour frame buffer device 160x64 [ 6.945437] drm drm: fb0: frame buffer device [ 6.949894] drm drm: registered panic notifier [ 6.976420] [drm] Initialized tegra 0.0.0 20120330 on minor 1
Regards, Andreas
[1] https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tre...
Hi,
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
However, I'm still having trouble with X11... Should that be working with linux.git? (haven't tried linux-next.git yet)
My understanding is that it's not or you need to use glamour to do so, wayland in theory should work.
Among other errors, it seems that nouveau is looking for firmware nouveau/nvea_fuc409c and nouveau/fuc409c - who should be providing that? It's not in linux-firmware.git [1], and I see no /dev/mmcblk0p* to check whether the original system has such a file (which I doubt, given the nouveau naming). It then falls back to the tegra drm iiuc.
Details of the changes with firmware loading in this patch series here, likely need the patches, or maybe newer ones for it to work: http://www.spinics.net/lists/dri-devel/msg84828.html
Firmware landed upstream here: https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/com...
With -rc2 I've seen the system freeze, with -rc3 just not behaving as expected when starting X (with ssh/serial remaining usable).
Without the above patchset I've seen the lockups too.
Peter
On 07/24/2015 10:07 PM, Peter Robinson wrote:
Hi,
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
However, I'm still having trouble with X11... Should that be working with linux.git? (haven't tried linux-next.git yet)
My understanding is that it's not or you need to use glamour to do so, wayland in theory should work.
Among other errors, it seems that nouveau is looking for firmware nouveau/nvea_fuc409c and nouveau/fuc409c - who should be providing that? It's not in linux-firmware.git [1], and I see no /dev/mmcblk0p* to check whether the original system has such a file (which I doubt, given the nouveau naming). It then falls back to the tegra drm iiuc.
Details of the changes with firmware loading in this patch series here, likely need the patches, or maybe newer ones for it to work: http://www.spinics.net/lists/dri-devel/msg84828.html
Firmware landed upstream here: https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/com...
With -rc2 I've seen the system freeze, with -rc3 just not behaving as expected when starting X (with ssh/serial remaining usable).
Without the above patchset I've seen the lockups too.
Sorry for the delayed reply.
As Peter mentioned, the correct firmware files have landed in linux-firmware, and the loading code using the right paths is in Nouveau. It may not have landed in Linux mainline yet, so for the moment I recommend to use https://github.com/Gnurou/linux/tree/staging/nouveau (can probably be merged into any recent kernel tree) for the kernel and https://github.com/Gnurou/nouveau/tree/staging for Nouveau. This will require Nouveau to be loaded as a module.
As for X, there are two issues to be addressed:
1) The display and render functions are performed by two different DRI nodes, and two different drivers (tegradrm for display, nouveau for render). I suspect the fastest path towards X acceleration is to use the modesetting driver + GLamor. It may require some changes to handle the two different nodes. Modesetting without GLamor should just work, in any case. I really should have a look at this sometime but am hoping someone else will pick that low-hanging fruit. :)
2) Buffers generated by Nouveau use a tiling mode that tegradrm can understand, but it needs to be told about it through a dedicated IOCTL. Without this, buffers would need to be copied into linear buffers before sharing, which would be suboptimal. The kmscube repository linked by Mikko includes the code to do that.
Note that Nouveau's DDX can also somehow work with this patch:
http://comments.gmane.org/gmane.comp.freedesktop.xorg.nouveau/20101
However, I think modesetting + GLamor is the way to do, especially since the DDX solution cannot currently work with the Maxwell GPUs found in Tegra X1 (whereas GLamor should provide acceleration).
In any case, I would be very interested to hear about progress with getting X on Tegra K1. I don't think the effort required is too big.
Good luck! Alex.
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase and merge them?
Thanks, Andreas
Andreas,
-----Original Message----- From: Andreas Färber [mailto:afaerber@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for
newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again.
Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase and merge them?
Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR.
Tom
Thanks, Andreas
-- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg)
-- nvpublic
Alex/Andreas,
-----Original Message----- From: Tom Warren Sent: Tuesday, August 04, 2015 8:41 AM To: 'Andreas Färber'; u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Guillaume Gardet Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Andreas,
-----Original Message----- From: Andreas Färber [mailto:afaerber@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for
newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65
- with these two patches I get a console login on HDMI again.
Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase
and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR.
Tom
Applied to u-boot-tegra/next (along with some other pending Tegra patches for clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset.
PTAL. Also, there doesn't appear to be a 'gpu@0,57000000' property in any t124/t210 DT file. Is that coming in another patch or one I missed?
Thanks,
Tom
Thanks, Andreas
-- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg)
-- nvpublic
On 08/05/2015 08:24 AM, Tom Warren wrote:
Alex/Andreas,
-----Original Message----- From: Tom Warren Sent: Tuesday, August 04, 2015 8:41 AM To: 'Andreas Färber'; u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Guillaume Gardet Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Andreas,
-----Original Message----- From: Andreas Färber [mailto:afaerber@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for
newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65
- with these two patches I get a console login on HDMI again.
Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase
and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR.
Tom
Applied to u-boot-tegra/next (along with some other pending Tegra patches for clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset.
PTAL. Also, there doesn't appear to be a 'gpu@0,57000000' property in any t124/t210 DT file. Is that coming in another patch or one I missed?
Thanks Tom! I have tried your branch and can confirm it is booting Jetson TK1 as expected (i.e. the GPU is in a usable state).
The GPU node is not needed in U-boot's DT files (if that's what you meant). It is present in the kernel though, and that's the DT my patches will modify.
Alex.
-----Original Message----- From: Alex Courbot Sent: Thursday, August 06, 2015 12:58 AM To: Tom Warren; Andreas Färber; u-boot@lists.denx.de Cc: linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
On 08/05/2015 08:24 AM, Tom Warren wrote:
Alex/Andreas,
-----Original Message----- From: Tom Warren Sent: Tuesday, August 04, 2015 8:41 AM To: 'Andreas Färber'; u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Guillaume Gardet Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Andreas,
-----Original Message----- From: Andreas Färber [mailto:afaerber@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-tegra@vger.kernel.org; gnurou@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Am 23.07.2015 um 13:46 schrieb Andreas Färber:
Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:
Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU.
VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for
newer chips.
Tested-by: Andreas Färber afaerber@suse.de
I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65
- with these two patches I get a console login on HDMI again.
Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase
and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR.
Tom
Applied to u-boot-tegra/next (along with some other pending Tegra patches
for clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset.
PTAL. Also, there doesn't appear to be a 'gpu@0,57000000' property in any
t124/t210 DT file. Is that coming in another patch or one I missed?
Thanks Tom! I have tried your branch and can confirm it is booting Jetson TK1 as expected (i.e. the GPU is in a usable state).
The GPU node is not needed in U-boot's DT files (if that's what you meant). It is present in the kernel though, and that's the DT my patches will modify.
Alex.
Thanks, Alex. I'll send a PR with your changes later today.
Tom -- nvpublic
participants (5)
-
Alexandre Courbot -
Andreas Färber -
Mikko Perttunen -
Peter Robinson -
Tom Warren