[PATCH v5 0/6] add support for Theobroma Systems PX30-µQ7 (Ringneck) with Haikou devkit
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30.
It provides the following feature set: * up to 4GB DDR4 * up to 128GB on-module eMMC (with 8-bit 1.8V interface) * SD card (on a baseboard) via edge connector * Fast Ethernet with on-module TI DP83825I PHY * MIPI-DSI/LVDS * MIPI-CSI * USB - 1x USB 2.0 dual-role - 3x USB 2.0 host * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller (STM32 only) * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi * on-module NXP SE05x Secure Element
[1] https://www.theobroma-systems.com/som-product/px30-uq7/
Cheers, Quentin
To: Heiko Stuebner heiko@sntech.de To: Simon Glass sjg@chromium.org To: Philipp Tomsich philipp.tomsich@vrull.eu To: Klaus Goger klaus.goger@theobroma-systems.com Cc: Quentin Schulz foss+uboot@0leil.net Cc: u-boot@lists.denx.de Cc: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- Changes in v5: - added fix for unused variables in px30.c, - fixed missing fdt_support.h inclusion in px30.c, - updated commit log to reference v6.1 and v6.2-rc2 sources for syncing of files instead of linux-next, - rebased on top of master, - Link to v4: https://lore.kernel.org/r/20221017-upstream-ringneck-v4-0-5e0a3f119047@theob...
Changes in v4: - added CONFIG_ENV_OVERWRITE to defconfig to match Puma behavior and allow commands specified in our user manual, - added comment in commit log for the DTS origin (next-20221114), - Link to v3: https://lore.kernel.org/r/20221017-upstream-ringneck-v3-0-d6ae387f35ef@theob...
Changes in v3: - added Rb, - rebased on top of master, - fixed http links to use u instead of encoded µ, - updated u-boot,mmc-env-offset from 16KB to 20KB to avoid GPT corruption when saving env + reduced env size to 0x3000 to adapt to the offset change, - removed video support from defconfig as there's no display support ATM, - Link to v2: https://lore.kernel.org/r/20221017-upstream-ringneck-v2-0-0f03912ebac2@theob...
Changes in v2: - updated DTS from Linux with v2 of the Linux kernel patch series, - updated node nade for bios-disable-override-hog to match v2 of Linux kernel, - removed uapi input patch since it is not needed anymore,
--- Quentin Schulz (6): rockchip: px30: fix possibly unused grf and cru variables rockchip: px30: fix CONFIG_IRAM_BASE rockchip: px30: list possible SPL boot devices rockchip: px30: insert u-boot,spl-boot-device into U-Boot device tree arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1 rockchip: add support for PX30 Ringneck SoM on Haikou Devkit
arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 91 +++++ arch/arm/dts/px30-ringneck-haikou.dts | 232 +++++++++++++ arch/arm/dts/px30-ringneck.dtsi | 382 +++++++++++++++++++++ arch/arm/dts/px30.dtsi | 28 +- arch/arm/mach-rockchip/px30/Kconfig | 25 ++ arch/arm/mach-rockchip/px30/px30.c | 67 ++++ board/theobroma-systems/ringneck_px30/Kconfig | 18 + board/theobroma-systems/ringneck_px30/MAINTAINERS | 9 + board/theobroma-systems/ringneck_px30/Makefile | 7 + board/theobroma-systems/ringneck_px30/README | 69 ++++ .../ringneck_px30/ringneck-px30.c | 175 ++++++++++ configs/ringneck-px30_defconfig | 128 +++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/px30_common.h | 3 +- include/configs/ringneck_px30.h | 15 + 15 files changed, 1245 insertions(+), 5 deletions(-) --- base-commit: 582e3c9fb2337c2f49faa73ac86dde25f4d56901 change-id: 20221017-upstream-ringneck-57abd09a7aaa
Best regards,
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The grf and cru are only used when no UART base is provided by the user (defaults to UART2) or for UART1, UART3 and UART5 to be used for the debug UART. Therefore, let's surround those variable definitions with the proper checks.
This wasn't an issue before support for UART0 was added, because all cases were using cru and grf. UART0 only uses pmucru so there's a need to not define those variables anymore.
Fixes: d0af506625ff ("rockchip: px30: support debug uart on UART0") Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- arch/arm/mach-rockchip/px30/px30.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6af0f..35a36700df 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -297,8 +297,18 @@ void board_debug_uart_init(void) CONFIG_DEBUG_UART_BASE == 0xff030000) static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE; #endif +#if !defined(CONFIG_DEBUG_UART_BASE) || \ + (CONFIG_DEBUG_UART_BASE != 0xff158000 && \ + CONFIG_DEBUG_UART_BASE != 0xff168000 && \ + CONFIG_DEBUG_UART_BASE != 0xff178000 && \ + CONFIG_DEBUG_UART_BASE != 0xff030000) || \ + (defined(CONFIG_DEBUG_UART_BASE) && \ + (CONFIG_DEBUG_UART_BASE == 0xff158000 || \ + CONFIG_DEBUG_UART_BASE == 0xff168000 || \ + CONFIG_DEBUG_UART_BASE == 0xff178000)) static struct px30_grf * const grf = (void *)GRF_BASE; static struct px30_cru * const cru = (void *)CRU_BASE; +#endif #if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000 static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE; #endif
Hi Quentin,
Seems like this still not fix all the case for board ringneck-px30.
I got below error after I fix the CFG_IRAM_BASE:
aarch64: + ringneck-px30 +/usr/lib/python3/dist-packages/setuptools/dist.py:473: UserWarning: Normalizing '2023.01' to '2023.1' + warnings.warn( +In file included from drivers/serial/ns16550.c:13:0: +include/ns16550.h:43:2: error: #error "Please define NS16550 registers size." + #error "Please define NS16550 registers size." + ^~~~~
Thanks,
- Kever
On 2023/1/3 21:26, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The grf and cru are only used when no UART base is provided by the user (defaults to UART2) or for UART1, UART3 and UART5 to be used for the debug UART. Therefore, let's surround those variable definitions with the proper checks.
This wasn't an issue before support for UART0 was added, because all cases were using cru and grf. UART0 only uses pmucru so there's a need to not define those variables anymore.
Fixes: d0af506625ff ("rockchip: px30: support debug uart on UART0") Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com
arch/arm/mach-rockchip/px30/px30.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6af0f..35a36700df 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -297,8 +297,18 @@ void board_debug_uart_init(void) CONFIG_DEBUG_UART_BASE == 0xff030000) static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE; #endif +#if !defined(CONFIG_DEBUG_UART_BASE) || \
- (CONFIG_DEBUG_UART_BASE != 0xff158000 && \
CONFIG_DEBUG_UART_BASE != 0xff168000 && \CONFIG_DEBUG_UART_BASE != 0xff178000 && \CONFIG_DEBUG_UART_BASE != 0xff030000) || \- (defined(CONFIG_DEBUG_UART_BASE) && \
(CONFIG_DEBUG_UART_BASE == 0xff158000 || \CONFIG_DEBUG_UART_BASE == 0xff168000 || \CONFIG_DEBUG_UART_BASE == 0xff178000))+#endif #if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000 static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE; #endif
Hi Kever,
On 1/5/23 03:15, Kever Yang wrote:
Hi Quentin,
Seems like this still not fix all the case for board ringneck-px30.
I got below error after I fix the CFG_IRAM_BASE:
aarch64: + ringneck-px30 +/usr/lib/python3/dist-packages/setuptools/dist.py:473: UserWarning: Normalizing '2023.01' to '2023.1' + warnings.warn( +In file included from drivers/serial/ns16550.c:13:0: +include/ns16550.h:43:2: error: #error "Please define NS16550 registers size."
- #error "Please define NS16550 registers size."
+ ^~~~~
Yes, there was the SYS_NS16550_MEM32 migration to Kconfig that needs to be done too.
I'm rebasing on top of next branch but the device does not boot at all because of some rework of the serial driver/subsystem, we're trying to work things out on IRC with Tom. You should have the same issue with a PX30 EVB I believe BTW.
I'll send a v6 when ready, thanks for the feedback.
Cheers, Quentin
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The IRAM on PX30 (or Int_MEM in datasheet) starts at 0xff0e0000 and not 0xff020000 as rightfully stated in the FIXME comment.
Let's fix it so that BROM_BOOTSOURCE_ID_ADDR points to the correct address for PX30.
Fixes: 46281a76bee3 ("rockchip: add core px30 headers") Cc: Quentin Schulz foss+uboot@0leil.net Reviewed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- include/configs/px30_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebd..c93bb053a5 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -10,8 +10,7 @@
#define CONFIG_SYS_NS16550_MEM32
-/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ -#define CONFIG_IRAM_BASE 0xff020000 +#define CONFIG_IRAM_BASE 0xff0e0000
#define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000
Hi Quentin,
On 2023/1/3 21:26, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The IRAM on PX30 (or Int_MEM in datasheet) starts at 0xff0e0000 and not 0xff020000 as rightfully stated in the FIXME comment.
Let's fix it so that BROM_BOOTSOURCE_ID_ADDR points to the correct address for PX30.
Fixes: 46281a76bee3 ("rockchip: add core px30 headers") Cc: Quentin Schulz foss+uboot@0leil.net Reviewed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com
include/configs/px30_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebd..c93bb053a5 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -10,8 +10,7 @@
#define CONFIG_SYS_NS16550_MEM32
-/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ -#define CONFIG_IRAM_BASE 0xff020000 +#define CONFIG_IRAM_BASE 0xff0e0000
This should be CFG_IRAM_BASE.
Please check mainline/next.
Thanks,
- Kever
#define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000
From: Quentin Schulz quentin.schulz@theobroma-systems.com
BOOTROM sets a bit in a CPU register so that the software can know from where the first stage bootloader was booted. One use case for this is to specify the default loading medium for U-Boot proper to match the one used by the BOOTROM to load the SPL (same-as-spl in u-boot,spl-boot-order).
Let's create the mapping between BOOTROM value and Device Tree node names for MMC devices.
Cc: Quentin Schulz foss+uboot@0leil.net Reviewed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- arch/arm/mach-rockchip/px30/px30.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 35a36700df..a90f18720a 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -8,6 +8,7 @@ #include <init.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/uart.h> @@ -15,6 +16,11 @@ #include <asm/arch-rockchip/cru_px30.h> #include <dt-bindings/clock/px30-cru.h>
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff370000", +}; + static struct mm_region px30_mem_map[] = { { .virt = 0x0UL,
From: Quentin Schulz quentin.schulz@theobroma-systems.com
It is possible to boot U-Boot proper from a different storage medium than the one used by the BOOTROM to load the SPL. This information is stored in the u-boot,spl-boot-device Device Tree property and is accessible from U-Boot proper so that it has knowledge at runtime where it was loaded from.
Let's add support for this feature for px30.
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- arch/arm/mach-rockchip/px30/px30.c | 51 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index a90f18720a..68233e3bb5 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -5,7 +5,9 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <fdt_support.h> #include <init.h> +#include <spl.h> #include <asm/armv8/mmu.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -437,3 +439,52 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const char *spl_decode_boot_device(u32 boot_device) +{ + int i; + static const struct { + u32 boot_device; + const char *ofpath; + } spl_boot_devices_tbl[] = { + { BOOT_DEVICE_MMC2, "/mmc@ff370000" }, + { BOOT_DEVICE_MMC1, "/mmc@ff390000" }, + }; + + for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) + if (spl_boot_devices_tbl[i].boot_device == boot_device) + return spl_boot_devices_tbl[i].ofpath; + + return NULL; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image->fdt_addr; + const char *boot_ofpath; + int chosen; + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT, if a FDT has been + * loaded at the same time. + */ + if (!blob) + return; + + boot_ofpath = spl_decode_boot_device(spl_image->boot_device); + if (!boot_ofpath) { + pr_err("%s: could not map boot_device to ofpath\n", __func__); + return; + } + + chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); + if (chosen < 0) { + pr_err("%s: could not find/create '/chosen'\n", __func__); + return; + } + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); +} +#endif
On 2023/1/3 21:26, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@theobroma-systems.com
It is possible to boot U-Boot proper from a different storage medium than the one used by the BOOTROM to load the SPL. This information is stored in the u-boot,spl-boot-device Device Tree property and is accessible from U-Boot proper so that it has knowledge at runtime where it was loaded from.
Let's add support for this feature for px30.
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/px30/px30.c | 51 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index a90f18720a..68233e3bb5 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -5,7 +5,9 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <fdt_support.h> #include <init.h> +#include <spl.h> #include <asm/armv8/mmu.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -437,3 +439,52 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const char *spl_decode_boot_device(u32 boot_device) +{
- int i;
- static const struct {
u32 boot_device;const char *ofpath;- } spl_boot_devices_tbl[] = {
{ BOOT_DEVICE_MMC2, "/mmc@ff370000" },{ BOOT_DEVICE_MMC1, "/mmc@ff390000" },- };
- for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
if (spl_boot_devices_tbl[i].boot_device == boot_device)return spl_boot_devices_tbl[i].ofpath;- return NULL;
+}
+void spl_perform_fixups(struct spl_image_info *spl_image) +{
- void *blob = spl_image->fdt_addr;
- const char *boot_ofpath;
- int chosen;
- /*
* Inject the ofpath of the device the full U-Boot (or Linux in* Falcon-mode) was booted from into the FDT, if a FDT has been* loaded at the same time.*/- if (!blob)
return;- boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
- if (!boot_ofpath) {
pr_err("%s: could not map boot_device to ofpath\n", __func__);return;- }
- chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
- if (chosen < 0) {
pr_err("%s: could not find/create '/chosen'\n", __func__);return;- }
- fdt_setprop_string(blob, chosen,
"u-boot,spl-boot-device", boot_ofpath);+} +#endif
From: Quentin Schulz quentin.schulz@theobroma-systems.com
Sync the px30 dtsi from Linux kernel v6.1.
Cc: Quentin Schulz foss+uboot@0leil.net Reviewed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- arch/arm/dts/px30.dtsi | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index 00f50b05d5..bfa3580429 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -365,6 +365,28 @@ status = "disabled"; };
+ i2s0_8ch: i2s@ff060000 { + compatible = "rockchip,px30-i2s-tdm"; + reg = <0x0 0xff060000 0x0 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + rockchip,grf = <&grf>; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 + &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 + &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 + &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s1_2ch: i2s@ff070000 { compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff070000 0x0 0x1000>; @@ -528,7 +550,7 @@ i2c0: i2c@ff180000 { compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; @@ -711,7 +733,7 @@ clock-names = "pclk", "timer"; };
- dmac: dmac@ff240000 { + dmac: dma-controller@ff240000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff240000 0x0 0x4000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -1072,7 +1094,7 @@ };
dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; + compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_MIPI_DSI>;
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip PX30 in a micro Qseven-compatible form-factor.
PX30-µQ7 features: * CPU: quad-core Cortex-A35 * DRAM: 2GB dual-channel * eMMC: onboard eMMC * SD/MMC * TI DP83825I 10/100Mbps PHY * USB: * USB2.0 dual role port * 3x USB2.0 host via onboard USB2.0 hub * Display: MIPI-DSI * Camera: MIPI-CSI * onboard 2.4GHz WiFi + Bluetooth module * Companion Controller: on-board additional microcontroller (STM32 Cortex-M0 or ATtiny): * RTC * fan controller * CAN (only STM32)
The non-U-Boot DTS files are imported from Linux v6.2-rc2.
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 91 +++++ arch/arm/dts/px30-ringneck-haikou.dts | 232 +++++++++++++ arch/arm/dts/px30-ringneck.dtsi | 382 +++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 25 ++ board/theobroma-systems/ringneck_px30/Kconfig | 18 + board/theobroma-systems/ringneck_px30/MAINTAINERS | 9 + board/theobroma-systems/ringneck_px30/Makefile | 7 + board/theobroma-systems/ringneck_px30/README | 69 ++++ .../ringneck_px30/ringneck-px30.c | 175 ++++++++++ configs/ringneck-px30_defconfig | 128 +++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/ringneck_px30.h | 15 + 12 files changed, 1152 insertions(+)
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi new file mode 100644 index 0000000000..e8a34c7c1e --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "px30-u-boot.dtsi" + +/ { + config { + u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */ + u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ + u-boot,boot-led = "module_led"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; + }; +}; + +&binman { + simple-bin { + blob { + offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; + }; + }; +}; + +&emmc_clk { + u-boot,dm-pre-reloc; +}; + +&emmc_cmd { + u-boot,dm-pre-reloc; +}; + +&emmc_bus8 { + u-boot,dm-pre-reloc; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; + + /* + * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module + * eMMC powered-down initially (in fact it keeps the reset signal + * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after + * the SPL has been booted from SD Card. + */ + bios-disable-override-hog { + u-boot,dm-pre-reloc; + }; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_8ma { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_up_8ma { + u-boot,dm-pre-reloc; +}; + +&sdmmc_bus4 { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_cmd { + u-boot,dm-pre-reloc; +}; + +&sdmmc_det { + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts new file mode 100644 index 0000000000..08a3ad3e7a --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30-ringneck.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit"; + compatible = "tsd,px30-ringneck-haikou", "rockchip,px30"; + + aliases { + mmc2 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&haikou_keys_pin>; + pinctrl-names = "default"; + + button-batlow-n { + label = "BATLOW#"; + linux,code = <KEY_BATTERY>; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label = "SLP_BTN#"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label = "WAKE#"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label = "LID_BTN#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; + + sd_card_led: led-1 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + function = LED_FUNCTION_SD; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + i2s0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + clocks = <&sgtl5000_clk>; + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + bitclock-master; + frame-master; + sound-dai = <&i2s0_8ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdda_codec: vdda-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdda_codec"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_baseboard>; + }; + + vddd_codec: vddd-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vddd_codec"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vdda_codec>; + VDDIO-supply = <&vcc3v3_baseboard>; + VDDD-supply = <&vddd_codec>; + }; +}; + +&i2c3 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&gmac { + status = "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins = + /* WAKE# */ + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5_xfer>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi new file mode 100644 index 0000000000..1239775583 --- /dev/null +++ b/arch/arm/dts/px30-ringneck.dtsi @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdio; + rtc0 = &rtc_twi; + rtc1 = &rk809; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + status = "okay"; + + module_led: led-0 { + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + vcc5v0_sys: vccsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_emmc>; + + status = "okay"; +}; + +/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ +&gmac { + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + phy-supply = <&vcc_3v3>; + clock_in_out = "output"; +}; + +&gpio2 { + /* + * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module + * eMMC powered-down initially (in fact it keeps the reset signal + * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after + * the SPL has been booted from SD Card. + */ + bios-disable-override-hog { + gpios = <RK_PB5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bios_disable_override"; + gpio-hog; + }; + + /* + * The BIOS_DISABLE hog is a feedback pin for the actual status of the + * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually + * represents the state of a switch on the baseboard. + */ + bios-disable-n-hog { + gpios = <RK_PC2 GPIO_ACTIVE_LOW>; + line-name = "bios_disable"; + input; + gpio-hog; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_int>; + pinctrl-names = "default"; + #clock-cells = <0>; + clock-output-names = "xin32k"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3>; + vcc6-supply = <&vcc_3v3>; + vcc7-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name = "vcc_3v0_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_lcd"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name = "vcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + /* SE05x is limited to Fast Mode */ + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + rockchip,trcm-sync-tx-only; + + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_emmc>; + vccio-oscgpi-supply = <&vcc_3v3>; + + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +/* Mule UCAN */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 28639c0041..41893920cb 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -35,6 +35,30 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+config TARGET_RINGNECK_PX30 + bool "Theobroma Systems PX30-µQ7 (Ringneck)" + help + The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, + MXM-230 connector) system-on-module from Theobroma Systems[1], + featuring the Rockchip PX30. + + It provides the following feature set: + * up to 4GB DDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card (on a baseboard) via edge connector + * Fast Ethernet with on-module TI DP83825I PHY + * MIPI-DSI/LVDS + * MIPI-CSI + * USB + - 1x USB 2.0 dual-role + - 3x USB 2.0 host + * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + - USB<->CAN bridge controller (STM32 only) + * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi + * on-module NXP SE05x Secure Element + config ROCKCHIP_BOOT_MODE_REG default 0xff010200
@@ -71,5 +95,6 @@ config DEBUG_UART_CHANNEL source "board/engicam/px30_core/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" +source "board/theobroma-systems/ringneck_px30/Kconfig"
endif diff --git a/board/theobroma-systems/ringneck_px30/Kconfig b/board/theobroma-systems/ringneck_px30/Kconfig new file mode 100644 index 0000000000..24d94807db --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/Kconfig @@ -0,0 +1,18 @@ +if TARGET_RINGNECK_PX30 + +config SYS_BOARD + default "ringneck_px30" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "ringneck_px30" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +config ENV_SIZE + default 0x3000 + +endif diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS new file mode 100644 index 0000000000..d764e26066 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -0,0 +1,9 @@ +RINGNECK-PX30 +M: Quentin Schulz quentin.schulz@theobroma-systems.com +M: Klaus Goger klaus.goger@theobroma-systems.com +S: Maintained +F: board/theobroma-systems/ringneck_px30 +F: include/configs/ringneck_px30.h +F: arch/arm/dts/px30-ringneck* +F: configs/ringneck-px30_defconfig +W: https://www.theobroma-systems.com/px30-uq7#tech-spec diff --git a/board/theobroma-systems/ringneck_px30/Makefile b/board/theobroma-systems/ringneck_px30/Makefile new file mode 100644 index 0000000000..31ada1a694 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ringneck-px30.o diff --git a/board/theobroma-systems/ringneck_px30/README b/board/theobroma-systems/ringneck_px30/README new file mode 100644 index 0000000000..e756b3a8ff --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/README @@ -0,0 +1,69 @@ +Introduction +============ + +The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 +connector) system-on-module from Theobroma Systems[1], featuring the +Rockchip PX30. + +It provides the following feature set: + * up to 4GB DDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card (on a baseboard) via edge connector + * Fast Ethernet with on-module TI DP83825I PHY + * MIPI-DSI/LVDS + * MIPI-CSI + * USB + - 1x USB 2.0 dual-role + - 3x USB 2.0 host + * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + - USB<->CAN bridge controller (STM32 only) + * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi + * on-module NXP SE05x Secure Element + +Here is the step-by-step to boot to U-Boot on px30. + +Get the Source and build ATF binary +=================================== + + > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + +Compile the ATF +=============== + + > cd trusted-firmware-a + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31 + > cp build/px30/release/bl31/bl31.elf ../u-boot/bl31.elf + +Compile the U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all + +Flash the image +=============== + +Copy u-boot-rockchip.bin to offset 32k for SD/eMMC. + +SD-Card +------- + + > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64 + +eMMC +---- + +rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with +help of the Rockchip loader binary. + + > git clone https://github.com/rockchip-linux/rkdeveloptool + > cd rkdeveloptool + > autoreconf -i && ./configure && make + > git clone https://github.com/rockchip-linux/rkbin.git + > cd rkbin + > ./tools/boot_merger RKBOOT/PX30MINIALL.ini + > cd .. + > ./rkdeveloptool db rkbin/px30_loader_v1.16.131.bin + > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c new file mode 100644 index 0000000000..47d1a40ef7 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <env_internal.h> +#include <init.h> +#include <log.h> +#include <misc.h> +#include <spl.h> +#include <syscon.h> +#include <u-boot/crc.h> +#include <usb.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/io.h> +#include <asm/setup.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/misc.h> +#include <power/regulator.h> +#include <u-boot/sha256.h> + +/* + * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. + * + * If bootsource is uSD-card we can assume that we want to use the + * SD-Card instead of the eMMC as first boot_target for distroboot. + * We only want to swap the defaults and not any custom environment a + * user has set. We exit early if a changed boot_targets environment + * is detected. + */ +static int setup_boottargets(void) +{ + const char *boot_device = + ofnode_read_chosen_string("u-boot,spl-boot-device"); + char *env_default, *env; + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return -1; + } + debug("%s: booted from %s\n", __func__, boot_device); + + env_default = env_get_default("boot_targets"); + env = env_get("boot_targets"); + if (!env) { + debug("%s: boot_targets does not exist\n", __func__); + return -1; + } + debug("%s: boot_targets current: %s - default: %s\n", + __func__, env, env_default); + + if (strcmp(env_default, env) != 0) { + debug("%s: boot_targets not default, don't change it\n", + __func__); + return 0; + } + + /* + * Make the default boot medium between SD Card and eMMC, the one that + * was used to load U-Boot proper. + */ + bool sd_booted = !strcmp(boot_device, "/mmc@ff370000"); + char *mmc0, *mmc1; + + debug("%s: booted from %s\n", __func__, + sd_booted ? "SD-Card" : "eMMC"); + mmc0 = strstr(env, "mmc0"); + mmc1 = strstr(env, "mmc1"); + + if (!mmc0 || !mmc1) { + debug("%s: only one mmc boot_target found\n", __func__); + return -1; + } + + /* + * If mmc0 comes first in the boot order and U-Boot proper was + * loaded from mmc1, swap mmc0 and mmc1 in the list. + * If mmc1 comes first in the boot order and U-Boot proper was + * loaded from mmc0, swap mmc0 and mmc1 in the list. + */ + if ((mmc0 < mmc1 && sd_booted) || + (mmc0 > mmc1 && !sd_booted)) { + mmc0[3] = '1'; + mmc1[3] = '0'; + debug("%s: set boot_targets to: %s\n", __func__, env); + env_set("boot_targets", env); + } + + return 0; +} + +int mmc_get_env_dev(void) +{ + const char *boot_device = + ofnode_read_chosen_string("u-boot,spl-boot-device"); + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return CONFIG_SYS_MMC_ENV_DEV; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + if (!strcmp(boot_device, "/mmc@ff370000")) + return 1; + + if (!strcmp(boot_device, "/mmc@ff390000")) + return 0; + + return CONFIG_SYS_MMC_ENV_DEV; +} + +#if !IS_ENABLED(CONFIG_ENV_IS_NOWHERE) +#error Please enable CONFIG_ENV_IS_NOWHERE +#endif + +enum env_location arch_env_get_location(enum env_operation op, int prio) +{ + const char *boot_device = + ofnode_read_chosen_string("u-boot,spl-boot-device"); + + if (prio > 0) + return ENVL_UNKNOWN; + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return ENVL_NOWHERE; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + (!strcmp(boot_device, "/mmc@ff370000") || + !strcmp(boot_device, "/mmc@ff390000"))) + return ENVL_MMC; + + printf("%s: No environment available: booted from %s but U-Boot " + "config does not allow loading environment from it.", + __func__, boot_device); + + return ENVL_NOWHERE; +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + if (ret) + return ret; + + setup_boottargets(); + + return 0; +} diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig new file mode 100644 index 0000000000..7ad281a3fe --- /dev/null +++ b/configs/ringneck-px30_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_RINGNECK_PX30=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF030000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_TPL_MAX_SIZE=0x20000 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_SLEEP is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_RAM_PX30_DDR4=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4ca7b00b1f..92a5c27306 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -27,6 +27,7 @@ List of mainline supported Rockchip boards: - Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30) - Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30) - Firefly Core-PX30-JD4 (firefly-px30) + - Theobroma Systems PX30-µQ7 SoM - Ringneck (ringneck-px30) * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) diff --git a/include/configs/ringneck_px30.h b/include/configs/ringneck_px30.h new file mode 100644 index 0000000000..c63c935e9a --- /dev/null +++ b/include/configs/ringneck_px30.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __RINGNECK_PX30_H +#define __RINGNECK_PX30_H + +#include <configs/px30_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif
On 2023/1/3 21:26, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@theobroma-systems.com
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip PX30 in a micro Qseven-compatible form-factor.
PX30-µQ7 features: * CPU: quad-core Cortex-A35 * DRAM: 2GB dual-channel * eMMC: onboard eMMC * SD/MMC * TI DP83825I 10/100Mbps PHY * USB: * USB2.0 dual role port * 3x USB2.0 host via onboard USB2.0 hub * Display: MIPI-DSI * Camera: MIPI-CSI * onboard 2.4GHz WiFi + Bluetooth module * Companion Controller: on-board additional microcontroller (STM32 Cortex-M0 or ATtiny): * RTC * fan controller * CAN (only STM32)
The non-U-Boot DTS files are imported from Linux v6.2-rc2.
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 91 +++++ arch/arm/dts/px30-ringneck-haikou.dts | 232 +++++++++++++ arch/arm/dts/px30-ringneck.dtsi | 382 +++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 25 ++ board/theobroma-systems/ringneck_px30/Kconfig | 18 + board/theobroma-systems/ringneck_px30/MAINTAINERS | 9 + board/theobroma-systems/ringneck_px30/Makefile | 7 + board/theobroma-systems/ringneck_px30/README | 69 ++++ .../ringneck_px30/ringneck-px30.c | 175 ++++++++++ configs/ringneck-px30_defconfig | 128 +++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/ringneck_px30.h | 15 + 12 files changed, 1152 insertions(+)
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi new file mode 100644 index 0000000000..e8a34c7c1e --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "px30-u-boot.dtsi"
+/ {
- config {
u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */u-boot,boot-led = "module_led";- };
- chosen {
stdout-path = "serial0:115200n8";u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;- };
+};
+&binman {
- simple-bin {
blob {offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;};- };
+};
+&emmc_clk {
- u-boot,dm-pre-reloc;
+};
+&emmc_cmd {
- u-boot,dm-pre-reloc;
+};
+&emmc_bus8 {
- u-boot,dm-pre-reloc;
+};
+&gpio0 {
- u-boot,dm-pre-reloc;
+};
+&gpio1 {
- u-boot,dm-pre-reloc;
+};
+&gpio2 {
- u-boot,dm-pre-reloc;
- /*
* The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module* eMMC powered-down initially (in fact it keeps the reset signal* asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after* the SPL has been booted from SD Card.*/- bios-disable-override-hog {
u-boot,dm-pre-reloc;- };
+};
+&pinctrl {
- u-boot,dm-pre-reloc;
+};
+&pcfg_pull_none_8ma {
- u-boot,dm-pre-reloc;
+};
+&pcfg_pull_up_8ma {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_bus4 {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_cmd {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_det {
- u-boot,dm-pre-reloc;
+};
+&uart0 {
- clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+}; diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts new file mode 100644 index 0000000000..08a3ad3e7a --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
+/dts-v1/; +#include "px30-ringneck.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h>
+/ {
- model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
- compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
- aliases {
mmc2 = &sdmmc;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- gpio-keys {
compatible = "gpio-keys";pinctrl-0 = <&haikou_keys_pin>;pinctrl-names = "default";button-batlow-n {label = "BATLOW#";linux,code = <KEY_BATTERY>;gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;};button-slp-btn-n {label = "SLP_BTN#";linux,code = <KEY_SLEEP>;gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;};button-wake-n {label = "WAKE#";linux,code = <KEY_WAKEUP>;gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;wakeup-source;};switch-lid-btn-n {label = "LID_BTN#";linux,code = <SW_LID>;linux,input-type = <EV_SW>;gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;};- };
- leds {
pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;sd_card_led: led-1 {gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc2";function = LED_FUNCTION_SD;color = <LED_COLOR_ID_BLUE>;};- };
- i2s0-sound {
compatible = "simple-audio-card";simple-audio-card,format = "i2s";simple-audio-card,name = "Haikou,I2S-codec";simple-audio-card,mclk-fs = <512>;simple-audio-card,codec {clocks = <&sgtl5000_clk>;sound-dai = <&sgtl5000>;};simple-audio-card,cpu {bitclock-master;frame-master;sound-dai = <&i2s0_8ch>;};- };
- sgtl5000_clk: sgtl5000-oscillator {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <24576000>;- };
- dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";regulator-name = "dc_12v";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- vcc3v3_baseboard: vcc3v3-baseboard-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_baseboard";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&dc_12v>;- };
- vcc5v0_baseboard: vcc5v0-baseboard-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_baseboard";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&dc_12v>;- };
- vdda_codec: vdda-codec-regulator {
compatible = "regulator-fixed";regulator-name = "vdda_codec";regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc5v0_baseboard>;- };
- vddd_codec: vddd-codec-regulator {
compatible = "regulator-fixed";regulator-name = "vddd_codec";regulator-boot-on;regulator-min-microvolt = <1600000>;regulator-max-microvolt = <1600000>;vin-supply = <&vcc5v0_baseboard>;- };
+};
+&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
- sgtl5000: codec@a {
compatible = "fsl,sgtl5000";reg = <0x0a>;clocks = <&sgtl5000_clk>;#sound-dai-cells = <0>;VDDA-supply = <&vdda_codec>;VDDIO-supply = <&vcc3v3_baseboard>;VDDD-supply = <&vddd_codec>;- };
+};
+&i2c3 {
- eeprom@50 {
reg = <0x50>;compatible = "atmel,24c01";pagesize = <8>;size = <128>;vcc-supply = <&vcc3v3_baseboard>;- };
+};
+&i2s0_8ch {
- status = "okay";
+};
+&gmac {
- status = "okay";
+};
+&pinctrl {
- haikou {
haikou_keys_pin: haikou-keys-pin {rockchip,pins =/* WAKE# */<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,/* SLP_BTN# */<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,/* LID_BTN */<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,/* BATLOW# */<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,/* BIOS_DISABLE# */<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- leds {
sd_card_led_pin: sd-card-led-pin {rockchip,pins =<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pwm0 {
- status = "okay";
+};
+&sdmmc {
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
- disable-wp;
- vmmc-supply = <&vcc3v3_baseboard>;
- status = "okay";
+};
+&spi1 {
- status = "okay";
+};
+&u2phy_otg {
- status = "okay";
+};
+&uart0 {
- status = "okay";
+};
+&uart5 {
- pinctrl-0 = <&uart5_xfer>;
- status = "okay";
+};
+&usb20_otg {
- status = "okay";
+}; diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi new file mode 100644 index 0000000000..1239775583 --- /dev/null +++ b/arch/arm/dts/px30-ringneck.dtsi @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
+/dts-v1/; +#include "px30.dtsi" +#include <dt-bindings/leds/common.h>
+/ {
- aliases {
mmc0 = &emmc;mmc1 = &sdio;rtc0 = &rtc_twi;rtc1 = &rk809;- };
- emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";pinctrl-0 = <&emmc_reset>;pinctrl-names = "default";reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;- };
- leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&module_led_pin>;status = "okay";module_led: led-0 {gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;function = LED_FUNCTION_HEARTBEAT;linux,default-trigger = "heartbeat";color = <LED_COLOR_ID_AMBER>;};- };
- vcc5v0_sys: vccsys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
+};
+&cpu0 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu1 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu2 {
- cpu-supply = <&vdd_arm>;
+};
+&cpu3 {
- cpu-supply = <&vdd_arm>;
+};
+&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- supports-emmc;
- mmc-pwrseq = <&emmc_pwrseq>;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_emmc>;
- status = "okay";
+};
+/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ +&gmac {
- snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- phy-supply = <&vcc_3v3>;
- clock_in_out = "output";
+};
+&gpio2 {
- /*
* The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module* eMMC powered-down initially (in fact it keeps the reset signal* asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after* the SPL has been booted from SD Card.*/- bios-disable-override-hog {
gpios = <RK_PB5 GPIO_ACTIVE_LOW>;output-high;line-name = "bios_disable_override";gpio-hog;- };
- /*
* The BIOS_DISABLE hog is a feedback pin for the actual status of the* signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually* represents the state of a switch on the baseboard.*/- bios-disable-n-hog {
gpios = <RK_PC2 GPIO_ACTIVE_LOW>;line-name = "bios_disable";input;gpio-hog;- };
+};
+&gpu {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
- rk809: pmic@20 {
compatible = "rockchip,rk809";reg = <0x20>;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-0 = <&pmic_int>;pinctrl-names = "default";#clock-cells = <0>;clock-output-names = "xin32k";rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc_3v3>;vcc6-supply = <&vcc_3v3>;vcc7-supply = <&vcc_3v3>;vcc9-supply = <&vcc5v0_sys>;regulators {vdd_log: DCDC_REG1 {regulator-name = "vdd_log";regulator-min-microvolt = <950000>;regulator-max-microvolt = <1350000>;regulator-ramp-delay = <6001>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <950000>;};};vdd_arm: DCDC_REG2 {regulator-name = "vdd_arm";regulator-min-microvolt = <950000>;regulator-max-microvolt = <1350000>;regulator-ramp-delay = <6001>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <950000>;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {regulator-name = "vcc_3v0_1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3000000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3000000>;};};vcc_3v3: DCDC_REG5 {regulator-name = "vcc_3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_1v8: LDO_REG2 {regulator-name = "vcc_1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc_1v0: LDO_REG3 {regulator-name = "vcc_1v0";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vccio_sd: LDO_REG5 {regulator-name = "vccio_sd";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_lcd: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-name = "vcc_lcd";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc_1v8_lcd: LDO_REG8 {regulator-name = "vcc_1v8_lcd";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcca_1v8: LDO_REG9 {regulator-name = "vcca_1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};};- };
+};
+&i2c1 {
- status = "okay";
- /* SE05x is limited to Fast Mode */
- clock-frequency = <400000>;
- fan: fan@18 {
compatible = "ti,amc6821";reg = <0x18>;#cooling-cells = <2>;- };
- rtc_twi: rtc@6f {
compatible = "isil,isl1208";reg = <0x6f>;- };
+};
+&i2c3 {
- status = "okay";
+};
+&i2s0_8ch {
- rockchip,trcm-sync-tx-only;
- pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
&i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;+};
+&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_emmc>;
- vccio-oscgpi-supply = <&vcc_3v3>;
- status = "okay";
+};
+&pinctrl {
- emmc {
emmc_reset: emmc-reset {rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- leds {
module_led_pin: module-led-pin {rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
pmic_int: pmic-int {rockchip,pins =<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;};- };
+};
+&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
+};
+&sdmmc {
- vqmmc-supply = <&vccio_sd>;
+};
+&tsadc {
- status = "okay";
+};
+&u2phy {
- status = "okay";
+};
+&u2phy_host {
- status = "okay";
+};
+/* Mule UCAN */ +&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&wdt {
- status = "okay";
+}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 28639c0041..41893920cb 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -35,6 +35,30 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+config TARGET_RINGNECK_PX30
- bool "Theobroma Systems PX30-µQ7 (Ringneck)"
- help
The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm,MXM-230 connector) system-on-module from Theobroma Systems[1],featuring the Rockchip PX30.It provides the following feature set:* up to 4GB DDR4* up to 128GB on-module eMMC (with 8-bit 1.8V interface)* SD card (on a baseboard) via edge connector* Fast Ethernet with on-module TI DP83825I PHY* MIPI-DSI/LVDS* MIPI-CSI* USB- 1x USB 2.0 dual-role- 3x USB 2.0 host* on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:- low-power RTC functionality (ISL1208 emulation)- fan controller (AMC6821 emulation)- USB<->CAN bridge controller (STM32 only)* on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi* on-module NXP SE05x Secure Element- config ROCKCHIP_BOOT_MODE_REG default 0xff010200
@@ -71,5 +95,6 @@ config DEBUG_UART_CHANNEL source "board/engicam/px30_core/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" +source "board/theobroma-systems/ringneck_px30/Kconfig"
endif diff --git a/board/theobroma-systems/ringneck_px30/Kconfig b/board/theobroma-systems/ringneck_px30/Kconfig new file mode 100644 index 0000000000..24d94807db --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/Kconfig @@ -0,0 +1,18 @@ +if TARGET_RINGNECK_PX30
+config SYS_BOARD
- default "ringneck_px30"
+config SYS_VENDOR
- default "theobroma-systems"
+config SYS_CONFIG_NAME
- default "ringneck_px30"
+config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+config ENV_SIZE
- default 0x3000
+endif diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS new file mode 100644 index 0000000000..d764e26066 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -0,0 +1,9 @@ +RINGNECK-PX30 +M: Quentin Schulz quentin.schulz@theobroma-systems.com +M: Klaus Goger klaus.goger@theobroma-systems.com +S: Maintained +F: board/theobroma-systems/ringneck_px30 +F: include/configs/ringneck_px30.h +F: arch/arm/dts/px30-ringneck* +F: configs/ringneck-px30_defconfig +W: https://www.theobroma-systems.com/px30-uq7#tech-spec diff --git a/board/theobroma-systems/ringneck_px30/Makefile b/board/theobroma-systems/ringneck_px30/Makefile new file mode 100644 index 0000000000..31ada1a694 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += ringneck-px30.o diff --git a/board/theobroma-systems/ringneck_px30/README b/board/theobroma-systems/ringneck_px30/README new file mode 100644 index 0000000000..e756b3a8ff --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/README @@ -0,0 +1,69 @@ +Introduction +============
+The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230 +connector) system-on-module from Theobroma Systems[1], featuring the +Rockchip PX30.
+It provides the following feature set:
- up to 4GB DDR4
- up to 128GB on-module eMMC (with 8-bit 1.8V interface)
- SD card (on a baseboard) via edge connector
- Fast Ethernet with on-module TI DP83825I PHY
- MIPI-DSI/LVDS
- MIPI-CSI
- USB
- 1x USB 2.0 dual-role
- 3x USB 2.0 host
- on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
- USB<->CAN bridge controller (STM32 only)
- on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
- on-module NXP SE05x Secure Element
+Here is the step-by-step to boot to U-Boot on px30.
+Get the Source and build ATF binary +===================================
+Compile the ATF +===============
+Compile the U-Boot +==================
+Flash the image +===============
+Copy u-boot-rockchip.bin to offset 32k for SD/eMMC.
+SD-Card +-------
+eMMC +----
+rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with +help of the Rockchip loader binary.
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c new file mode 100644 index 0000000000..47d1a40ef7 --- /dev/null +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH
- */
+#include <common.h> +#include <dm.h> +#include <env.h> +#include <env_internal.h> +#include <init.h> +#include <log.h> +#include <misc.h> +#include <spl.h> +#include <syscon.h> +#include <u-boot/crc.h> +#include <usb.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/io.h> +#include <asm/setup.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/misc.h> +#include <power/regulator.h> +#include <u-boot/sha256.h>
+/*
- Swap mmc0 and mmc1 in boot_targets if booted from SD-Card.
- If bootsource is uSD-card we can assume that we want to use the
- SD-Card instead of the eMMC as first boot_target for distroboot.
- We only want to swap the defaults and not any custom environment a
- user has set. We exit early if a changed boot_targets environment
- is detected.
- */
+static int setup_boottargets(void) +{
- const char *boot_device =
ofnode_read_chosen_string("u-boot,spl-boot-device");- char *env_default, *env;
- if (!boot_device) {
debug("%s: /chosen/u-boot,spl-boot-device not set\n",__func__);return -1;- }
- debug("%s: booted from %s\n", __func__, boot_device);
- env_default = env_get_default("boot_targets");
- env = env_get("boot_targets");
- if (!env) {
debug("%s: boot_targets does not exist\n", __func__);return -1;- }
- debug("%s: boot_targets current: %s - default: %s\n",
__func__, env, env_default);- if (strcmp(env_default, env) != 0) {
debug("%s: boot_targets not default, don't change it\n",__func__);return 0;- }
- /*
* Make the default boot medium between SD Card and eMMC, the one that* was used to load U-Boot proper.*/- bool sd_booted = !strcmp(boot_device, "/mmc@ff370000");
- char *mmc0, *mmc1;
- debug("%s: booted from %s\n", __func__,
sd_booted ? "SD-Card" : "eMMC");- mmc0 = strstr(env, "mmc0");
- mmc1 = strstr(env, "mmc1");
- if (!mmc0 || !mmc1) {
debug("%s: only one mmc boot_target found\n", __func__);return -1;- }
- /*
* If mmc0 comes first in the boot order and U-Boot proper was* loaded from mmc1, swap mmc0 and mmc1 in the list.* If mmc1 comes first in the boot order and U-Boot proper was* loaded from mmc0, swap mmc0 and mmc1 in the list.*/- if ((mmc0 < mmc1 && sd_booted) ||
(mmc0 > mmc1 && !sd_booted)) {mmc0[3] = '1';mmc1[3] = '0';debug("%s: set boot_targets to: %s\n", __func__, env);env_set("boot_targets", env);- }
- return 0;
+}
+int mmc_get_env_dev(void) +{
- const char *boot_device =
ofnode_read_chosen_string("u-boot,spl-boot-device");- if (!boot_device) {
debug("%s: /chosen/u-boot,spl-boot-device not set\n",__func__);return CONFIG_SYS_MMC_ENV_DEV;- }
- debug("%s: booted from %s\n", __func__, boot_device);
- if (!strcmp(boot_device, "/mmc@ff370000"))
return 1;- if (!strcmp(boot_device, "/mmc@ff390000"))
return 0;- return CONFIG_SYS_MMC_ENV_DEV;
+}
+#if !IS_ENABLED(CONFIG_ENV_IS_NOWHERE) +#error Please enable CONFIG_ENV_IS_NOWHERE +#endif
+enum env_location arch_env_get_location(enum env_operation op, int prio) +{
- const char *boot_device =
ofnode_read_chosen_string("u-boot,spl-boot-device");- if (prio > 0)
return ENVL_UNKNOWN;- if (!boot_device) {
debug("%s: /chosen/u-boot,spl-boot-device not set\n",__func__);return ENVL_NOWHERE;- }
- debug("%s: booted from %s\n", __func__, boot_device);
- if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) &&
(!strcmp(boot_device, "/mmc@ff370000") ||!strcmp(boot_device, "/mmc@ff390000")))return ENVL_MMC;- printf("%s: No environment available: booted from %s but U-Boot "
"config does not allow loading environment from it.",__func__, boot_device);- return ENVL_NOWHERE;
+}
+int misc_init_r(void) +{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
return ret;- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
return ret;- ret = rockchip_setup_macaddr();
- if (ret)
return ret;- setup_boottargets();
- return 0;
+} diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig new file mode 100644 index 0000000000..7ad281a3fe --- /dev/null +++ b/configs/ringneck-px30_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_RINGNECK_PX30=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF030000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_TPL_MAX_SIZE=0x20000 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_SLEEP is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_RAM_PX30_DDR4=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4ca7b00b1f..92a5c27306 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -27,6 +27,7 @@ List of mainline supported Rockchip boards: - Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30) - Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30) - Firefly Core-PX30-JD4 (firefly-px30)
- Theobroma Systems PX30-µQ7 SoM - Ringneck (ringneck-px30)
- rk3036
- Rockchip Evb-RK3036 (evb-rk3036)
- Kylin (kylin_rk3036)
diff --git a/include/configs/ringneck_px30.h b/include/configs/ringneck_px30.h new file mode 100644 index 0000000000..c63c935e9a --- /dev/null +++ b/include/configs/ringneck_px30.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH
- */
+#ifndef __RINGNECK_PX30_H +#define __RINGNECK_PX30_H
+#include <configs/px30_common.h>
+#define ROCKCHIP_DEVICE_SETTINGS \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
+#endif
participants (3)
-
Kever Yang -
Quentin Schulz -
Quentin Schulz