[U-Boot] [PATCH] PCI: add 64-bit prefetchable memory support
From: David Feng fenghua@phytium.com.cn
PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors.
Signed-off-by: David Feng fenghua@phytium.com.cn --- drivers/pci/pci_auto.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ed92857..5ddb0b8 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -223,9 +223,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_mem = hose->pci_mem; struct pci_region *pci_prefetch = hose->pci_prefetch; struct pci_region *pci_io = hose->pci_io; - u16 cmdstat; + u16 cmdstat, prefechable_64;
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); + pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, + &prefechable_64); + prefechable_64 &= 0x1;
/* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, @@ -252,12 +255,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, /* Set up memory and I/O filter limits, assume 32-bit I/O space */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, (pci_prefetch->bus_lower & 0xfff00000) >> 16); + if (prefechable_64) +#ifdef CONFIG_SYS_PCI_64BIT + pci_hose_write_config_dword(hose, dev, + PCI_PREF_BASE_UPPER32, + pci_prefetch->bus_lower >> 32); +#else + pci_hose_write_config_dword(hose, dev, + PCI_PREF_BASE_UPPER32, + 0x0); +#endif
cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); + if (prefechable_64) { + pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); + pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); + } }
if (pci_io) { @@ -297,11 +314,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, }
if (pci_prefetch) { + u16 prefechable_64; + + pci_hose_read_config_word(hose, dev, + PCI_PREF_MEMORY_LIMIT, + &prefechable_64); + prefechable_64 &= 0x1; + /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, (pci_prefetch->bus_lower - 1) >> 16); + if (prefechable_64) +#ifdef CONFIG_SYS_PCI_64BIT + pci_hose_write_config_dword(hose, dev, + PCI_PREF_LIMIT_UPPER32, + (pci_prefetch->bus_lower - 1) >> 32); +#else + pci_hose_write_config_dword(hose, dev, + PCI_PREF_LIMIT_UPPER32, + 0x0); +#endif }
if (pci_io) {
Hi David,
On Mon, Feb 2, 2015 at 11:30 AM, fenghua@phytium.com.cn wrote:
From: David Feng fenghua@phytium.com.cn
PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors.
Signed-off-by: David Feng fenghua@phytium.com.cn
This patch looks good to me, except a minor issue below.
drivers/pci/pci_auto.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ed92857..5ddb0b8 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -223,9 +223,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_mem = hose->pci_mem; struct pci_region *pci_prefetch = hose->pci_prefetch; struct pci_region *pci_io = hose->pci_io;
u16 cmdstat;
u16 cmdstat, prefechable_64; pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,&prefechable_64);prefechable_64 &= 0x1;
Please use PCI_PREF_RANGE_TYPE_64.
/* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,@@ -252,12 +255,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, /* Set up memory and I/O filter limits, assume 32-bit I/O space */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, (pci_prefetch->bus_lower & 0xfff00000) >> 16);
if (prefechable_64)+#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev,PCI_PREF_BASE_UPPER32,pci_prefetch->bus_lower >> 32);+#else
pci_hose_write_config_dword(hose, dev,PCI_PREF_BASE_UPPER32,0x0);+#endif
cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
if (prefechable_64) {pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);} } if (pci_io) {@@ -297,11 +314,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, }
if (pci_prefetch) {
u16 prefechable_64;pci_hose_read_config_word(hose, dev,PCI_PREF_MEMORY_LIMIT,&prefechable_64);prefechable_64 &= 0x1;
Ditto.
/* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_prefetch, 0x100000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, (pci_prefetch->bus_lower - 1) >> 16);
if (prefechable_64)+#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev,PCI_PREF_LIMIT_UPPER32,(pci_prefetch->bus_lower - 1) >> 32);+#else
pci_hose_write_config_dword(hose, dev,PCI_PREF_LIMIT_UPPER32,0x0);+#endif }
if (pci_io) {--
Regards, Bin
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