Do the DRAM init according to micron MT47H64M8B6-37E documentation.

Signed-off-by: Kenneth Johansson kenneth@southpole.se

diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8629b03..606cc6b 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -158,26 +158,18 @@ long int fixed_sdram (void) im->mddrc.ddr_command = CFG_MICRON_NOP;

im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_EM3; - im->mddrc.ddr_command = CFG_MICRON_EN_DLL; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_EM2; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_EM3; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_EM; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_MR_DLL_RESET; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_MR; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_EM_OCD; + im->mddrc.ddr_command = CFG_MICRON_DDR2_LM_EM_EXIT;

/* Start MDDRC */ im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index c147424..83781c6 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -117,14 +117,22 @@ #define CFG_MDDRC_TIME_CFG1 0x54EC1168 #define CFG_MDDRC_TIME_CFG2 0x35210864

-#define CFG_MICRON_NOP 0x01380000 -#define CFG_MICRON_PCHG_ALL 0x01100400 -#define CFG_MICRON_EM2 0x01020000 -#define CFG_MICRON_EM3 0x01030000 -#define CFG_MICRON_EN_DLL 0x01010000 -#define CFG_MICRON_RFSH 0x01080000 -#define CFG_MICRON_INIT_DEV_OP 0x01000432 -#define CFG_MICRON_OCD_DEFAULT 0x01010780 +/* DRAM commands */ +#define CFG_MICRON_NOP 0x01380000 +#define CFG_MICRON_PCHG_ALL 0x01100400 +#define CFG_MICRON_RFSH 0x01080000 + +/* DDR2 specific commands */ +#define CFG_MICRON_DDR2_LM_MR_DLL_RESET 0x01000100 /* reset DLL */ +#define CFG_MICRON_DDR2_LM_MR 0x01000432 /* burst lenght 4 */ + /* CAS 3 */ + /* Write recovery 3 */ +#define CFG_MICRON_DDR2_LM_EM_OCD 0x01010780 /* OCD default */ + /* DQS# enable */ +#define CFG_MICRON_DDR2_LM_EM_EXIT 0x01010400 /* DQS# enable */ +#define CFG_MICRON_DDR2_LM_EM 0x01010000 +#define CFG_MICRON_DDR2_LM_EM2 0x01020000 +#define CFG_MICRON_DDR2_LM_EM3 0x01030000

/* DDR Priority Manager Configuration */ #define CFG_MDDRCGRP_PM_CFG1 0x000777AA