Several DIU registers were being initialized either unnecessarily or to wrong values.

1) All interrupts were enabled even though there's no interrupt handler. Interrupts were left enabled when booting Linux.

2) Don't configure a dummy area descriptor, since we don't support ADs in U-Boot.

3) Don't configure any write-back buffer registers, since we don't use that mode.

4) The default values for the THRESHOLDS, SYN_POL, and PLUT registers should be used, so don't touch those registers either.

Signed-off-by: Timur Tabi timur@freescale.com --- drivers/video/fsl_diu_fb.c | 21 ++------------------- 1 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c index 648ffa3..a98cb67 100644 --- a/drivers/video/fsl_diu_fb.c +++ b/drivers/video/fsl_diu_fb.c @@ -271,7 +271,6 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR; u8 *gamma_table_base; unsigned int i, j; - struct diu_ad *dummy_ad; struct diu_addr gamma; struct diu_addr cursor;

@@ -302,14 +301,6 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) return -1; }

- /* The AD struct for the dummy framebuffer and the FB itself */ - dummy_ad = allocate_fb(2, 4, 4, NULL); - if (!dummy_ad) { - printf("DIU: Out of memory\n"); - return -1; - } - dummy_ad->pix_fmt = 0x88883316; - /* read mode info */ info.var.xres = fsl_diu_mode_db->xres; info.var.yres = fsl_diu_mode_db->yres; @@ -376,10 +367,7 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) out_be32(&hw->gamma, gamma.paddr); out_be32(&hw->cursor, cursor.paddr); out_be32(&hw->bgnd, 0x007F7F7F); - out_be32(&hw->bgnd_wb, 0); out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres); - out_be32(&hw->wb_size, 0); - out_be32(&hw->wb_mem_addr, 0); out_be32(&hw->hsyn_para, info.var.left_margin << 22 | info.var.hsync_len << 11 | info.var.right_margin); @@ -388,18 +376,13 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) info.var.vsync_len << 11 | info.var.lower_margin);

- out_be32(&hw->syn_pol, 0); - out_be32(&hw->thresholds, 0x00037800); - out_be32(&hw->int_status, 0); - out_be32(&hw->int_mask, 0); - out_be32(&hw->plut, 0x01F5F666); /* Pixel Clock configuration */ diu_set_pixel_clock(info.var.pixclock);

/* Set the frame buffers */ out_be32(&hw->desc[0], virt_to_phys(ad)); - out_be32(&hw->desc[1], virt_to_phys(dummy_ad)); - out_be32(&hw->desc[2], virt_to_phys(dummy_ad)); + out_be32(&hw->desc[1], 0); + out_be32(&hw->desc[2], 0);

/* Enable the DIU, set display to all three planes */ out_be32(&hw->diu_mode, 1);