[U-Boot] [PATCH 01/15] clk: renesas: Fix swapped arguments in debug message

Marek Vasut

1 Jun 2018 1 Jun '18

9:45 a.m.

The mul and div arguments were reported in reverse order in the debug message, swap them to fix this.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3a95647abe..4f10fd6352 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -230,7 +230,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_FF: case CLK_TYPE_GEN3_PE: /* FIXME */ rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", + debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate;

-- 2.16.2

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Marek Vasut

1 Jun 1 Jun

9:45 a.m.

New subject: [U-Boot] [PATCH 02/15] clk: renesas: Pass clock rate around as 64bit number internally

The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/clk-rcar-gen3.c | 56 ++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 4f10fd6352..834cd5ac58 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -134,7 +134,7 @@ static int gen3_clk_disable(struct clk *clk) return renesas_clk_endisable(clk, priv->base, false); }

-static ulong gen3_clk_get_rate(struct clk *clk) +static u64 gen3_clk_get_rate64(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct cpg_mssr_info *info = priv->info; @@ -142,7 +142,8 @@ static ulong gen3_clk_get_rate(struct clk *clk) const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = priv->cpg_pll_config; - u32 value, mult, prediv, postdiv, rate = 0; + u32 value, mult, prediv, postdiv; + u64 rate = 0; int i, ret;

debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); @@ -154,8 +155,8 @@ static ulong gen3_clk_get_rate(struct clk *clk) }

if (renesas_clk_is_mod(clk)) { - rate = gen3_clk_get_rate(&parent); - debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", + rate = gen3_clk_get_rate64(&parent); + debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n", __func__, __LINE__, parent.id, rate); return rate; } @@ -168,14 +169,14 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_IN: if (core->id == info->clk_extal_id) { rate = clk_get_rate(&priv->clk_extal); - debug("%s[%i] EXTAL clk: rate=%u\n", + debug("%s[%i] EXTAL clk: rate=%llu\n", __func__, __LINE__, rate); return rate; }

if (core->id == info->clk_extalr_id) { rate = clk_get_rate(&priv->clk_extalr); - debug("%s[%i] EXTALR clk: rate=%u\n", + debug("%s[%i] EXTALR clk: rate=%llu\n", __func__, __LINE__, rate); return rate; } @@ -183,8 +184,8 @@ static ulong gen3_clk_get_rate(struct clk *clk) return -EINVAL;

case CLK_TYPE_GEN3_MAIN: - rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; - debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div; + debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n", __func__, __LINE__, core->parent, pll_config->extal_div, rate); return rate; @@ -192,14 +193,14 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_GEN3_PLL0: value = readl(priv->base + CPG_PLL0CR); mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate(&parent) * mult; - debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) * mult; + debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n", __func__, __LINE__, core->parent, mult, rate); return rate;

case CLK_TYPE_GEN3_PLL1: - rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; - debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; + debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n", __func__, __LINE__, core->parent, pll_config->pll1_mult, rate); return rate; @@ -207,14 +208,14 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_GEN3_PLL2: value = readl(priv->base + CPG_PLL2CR); mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate(&parent) * mult; - debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) * mult; + debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n", __func__, __LINE__, core->parent, mult, rate); return rate;

case CLK_TYPE_GEN3_PLL3: - rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; - debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; + debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n", __func__, __LINE__, core->parent, pll_config->pll3_mult, rate); return rate; @@ -222,15 +223,15 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_GEN3_PLL4: value = readl(priv->base + CPG_PLL4CR); mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate(&parent) * mult; - debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n", + rate = gen3_clk_get_rate64(&parent) * mult; + debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n", __func__, __LINE__, core->parent, mult, rate); return rate;

case CLK_TYPE_FF: case CLK_TYPE_GEN3_PE: /* FIXME */ - rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", + rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div; + debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate; @@ -243,9 +244,9 @@ static ulong gen3_clk_get_rate(struct clk *clk) if (cpg_sd_div_table[i].val != value) continue;

- rate = gen3_clk_get_rate(&parent) / + rate = gen3_clk_get_rate64(&parent) / cpg_sd_div_table[i].div; - debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n", + debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n", __func__, __LINE__, core->parent, cpg_sd_div_table[i].div, rate);

@@ -255,7 +256,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) return -EINVAL;

case CLK_TYPE_GEN3_RPC: - rate = gen3_clk_get_rate(&parent); + rate = gen3_clk_get_rate64(&parent);

value = readl(priv->base + core->offset);

@@ -272,7 +273,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) CPG_RPC_POSTDIV_MASK; rate /= postdiv + 1;

- debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n", + debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n", __func__, __LINE__, core->parent, prediv, postdiv, rate);

@@ -285,11 +286,16 @@ static ulong gen3_clk_get_rate(struct clk *clk) return -ENOENT; }

+static ulong gen3_clk_get_rate(struct clk *clk) +{ + return gen3_clk_get_rate64(clk); +} + static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) { /* Force correct SD-IF divider configuration if applicable */ gen3_clk_setup_sdif_div(clk); - return gen3_clk_get_rate(clk); + return gen3_clk_get_rate64(clk); }

static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 03/15] clk: renesas: Add PLL1 and PLL3 dividers

Add and use the PLL1 and PLL3 dividers.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/clk-rcar-gen3.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 834cd5ac58..f2550598a4 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -200,9 +200,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)

case CLK_TYPE_GEN3_PLL1: rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; - debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n", + rate /= pll_config->pll1_div; + debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, - core->parent, pll_config->pll1_mult, rate); + core->parent, pll_config->pll1_mult, + pll_config->pll1_div, rate); return rate;

case CLK_TYPE_GEN3_PLL2: @@ -215,9 +217,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)

case CLK_TYPE_GEN3_PLL3: rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; - debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n", + rate /= pll_config->pll3_div; + debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, - core->parent, pll_config->pll3_mult, rate); + core->parent, pll_config->pll3_mult, + pll_config->pll3_div, rate); return rate;

case CLK_TYPE_GEN3_PLL4:

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 04/15] clk: renesas: Add PE clock handling

The PE clock have two parents, add support for picking the correct one and deriving the clock from it.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/clk-rcar-gen3.c | 40 +++++++++++++++++++++++++++++++++---- drivers/clk/renesas/rcar-gen3-cpg.h | 6 ++++-- 2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index f2550598a4..99698b1f46 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -85,6 +85,28 @@ static const struct sd_div_table cpg_sd_div_table[] = { CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), };

+static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, + struct cpg_mssr_info *info, struct clk *parent) +{ + const struct cpg_core_clk *core; + int ret; + + if (!renesas_clk_is_mod(clk)) { + ret = renesas_clk_get_core(clk, info, &core); + if (ret) + return ret; + + if (core->type == CLK_TYPE_GEN3_PE) { + parent->dev = clk->dev; + parent->id = core->parent >> (priv->sscg ? 16 : 0); + parent->id &= 0xffff; + return 0; + } + } + + return renesas_clk_get_parent(clk, info, parent); +} + static int gen3_clk_setup_sdif_div(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); @@ -93,7 +115,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) struct clk parent; int ret;

- ret = renesas_clk_get_parent(clk, info, &parent); + ret = gen3_clk_get_parent(priv, clk, info, &parent); if (ret) { printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); return ret; @@ -142,13 +164,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk) const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = priv->cpg_pll_config; - u32 value, mult, prediv, postdiv; + u32 value, mult, div, prediv, postdiv; u64 rate = 0; int i, ret;

debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);

case CLK_TYPE_FF: - case CLK_TYPE_GEN3_PE: /* FIXME */ rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div; debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate;

+ case CLK_TYPE_GEN3_PE: + div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff; + rate = gen3_clk_get_rate64(&parent) / div; + debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n", + __func__, __LINE__, + (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff, + div, rate); + return rate; + case CLK_TYPE_GEN3_SD: /* FIXME */ value = readl(priv->base + core->offset); value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; @@ -351,6 +381,8 @@ int gen3_clk_probe(struct udevice *dev) if (!priv->cpg_pll_config->extal_div) return -EINVAL;

+ priv->sscg = !(cpg_mode & BIT(12)); + ret = clk_get_by_name(dev, "extal", &priv->clk_extal); if (ret < 0) return ret; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 2f410df42a..58e71f363c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -31,8 +31,9 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ _div_clean) \ - DEF_BASE(_name, _id, CLK_TYPE_FF, \ - (_parent_clean), .div = (_div_clean), 1) + DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ + (_parent_sscg) << 16 | (_parent_clean), \ + .div = (_div_sscg) << 16 | (_div_clean))

struct rcar_gen3_cpg_pll_config { u8 extal_div; @@ -49,6 +50,7 @@ struct gen3_clk_priv { struct cpg_mssr_info *info; struct clk clk_extal; struct clk clk_extalr; + bool sscg; const struct rcar_gen3_cpg_pll_config *cpg_pll_config; };

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 05/15] clk: renesas: Add R8A77990 E3 clock tables

Add clock tables for R8A77990 E3 SoC .

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/Kconfig | 7 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 303 ++++++++++++++++++++++++++ include/dt-bindings/clock/r8a77990-cpg-mssr.h | 63 ++++++ 4 files changed, 374 insertions(+) create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index b5a6bcc3af..578e6a8049 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -74,6 +74,13 @@ config CLK_R8A77970 help Enable this to support the clocks on Renesas R8A77970 SoC.

+config CLK_R8A77990 + bool "Renesas R8A77990 clock driver" + def_bool y if R8A77990 + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A77990 SoC. + config CLK_R8A77995 bool "Renesas R8A77995 clock driver" def_bool y if R8A77995 diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index a65d89f59c..22a817a919 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c new file mode 100644 index 0000000000..792d6101b8 --- /dev/null +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -0,0 +1,303 @@ +/* + * Renesas R8A77990 CPG MSSR driver + * + * Copyright (C) 2017-2018 Marek Vasut marek.vasut@gmail.com + * + * Based on the following driver from Linux kernel: + * r8a7796 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2016 Glider bvba + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> + +#include <dt-bindings/clock/r8a77990-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77990_CLK_CPEX, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL0D4, + CLK_PLL0D6, + CLK_PLL0D8, + CLK_PLL0D20, + CLK_PLL0D24, + CLK_PLL1D2, + CLK_PE, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77990_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + + DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100), + DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1), + DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1), + DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1), + DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1), + DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1), + DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), + DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + + /* Core Clock Outputs */ + DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), + DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), + DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), + DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), + DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1), + DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), + DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), + DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + + DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), + DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), + DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1), + DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), + + DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6), + DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), + DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), + DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), + + DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), + DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), + DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), +}; + +static const struct mssr_mod_clk r8a77990_mod_clks[] = { + DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C), + DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C), + DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C), + DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C), + DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C), + DEF_MOD("msiof3", 208, R8A77990_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77990_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77990_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77990_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1), + DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1), + + DEF_MOD("cmt3", 300, R8A77990_CLK_R), + DEF_MOD("cmt2", 301, R8A77990_CLK_R), + DEF_MOD("cmt1", 302, R8A77990_CLK_R), + DEF_MOD("cmt0", 303, R8A77990_CLK_R), + DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C), + DEF_MOD("sdif3", 311, R8A77990_CLK_SD3), + DEF_MOD("sdif1", 313, R8A77990_CLK_SD1), + DEF_MOD("sdif0", 314, R8A77990_CLK_SD0), + DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1), + + DEF_MOD("rwdt", 402, R8A77990_CLK_R), + DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3), + + DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), + DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), + DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), + DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), + DEF_MOD("drif4", 511, R8A77990_CLK_S3D2), + DEF_MOD("drif3", 512, R8A77990_CLK_S3D2), + DEF_MOD("drif2", 513, R8A77990_CLK_S3D2), + DEF_MOD("drif1", 514, R8A77990_CLK_S3D2), + DEF_MOD("drif0", 515, R8A77990_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C), + DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C), + DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C), + DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C), + DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C), + DEF_MOD("thermal", 522, R8A77990_CLK_CP), + DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C), + + DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2), + DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2), + DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1), + DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1), + DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2), + DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2), + DEF_MOD("vspb", 626, R8A77990_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1), + + DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), + DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), + DEF_MOD("du1", 723, R8A77990_CLK_S2D1), + DEF_MOD("du0", 724, R8A77990_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), + + DEF_MOD("vin7", 804, R8A77990_CLK_S1D2), + DEF_MOD("vin6", 805, R8A77990_CLK_S1D2), + DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), + DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), + DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), + + DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), + DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), + DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), + DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2), + DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2), + DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), + + DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +/* + * CPG Clock Data + */ + +/* + * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 + *-------------------------------------------------------------------- + * 0 48 x 1 x100/4 x100/3 x100/3 + * 1 48 x 1 x100/4 x100/3 x58/3 + */ +#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 100, 3, 100, 3, }, + { 1, 100, 3, 58, 3, }, +}; + +static const struct mstp_stop_table r8a77990_mstp_table[] = { + { 0x00200000, 0x0, 0x00200000, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, + { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, + { 0x80000184, 0x180, 0x80000184, 0 }, + { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, + { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, + { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, + { 0x000000B7, 0x0, 0x000000B7, 0 }, +}; + +static const void *r8a77990_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + +static const struct cpg_mssr_info r8a77990_cpg_mssr_info = { + .core_clk = r8a77990_core_clks, + .core_clk_size = ARRAY_SIZE(r8a77990_core_clks), + .mod_clk = r8a77990_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a77990_mod_clks), + .mstp_table = r8a77990_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table), + .reset_node = "renesas,r8a77990-rst", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = ~0, + .get_pll_config = r8a77990_get_pll_config, +}; + +static const struct udevice_id r8a77990_clk_ids[] = { + { + .compatible = "renesas,r8a77990-cpg-mssr", + .data = (ulong)&r8a77990_cpg_mssr_info + }, + { } +}; + +U_BOOT_DRIVER(clk_r8a77990) = { + .name = "clk_r8a77990", + .id = UCLASS_CLK, + .of_match = r8a77990_clk_ids, + .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), + .ops = &gen3_clk_ops, + .probe = gen3_clk_probe, + .remove = gen3_clk_remove, +}; diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h new file mode 100644 index 0000000000..c806fce449 --- /dev/null +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77990 CPG Core Clocks */ +#define R8A77990_CLK_Z2 0 +#define R8A77990_CLK_ZR 1 +#define R8A77990_CLK_ZG 2 +#define R8A77990_CLK_ZTR 3 +#define R8A77990_CLK_ZT 4 +#define R8A77990_CLK_ZX 5 +#define R8A77990_CLK_S0D1 6 +#define R8A77990_CLK_S0D3 7 +#define R8A77990_CLK_S0D6 8 +#define R8A77990_CLK_S0D12 9 +#define R8A77990_CLK_S0D24 10 +#define R8A77990_CLK_S1D1 11 +#define R8A77990_CLK_S1D2 12 +#define R8A77990_CLK_S1D4 13 +#define R8A77990_CLK_S2D1 14 +#define R8A77990_CLK_S2D2 15 +#define R8A77990_CLK_S2D4 16 +#define R8A77990_CLK_S3D1 17 +#define R8A77990_CLK_S3D2 18 +#define R8A77990_CLK_S3D4 19 +#define R8A77990_CLK_S0D6C 20 +#define R8A77990_CLK_S3D1C 21 +#define R8A77990_CLK_S3D2C 22 +#define R8A77990_CLK_S3D4C 23 +#define R8A77990_CLK_LB 24 +#define R8A77990_CLK_CL 25 +#define R8A77990_CLK_ZB3 26 +#define R8A77990_CLK_ZB3D2 27 +#define R8A77990_CLK_CR 28 +#define R8A77990_CLK_CRD2 29 +#define R8A77990_CLK_SD0H 30 +#define R8A77990_CLK_SD0 31 +#define R8A77990_CLK_SD1H 32 +#define R8A77990_CLK_SD1 33 +#define R8A77990_CLK_SD3H 34 +#define R8A77990_CLK_SD3 35 +#define R8A77990_CLK_RPC 36 +#define R8A77990_CLK_RPCD2 37 +#define R8A77990_CLK_ZA2 38 +#define R8A77990_CLK_ZA8 39 +#define R8A77990_CLK_Z2D 40 +#define R8A77990_CLK_CANFD 41 +#define R8A77990_CLK_MSO 42 +#define R8A77990_CLK_R 43 +#define R8A77990_CLK_OSC 44 +#define R8A77990_CLK_LV0 45 +#define R8A77990_CLK_LV1 46 +#define R8A77990_CLK_CSI0 47 +#define R8A77990_CLK_POST3 48 +#define R8A77990_CLK_CP 49 +#define R8A77990_CLK_CPEX 50 + +#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 06/15] pinctrl: renesas: Add PORT_GP_11 helper macro

From: Takeshi Kihara takeshi.kihara.df@renesas.com

This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC.

Signed-off-by: Takeshi Kihara takeshi.kihara.df@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/pinctrl/renesas/sh_pfc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 22b8c95009..9755826201 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -368,9 +368,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)

-#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ PORT_GP_CFG_10(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) +#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) + +#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ + PORT_GP_CFG_11(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 07/15] pinctrl: renesas: Initial R8A77990 PFC support

This patch adds initial pinctrl driver to support for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara takeshi.kihara.df@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r8a77990.c | 1732 ++++++++++++++++++++++++++++++++ drivers/pinctrl/renesas/pfc.c | 11 + drivers/pinctrl/renesas/sh_pfc.h | 1 + 5 files changed, 1756 insertions(+) create mode 100644 drivers/pinctrl/renesas/pfc-r8a77990.c

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 5e6d854065..1baab9088a 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -94,6 +94,17 @@ config PINCTRL_PFC_R8A77970 the GPIO definitions and pin control functions for each available multiplex function.

+config PINCTRL_PFC_R8A77990 + bool "Renesas RCar Gen3 R8A77990 pin control driver" + def_bool y if R8A77990 + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_PFC_R8A77995 bool "Renesas RCar Gen3 R8A77995 pin control driver" def_bool y if R8A77995 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 29b9912f83..62bc40b8c1 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o +obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c new file mode 100644 index 0000000000..f32e528f93 --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -0,0 +1,1732 @@ +/* + * R8A77990 processor support - PFC hardware block. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <dm/pinctrl.h> +#include <linux/kernel.h> + +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_18(0, fn, sfx), \ + PORT_GP_23(1, fn, sfx), \ + PORT_GP_26(2, fn, sfx), \ + PORT_GP_16(3, fn, sfx), \ + PORT_GP_11(4, fn, sfx), \ + PORT_GP_20(5, fn, sfx), \ + PORT_GP_18(6, fn, sfx) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_17 F_(SDA4, IP7_27_24) +#define GPSR0_16 F_(SCL4, IP7_23_20) +#define GPSR0_15 F_(D15, IP7_19_16) +#define GPSR0_14 F_(D14, IP7_15_12) +#define GPSR0_13 F_(D13, IP7_11_8) +#define GPSR0_12 F_(D12, IP7_7_4) +#define GPSR0_11 F_(D11, IP7_3_0) +#define GPSR0_10 F_(D10, IP6_31_28) +#define GPSR0_9 F_(D9, IP6_27_24) +#define GPSR0_8 F_(D8, IP6_23_20) +#define GPSR0_7 F_(D7, IP6_19_16) +#define GPSR0_6 F_(D6, IP6_15_12) +#define GPSR0_5 F_(D5, IP6_11_8) +#define GPSR0_4 F_(D4, IP6_7_4) +#define GPSR0_3 F_(D3, IP6_3_0) +#define GPSR0_2 F_(D2, IP5_31_28) +#define GPSR0_1 F_(D1, IP5_27_24) +#define GPSR0_0 F_(D0, IP5_23_20) + +/* GPSR1 */ +#define GPSR1_22 F_(WE0_N, IP5_19_16) +#define GPSR1_21 F_(CS0_N, IP5_15_12) +#define GPSR1_20 FM(CLKOUT) +#define GPSR1_19 F_(A19, IP5_11_8) +#define GPSR1_18 F_(A18, IP5_7_4) +#define GPSR1_17 F_(A17, IP5_3_0) +#define GPSR1_16 F_(A16, IP4_31_28) +#define GPSR1_15 F_(A15, IP4_27_24) +#define GPSR1_14 F_(A14, IP4_23_20) +#define GPSR1_13 F_(A13, IP4_19_16) +#define GPSR1_12 F_(A12, IP4_15_12) +#define GPSR1_11 F_(A11, IP4_11_8) +#define GPSR1_10 F_(A10, IP4_7_4) +#define GPSR1_9 F_(A9, IP4_3_0) +#define GPSR1_8 F_(A8, IP3_31_28) +#define GPSR1_7 F_(A7, IP3_27_24) +#define GPSR1_6 F_(A6, IP3_23_20) +#define GPSR1_5 F_(A5, IP3_19_16) +#define GPSR1_4 F_(A4, IP3_15_12) +#define GPSR1_3 F_(A3, IP3_11_8) +#define GPSR1_2 F_(A2, IP3_7_4) +#define GPSR1_1 F_(A1, IP3_3_0) +#define GPSR1_0 F_(A0, IP2_31_28) + +/* GPSR2 */ +#define GPSR2_25 F_(EX_WAIT0, IP2_27_24) +#define GPSR2_24 F_(RD_WR_N, IP2_23_20) +#define GPSR2_23 F_(RD_N, IP2_19_16) +#define GPSR2_22 F_(BS_N, IP2_15_12) +#define GPSR2_21 FM(AVB_PHY_INT) +#define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) +#define GPSR2_19 FM(AVB_RD3) +#define GPSR2_18 F_(AVB_RD2, IP1_31_28) +#define GPSR2_17 F_(AVB_RD1, IP1_27_24) +#define GPSR2_16 F_(AVB_RD0, IP1_23_20) +#define GPSR2_15 FM(AVB_RXC) +#define GPSR2_14 FM(AVB_RX_CTL) +#define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) +#define GPSR2_12 F_(RPC_INT_N, IP1_15_12) +#define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) +#define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) +#define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) +#define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) +#define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) +#define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) +#define GPSR2_5 FM(QSPI0_SSL) +#define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) +#define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) +#define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) +#define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) +#define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) + +/* GPSR3 */ +#define GPSR3_15 F_(SD1_WP, IP11_7_4) +#define GPSR3_14 F_(SD1_CD, IP11_3_0) +#define GPSR3_13 F_(SD0_WP, IP10_31_28) +#define GPSR3_12 F_(SD0_CD, IP10_27_24) +#define GPSR3_11 F_(SD1_DAT3, IP9_11_8) +#define GPSR3_10 F_(SD1_DAT2, IP9_7_4) +#define GPSR3_9 F_(SD1_DAT1, IP9_3_0) +#define GPSR3_8 F_(SD1_DAT0, IP8_31_28) +#define GPSR3_7 F_(SD1_CMD, IP8_27_24) +#define GPSR3_6 F_(SD1_CLK, IP8_23_20) +#define GPSR3_5 F_(SD0_DAT3, IP8_19_16) +#define GPSR3_4 F_(SD0_DAT2, IP8_15_12) +#define GPSR3_3 F_(SD0_DAT1, IP8_11_8) +#define GPSR3_2 F_(SD0_DAT0, IP8_7_4) +#define GPSR3_1 F_(SD0_CMD, IP8_3_0) +#define GPSR3_0 F_(SD0_CLK, IP7_31_28) + +/* GPSR4 */ +#define GPSR4_10 F_(SD3_DS, IP10_23_20) +#define GPSR4_9 F_(SD3_DAT7, IP10_19_16) +#define GPSR4_8 F_(SD3_DAT6, IP10_15_12) +#define GPSR4_7 F_(SD3_DAT5, IP10_11_8) +#define GPSR4_6 F_(SD3_DAT4, IP10_7_4) +#define GPSR4_5 F_(SD3_DAT3, IP10_3_0) +#define GPSR4_4 F_(SD3_DAT2, IP9_31_28) +#define GPSR4_3 F_(SD3_DAT1, IP9_27_24) +#define GPSR4_2 F_(SD3_DAT0, IP9_23_20) +#define GPSR4_1 F_(SD3_CMD, IP9_19_16) +#define GPSR4_0 F_(SD3_CLK, IP9_15_12) + +/* GPSR5 */ +#define GPSR5_19 F_(MLB_DAT, IP13_23_20) +#define GPSR5_18 F_(MLB_SIG, IP13_19_16) +#define GPSR5_17 F_(MLB_CLK, IP13_15_12) +#define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) +#define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) +#define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) +#define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) +#define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) +#define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) +#define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) +#define GPSR5_9 F_(RX2_A, IP12_15_12) +#define GPSR5_8 F_(TX2_A, IP12_11_8) +#define GPSR5_7 F_(SCK2_A, IP12_7_4) +#define GPSR5_6 F_(TX1, IP12_3_0) +#define GPSR5_5 F_(RX1, IP11_31_28) +#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) +#define GPSR5_3 F_(CTS0_N_A, IP11_19_16) +#define GPSR5_2 F_(TX0_A, IP11_15_12) +#define GPSR5_1 F_(RX0_A, IP11_11_8) +#define GPSR5_0 F_(SCK0_A, IP11_27_24) + +/* GPSR6 */ +#define GPSR6_17 F_(USB30_PWEN, IP15_27_24) +#define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) +#define GPSR6_15 F_(SSI_WS6, IP15_15_12) +#define GPSR6_14 F_(SSI_SCK6, IP15_11_8) +#define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) +#define GPSR6_12 F_(SSI_WS5, IP15_3_0) +#define GPSR6_11 F_(SSI_SCK5, IP14_31_28) +#define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) +#define GPSR6_9 F_(USB30_OVC, IP15_31_28) +#define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) +#define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) +#define GPSR6_6 F_(SSI_WS349, IP14_19_16) +#define GPSR6_5 F_(SSI_SCK349, IP14_15_12) +#define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) +#define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) +#define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) +#define GPSR6_1 F_(SSI_WS01239, IP13_31_28) +#define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ +#define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ +#define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ +#define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB1_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ +#define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ +\ + \ + \ + \ + \ + \ + \ + GPSR2_25 \ + GPSR2_24 \ + GPSR2_23 \ + GPSR1_22 GPSR2_22 \ + GPSR1_21 GPSR2_21 \ + GPSR1_20 GPSR2_20 \ + GPSR1_19 GPSR2_19 GPSR5_19 \ + GPSR1_18 GPSR2_18 GPSR5_18 \ +GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ +\ +FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ +FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ +FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ +FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ +FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ +FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ +FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ +FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 + +/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0) +#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) +#define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0) +#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) +#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) +#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) +#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) +#define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) FM(SEL_I2C1_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) +#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) +#define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0) +#define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0) +#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) +#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) +#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) +#define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0) +#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) +#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) +#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) +#define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0) + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) +#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) +#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) +#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) +#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) +#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) +#define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) +#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) +#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) +#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) +#define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0) +#define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) +#define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0) +#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) +#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) +#define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0) +#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) + +#define PINMUX_MOD_SELS \ +\ + MOD_SEL1_31 \ +MOD_SEL0_30_29 MOD_SEL1_30 \ + MOD_SEL1_29 \ +MOD_SEL0_28 MOD_SEL1_28 \ +MOD_SEL0_27_26 \ + MOD_SEL1_26 \ +MOD_SEL0_25 MOD_SEL1_25 \ +MOD_SEL0_24 MOD_SEL1_24_23_22 \ +MOD_SEL0_23 \ +MOD_SEL0_22 \ +MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ +MOD_SEL0_19_18_17 MOD_SEL1_18 \ + MOD_SEL1_17 \ +MOD_SEL0_16 MOD_SEL1_16 \ +MOD_SEL0_15 MOD_SEL1_15 \ +MOD_SEL0_14 MOD_SEL1_14_13 \ +MOD_SEL0_13_12 \ + MOD_SEL1_12_11 \ +MOD_SEL0_11_10 \ + MOD_SEL1_10_9 \ +MOD_SEL0_9 \ +MOD_SEL0_8 MOD_SEL1_8 \ +MOD_SEL0_7 MOD_SEL1_7 \ +MOD_SEL0_6_5 MOD_SEL1_6_5 \ +MOD_SEL0_4 MOD_SEL1_4 \ +MOD_SEL0_3 \ +MOD_SEL0_2 \ +MOD_SEL0_1_0 + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), + PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), + + PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), + PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), + + PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), + PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), + + PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), + PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), + + PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), + PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), + + PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), + PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), + PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), + PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), + PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), + PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), + PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), + PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), + PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), + PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), + PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), + PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), + PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), + PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), + PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), + PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), + + PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), + + PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), + + PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), + + PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), + + PINMUX_IPSR_GPSR(IP2_15_12, BS_N), + PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), + PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), + PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), + PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), + PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP2_19_16, RD_N), + PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), + PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), + PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), + PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), + PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), + PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), + PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A), + PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), + PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), + PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), + + PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), + PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), + PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A), + PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), + PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), + + PINMUX_IPSR_GPSR(IP2_31_28, A0), + PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), + PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), + PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), + PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), + PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_GPSR(IP2_31_28, IERX), + PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, A1), + PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), + PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), + PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), + PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), + PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP3_3_0, IETX), + PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), + + PINMUX_IPSR_GPSR(IP3_7_4, A2), + PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), + PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), + PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), + PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), + PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), + + PINMUX_IPSR_GPSR(IP3_11_8, A3), + PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), + PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), + PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), + PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), + PINMUX_IPSR_GPSR(IP3_11_8, IECLK), + PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), + + PINMUX_IPSR_GPSR(IP3_15_12, A4), + PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), + PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), + PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), + PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), + + PINMUX_IPSR_GPSR(IP3_19_16, A5), + PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), + PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), + PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), + PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), + + PINMUX_IPSR_GPSR(IP3_23_20, A6), + PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), + PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), + + PINMUX_IPSR_GPSR(IP3_27_24, A7), + PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), + PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), + PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), + PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), + + PINMUX_IPSR_GPSR(IP3_31_28, A8), + PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), + PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), + PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, A9), + PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), + PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), + PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), + PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), + PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), + + PINMUX_IPSR_GPSR(IP4_7_4, A10), + PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), + PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), + PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), + PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), + PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), + + PINMUX_IPSR_GPSR(IP4_11_8, A11), + PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), + PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), + PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), + PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), + PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), + + PINMUX_IPSR_GPSR(IP4_15_12, A12), + PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), + PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), + PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), + PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), + + PINMUX_IPSR_GPSR(IP4_19_16, A13), + PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), + PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), + PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), + PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), + + PINMUX_IPSR_GPSR(IP4_23_20, A14), + PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), + PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), + PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), + PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), + PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), + + PINMUX_IPSR_GPSR(IP4_27_24, A15), + PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), + PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), + PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), + PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), + + PINMUX_IPSR_GPSR(IP4_31_28, A16), + PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), + PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), + PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), + PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, A17), + PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), + PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), + PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), + + PINMUX_IPSR_GPSR(IP5_7_4, A18), + PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), + PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), + PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), + PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), + + PINMUX_IPSR_GPSR(IP5_11_8, A19), + PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), + PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), + PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), + PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), + + PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), + PINMUX_IPSR_GPSR(IP5_15_12, SCL5), + PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), + PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), + + PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), + PINMUX_IPSR_GPSR(IP5_19_16, SDA5), + PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), + PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), + + PINMUX_IPSR_GPSR(IP5_23_20, D0), + PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), + PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), + + PINMUX_IPSR_GPSR(IP5_27_24, D1), + PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), + PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), + PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), + PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), + + PINMUX_IPSR_GPSR(IP5_31_28, D2), + PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), + PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, D3), + PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), + PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), + PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), + PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), + PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), + + PINMUX_IPSR_GPSR(IP6_7_4, D4), + PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), + PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), + PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), + PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), + PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), + PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP6_11_8, D5), + PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), + PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), + + PINMUX_IPSR_GPSR(IP6_15_12, D6), + PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), + PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), + PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), + PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), + PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), + + PINMUX_IPSR_GPSR(IP6_19_16, D7), + PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), + PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), + PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), + PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP6_23_20, D8), + PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), + PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), + PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), + + PINMUX_IPSR_GPSR(IP6_27_24, D9), + PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), + PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), + PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), + + PINMUX_IPSR_GPSR(IP6_31_28, D10), + PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), + PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), + PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), + PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, D11), + PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), + PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), + PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), + PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), + PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), + + PINMUX_IPSR_GPSR(IP7_7_4, D12), + PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), + PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), + PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), + PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), + PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP7_11_8, D13), + PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), + PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), + PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), + PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), + PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP7_15_12, D14), + PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), + PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), + PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), + PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), + + PINMUX_IPSR_GPSR(IP7_19_16, D15), + PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), + PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), + PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), + PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), + PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), + + PINMUX_IPSR_GPSR(IP7_23_20, SCL4), + PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), + PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), + PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), + PINMUX_IPSR_GPSR(IP7_23_20, QCLK), + + PINMUX_IPSR_GPSR(IP7_27_24, SDA4), + PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), + PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), + PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), + + PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), + PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), + PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), + PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), + PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), + PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), + + PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), + PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), + PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), + PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), + + PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), + PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), + PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), + + PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), + PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), + PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), + + PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), + PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), + PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), + PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), + PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), + + PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + + PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + + PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), + PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), + PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), + + PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), + PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), + + PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), + PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), + + PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), + PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), + + PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), + PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), + + PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), + PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), + + PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), + PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), + + PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), + PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), + PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), + + PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), + PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), + + PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), + PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), + + PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), + PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), + + PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), + PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), + + PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), + PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), + + PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), + PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), + PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), + PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), + PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), + PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), + + PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), + PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), + PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), + PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), + PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), + PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), + + /* IPSR11 */ + PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), + PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), + PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), + PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), + PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), + + PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), + PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), + PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), + PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), + PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), + + PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), + PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), + + PINMUX_IPSR_GPSR(IP11_15_12, TX0_A), + PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), + PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), + PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), + + PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), + PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), + PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), + + PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), + PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), + PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), + + PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), + PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_GPSR(IP11_27_24, USB1_ID), + + PINMUX_IPSR_GPSR(IP11_31_28, RX1), + PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), + + /* IPSR12 */ + PINMUX_IPSR_GPSR(IP12_3_0, TX1), + PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), + PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), + + PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A), + PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), + PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), + PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), + PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), + + PINMUX_IPSR_GPSR(IP12_11_8, TX2_A), + PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), + PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), + PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), + + PINMUX_IPSR_GPSR(IP12_15_12, RX2_A), + PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), + PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), + PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), + PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), + + PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), + + PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), + PINMUX_IPSR_GPSR(IP12_23_20, TX2_B), + + PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), + PINMUX_IPSR_GPSR(IP12_27_24, RX2_B), + + PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), + PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), + + /* IPSR13 */ + PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), + PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), + PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), + PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), + + PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), + PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), + PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), + PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), + + PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), + PINMUX_IPSR_GPSR(IP13_11_8, SCK1), + + PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), + PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), + + PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), + PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), + + PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), + PINMUX_IPSR_GPSR(IP13_23_20, TX0_B), + PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), + PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), + + PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), + + PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), + + /* IPSR14 */ + PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), + + PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), + PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), + + PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), + PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), + PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), + + PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), + PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), + + PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), + PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), + + PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), + PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), + PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), + PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), + + PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), + + PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), + PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), + PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), + PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), + + /* IPSR15 */ + PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), + PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), + PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), + PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), + + PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), + PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), + PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), + + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), + PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), + PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), + PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), + + PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), + PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), + PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), + PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), + PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), + PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), + + PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), + PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), + PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), + PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), + PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), + + PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), + + PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), + PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), + + PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), + PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { +}; + +static const struct sh_pfc_function pinmux_functions[] = { +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_25_FN, GPSR2_25, + GP_2_24_FN, GPSR2_24, + GP_2_23_FN, GPSR2_23, + GP_2_22_FN, GPSR2_22, + GP_2_21_FN, GPSR2_21, + GP_2_20_FN, GPSR2_20, + GP_2_19_FN, GPSR2_19, + GP_2_18_FN, GPSR2_18, + GP_2_17_FN, GPSR2_17, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + IP7_15_12 + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + IP11_31_28 + IP11_27_24 + IP11_23_20 + IP11_19_16 + IP11_15_12 + IP11_11_8 + IP11_7_4 + IP11_3_0 } + }, + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + IP12_31_28 + IP12_27_24 + IP12_23_20 + IP12_19_16 + IP12_15_12 + IP12_11_8 + IP12_7_4 + IP12_3_0 } + }, + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + IP13_31_28 + IP13_27_24 + IP13_23_20 + IP13_19_16 + IP13_15_12 + IP13_11_8 + IP13_7_4 + IP13_3_0 } + }, + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + IP14_31_28 + IP14_27_24 + IP14_23_20 + IP14_19_16 + IP14_15_12 + IP14_11_8 + IP14_7_4 + IP14_3_0 } + }, + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + IP15_31_28 + IP15_27_24 + IP15_23_20 + IP15_19_16 + IP15_15_12 + IP15_11_8 + IP15_7_4 + IP15_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, + 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { + /* RESERVED 31 */ + 0, 0, + MOD_SEL0_30_29 + MOD_SEL0_28 + MOD_SEL0_27_26 + MOD_SEL0_25 + MOD_SEL0_24 + MOD_SEL0_23 + MOD_SEL0_22 + MOD_SEL0_21_20 + MOD_SEL0_19_18_17 + MOD_SEL0_16 + MOD_SEL0_15 + MOD_SEL0_14 + MOD_SEL0_13_12 + MOD_SEL0_11_10 + MOD_SEL0_9 + MOD_SEL0_8 + MOD_SEL0_7 + MOD_SEL0_6_5 + MOD_SEL0_4 + MOD_SEL0_3 + MOD_SEL0_2 + MOD_SEL0_1_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, + 1, 2, 2, 2, 1, 1, 2, 1, 4) { + MOD_SEL1_31 + MOD_SEL1_30 + MOD_SEL1_29 + MOD_SEL1_28 + /* RESERVED 27 */ + 0, 0, + MOD_SEL1_26 + MOD_SEL1_25 + MOD_SEL1_24_23_22 + MOD_SEL1_21_20_19 + MOD_SEL1_18 + MOD_SEL1_17 + MOD_SEL1_16 + MOD_SEL1_15 + MOD_SEL1_14_13 + MOD_SEL1_12_11 + MOD_SEL1_10_9 + MOD_SEL1_8 + MOD_SEL1_7 + MOD_SEL1_6_5 + MOD_SEL1_4 + /* RESERVED 3, 2, 1, 0 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a77990_pinmux_info = { + .name = "r8a77990_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 66f0ce11b6..01a027f663 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -29,6 +29,7 @@ enum sh_pfc_model { SH_PFC_R8A7795, SH_PFC_R8A7796, SH_PFC_R8A77970, + SH_PFC_R8A77990, SH_PFC_R8A77995, };

@@ -806,6 +807,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A77970) priv->pfc.info = &r8a77970_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77990 + if (model == SH_PFC_R8A77990) + priv->pfc.info = &r8a77990_pinmux_info; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77995 if (model == SH_PFC_R8A77995) priv->pfc.info = &r8a77995_pinmux_info; @@ -870,6 +875,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A77970, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77990 + { + .compatible = "renesas,pfc-r8a77990", + .data = SH_PFC_R8A77990, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77995 { .compatible = "renesas,pfc-r8a77995", diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 9755826201..f4060096e2 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -253,6 +253,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; +extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 08/15] gpio: rmobile: Add R8A77990 E3 compatible

Add new compatible to the GPIO driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/gpio/gpio-rcar.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index b46621f76b..6fd1270640 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -175,6 +175,7 @@ static const struct udevice_id rcar_gpio_ids[] = { { .compatible = "renesas,gpio-r8a7796" }, { .compatible = "renesas,gpio-r8a77965" }, { .compatible = "renesas,gpio-r8a77970" }, + { .compatible = "renesas,gpio-r8a77990" }, { .compatible = "renesas,gpio-r8a77995" }, { .compatible = "renesas,rcar-gen2-gpio" }, { .compatible = "renesas,rcar-gen3-gpio" },

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 09/15] mmc: renesas-sdhi: Add R8A77990 E3 compatible

Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Masahiro Yamada yamada.masahiro@socionext.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/mmc/renesas-sdhi.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 62577895ee..ecdb088ac4 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -323,6 +323,7 @@ static const struct udevice_id renesas_sdhi_match[] = { { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS }, { /* sentinel */ } };

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 10/15] net: ravb: Add R8A77990 E3 compatible

Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/net/ravb.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 3392e5854d..999894f0f6 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -659,6 +659,7 @@ static const struct udevice_id ravb_ids[] = { { .compatible = "renesas,etheravb-r8a7796" }, { .compatible = "renesas,etheravb-r8a77965" }, { .compatible = "renesas,etheravb-r8a77970" }, + { .compatible = "renesas,etheravb-r8a77990" }, { .compatible = "renesas,etheravb-r8a77995" }, { .compatible = "renesas,etheravb-rcar-gen3" }, { }

-- 2.16.2

Joe Hershberger

7 Jun 7 Jun

12:31 a.m.

New subject: [U-Boot] [PATCH 10/15] net: ravb: Add R8A77990 E3 compatible

On Fri, Jun 1, 2018 at 2:45 AM, Marek Vasut marek.vasut@gmail.com wrote:

...

Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org

Acked-by: Joe Hershberger joe.hershberger@ni.com

Marek Vasut

1 Jun 1 Jun

9:45 a.m.

New subject: [U-Boot] [PATCH 11/15] ARM: renesas: Add R8A77990 E3 SoC ID

Add ID and Kconfig entry for the Renesas R8A77990 E3 SoC.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/mach-rmobile/Kconfig.64 | 3 +++ arch/arm/mach-rmobile/cpu_info.c | 1 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 3 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 6112d79f0d..6b93d25358 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -12,6 +12,9 @@ config R8A7796 config R8A77970 bool "Renesas SoC R8A77970"

+config R8A77990 + bool "Renesas SoC R8A77990" + config R8A77995 bool "Renesas SoC R8A77995"

diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 4e6a191cb1..e110737471 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -59,6 +59,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, { RMOBILE_CPU_TYPE_R8A77965, "R8A77965" }, { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" }, + { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 94ea366f45..c94b3ff509 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -35,6 +35,7 @@ #define RMOBILE_CPU_TYPE_R8A7796 0x52 #define RMOBILE_CPU_TYPE_R8A77965 0x55 #define RMOBILE_CPU_TYPE_R8A77970 0x54 +#define RMOBILE_CPU_TYPE_R8A77990 0x57 #define RMOBILE_CPU_TYPE_R8A77995 0x58

#ifndef __ASSEMBLY__

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 12/15] ARM: dts: rmobile: Add Renesas R8A77990 SoC support

From: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com

This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC: - PSCI - CPU (single) - Cache controller - Main clocks and controller - Interrupt controller - Timer - PMU - Reset controller - Product register - System controller - UART for console

Inspried by a patch by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/r8a77990.dtsi | 131 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 arch/arm/dts/r8a77990.dtsi

diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi new file mode 100644 index 0000000000..310bfd9d88 --- /dev/null +++ b/arch/arm/dts/r8a77990.dtsi @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the r8a77990 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r8a77990"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a53_0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77990-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77990-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77990-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 310>; + status = "disabled"; + }; + }; +};

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 13/15] ARM: dts: rmobile: Add Renesas Ebisu board support

From: Takeshi Kihara takeshi.kihara.df@renesas.com

Basic support for the Renesas Ebisu board based on R-Car E3: - Memory, - Main crystal, - Serial console,

Signed-off-by: Takeshi Kihara takeshi.kihara.df@renesas.com [shimoda: rebase and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r8a77990-ebisu.dts | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/dts/r8a77990-ebisu.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8975..6df8bc2fd6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -439,6 +439,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a7796-salvator-x.dtb \ r8a77965-salvator-x.dtb \ r8a77970-eagle.dtb \ + r8a77990-ebisu.dtb \ r8a77995-draak.dtb

dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts new file mode 100644 index 0000000000..63ee1347bb --- /dev/null +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the ebisu board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77990.dtsi" + +/ { + model = "Renesas Ebisu board based on r8a77990"; + compatible = "renesas,ebisu", "renesas,r8a77990"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +};

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 14/15] ARM: renesas: Add R8A77990 E3 Ebisu board

Add support for the R8A77990 Ebisu board.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/r8a77990-ebisu-u-boot.dts | 10 ++++ arch/arm/dts/r8a77990-u-boot.dtsi | 9 ++++ arch/arm/mach-rmobile/Kconfig.64 | 6 +++ board/renesas/ebisu/Kconfig | 15 ++++++ board/renesas/ebisu/MAINTAINERS | 6 +++ board/renesas/ebisu/Makefile | 9 ++++ board/renesas/ebisu/ebisu.c | 87 ++++++++++++++++++++++++++++++++++ configs/r8a77990_ebisu_defconfig | 64 +++++++++++++++++++++++++ include/configs/ebisu.h | 34 +++++++++++++ 9 files changed, 240 insertions(+) create mode 100644 arch/arm/dts/r8a77990-ebisu-u-boot.dts create mode 100644 arch/arm/dts/r8a77990-u-boot.dtsi create mode 100644 board/renesas/ebisu/Kconfig create mode 100644 board/renesas/ebisu/MAINTAINERS create mode 100644 board/renesas/ebisu/Makefile create mode 100644 board/renesas/ebisu/ebisu.c create mode 100644 configs/r8a77990_ebisu_defconfig create mode 100644 include/configs/ebisu.h

diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts new file mode 100644 index 0000000000..28bc497046 --- /dev/null +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -0,0 +1,10 @@ +/* + * Device Tree Source extras for U-Boot for the Ebisu board + * + * Copyright (C) 2018 Marek Vasut marek.vasut@gmail.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "r8a77990-ebisu.dts" +#include "r8a77990-u-boot.dtsi" diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi new file mode 100644 index 0000000000..30a9f0b8ea --- /dev/null +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -0,0 +1,9 @@ +/* + * Device Tree Source extras for U-Boot on RCar R8A77990 SoC + * + * Copyright (C) 2018 Marek Vasut marek.vasut@gmail.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "r8a779x-u-boot.dtsi" diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 6b93d25358..cb9f569e5f 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -34,6 +34,11 @@ config TARGET_EAGLE help Support for Renesas R-Car Gen3 Eagle platform

+config TARGET_EBISU + bool "Ebisu board" + help + Support for Renesas R-Car Gen3 Ebisu platform + config TARGET_SALVATOR_X bool "Salvator-X board" help @@ -51,6 +56,7 @@ config SYS_SOC

source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" +source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig"

diff --git a/board/renesas/ebisu/Kconfig b/board/renesas/ebisu/Kconfig new file mode 100644 index 0000000000..f500a94c9a --- /dev/null +++ b/board/renesas/ebisu/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EBISU + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "ebisu" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ebisu" + +endif diff --git a/board/renesas/ebisu/MAINTAINERS b/board/renesas/ebisu/MAINTAINERS new file mode 100644 index 0000000000..facad520ca --- /dev/null +++ b/board/renesas/ebisu/MAINTAINERS @@ -0,0 +1,6 @@ +EBISU BOARD +M: Marek Vasut marek.vasut+renesas@gmail.com +S: Maintained +F: board/renesas/ebisu/ +F: include/configs/ebisu.h +F: configs/r8a77990_ebisu_defconfig diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile new file mode 100644 index 0000000000..2741035c57 --- /dev/null +++ b/board/renesas/ebisu/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/ebisu/Makefile +# +# Copyright (C) 2018 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ebisu.o diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c new file mode 100644 index 0000000000..92062141a2 --- /dev/null +++ b/board/renesas/ebisu/ebisu.c @@ -0,0 +1,87 @@ +/* + * board/renesas/ebisu/ebisu.c + * This file is Ebisu board support. + * + * Copyright (C) 2018 Marek Vasut marek.vasut+renesas@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +#define TMU0_MSTP125 BIT(25) /* secure */ + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig new file mode 100644 index 0000000000..591eafed3b --- /dev/null +++ b/configs/r8a77990_ebisu_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77990=y +CONFIG_TARGET_EBISU=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttySC0,115200" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_MANUFACTURER="" diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h new file mode 100644 index 0000000000..7dc4651dd2 --- /dev/null +++ b/include/configs/ebisu.h @@ -0,0 +1,34 @@ +/* + * include/configs/ebisu.h + * This file is Ebisu board configuration. + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EBISU_H +#define __EBISU_H + +#undef DEBUG + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 48000000u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 2 +#define CONFIG_SYS_MMC_ENV_PART 2 + +#endif /* __EBISU_H */

-- 2.16.2

Marek Vasut

9:45 a.m.

New subject: [U-Boot] [PATCH 15/15] ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux

Import the R8A77990 and Ebisu DTS from linux-next to get the latest version. This makes AVB ethernet work in U-Boot since the ethernet node is now present in DT, as well as GPIOs.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/r8a77990-ebisu.dts | 28 +++++ arch/arm/dts/r8a77990.dtsi | 220 +++++++++++++++++++++++++++++++++------- 2 files changed, 213 insertions(+), 35 deletions(-)

diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 63ee1347bb..7a09d0524f 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -7,6 +7,7 @@

/dts-v1/; #include "r8a77990.dtsi" +#include <dt-bindings/gpio/gpio.h>

/ { model = "Renesas Ebisu board based on r8a77990"; @@ -14,6 +15,7 @@

aliases { serial0 = &scif2; + ethernet0 = &avb; };

chosen { @@ -28,10 +30,36 @@ }; };

+&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <48000000>; };

+&pfc { + avb_pins: avb { + mux { + groups = "avb_link", "avb_mii"; + function = "avb"; + }; + }; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index 310bfd9d88..be4f519711 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -27,9 +27,8 @@ enable-method = "psci"; };

- L2_CA53: cache-controller@0 { + L2_CA53: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc 21>; cache-unified; cache-level = <2>; @@ -43,8 +42,14 @@ clock-frequency = <0>; };

+ pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>; + }; + psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; };

@@ -55,39 +60,114 @@ #size-cells = <2>; ranges;

- gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 18>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc 32>; - resets = <&cpg 408>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc 32>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc 32>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc 32>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 11>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc 32>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc 32>; + resets = <&cpg 907>; };

- timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc 32>; + resets = <&cpg 906>; };

- pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77990"; + reg = <0 0xe6060000 0 0x508>; };

cpg: clock-controller@e6150000 { @@ -105,17 +185,57 @@ reg = <0 0xe6160000 0 0x0200>; };

- prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77990-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; };

+ avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77990", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77990", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -127,5 +247,35 @@ resets = <&cpg 310>; status = "disabled"; }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; };

-- 2.16.2

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Joe Hershberger
Marek Vasut