[U-Boot] [PATCH 1/3] imx: mx6ul: skip setting ahb rate
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them.
Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/soc.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bdd41b0..f29901f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -328,13 +328,18 @@ int arch_cpu_init(void) */ init_bandgap();
- /* - * When low freq boot is enabled, ROM will not set AHB - * freq, so we need to ensure AHB freq is 132MHz in such - * scenario. - */ - if (mxc_get_clock(MXC_ARM_CLK) == 396000000) - set_ahb_rate(132000000); + if (!IS_ENABLED(CONFIG_MX6UL)) { + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + * + * To i.MX6UL, when power up, default ARM core and + * AHB rate is 396M and 132M. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + }
/* Set perclk to source from OSC 24MHz */ #if defined(CONFIG_MX6SL)
Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin for i.MX 6UltraLite TO1.0.
Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/soc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f29901f..d4b22ad 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -341,7 +341,17 @@ int arch_cpu_init(void) set_ahb_rate(132000000); }
- /* Set perclk to source from OSC 24MHz */ + if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) { + /* + * According to the design team's requirement on i.MX6UL, + * the PMIC_STBY_REQ PAD should be configured as open + * drain 100K (0x0000b8a0). + * Only exists on TO1.0 + */ + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + } + + /* Set perclk to source from OSC 24MHz */ #if defined(CONFIG_MX6SL) set_preclk_from_osc(); #endif
Default print ARM clock for clocks command. Test on i.MX6UL 14x14 evk board: " => clocks PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz
ARM 396000 kHz "
Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/clock.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 88380a6..3b53842 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n"); + printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI
Hi Stefano,
Gentle Ping on the three patches.
Thanks, Peng. On Wed, Mar 09, 2016 at 04:44:36PM +0800, Peng Fan wrote:
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them.
Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/armv7/mx6/soc.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bdd41b0..f29901f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -328,13 +328,18 @@ int arch_cpu_init(void) */ init_bandgap();
- /*
* When low freq boot is enabled, ROM will not set AHB* freq, so we need to ensure AHB freq is 132MHz in such* scenario.*/- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
if (!IS_ENABLED(CONFIG_MX6UL)) {
/** When low freq boot is enabled, ROM will not set AHB* freq, so we need to ensure AHB freq is 132MHz in such* scenario.** To i.MX6UL, when power up, default ARM core and* AHB rate is 396M and 132M.*/if (mxc_get_clock(MXC_ARM_CLK) == 396000000)set_ahb_rate(132000000);}
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
2.6.2
On 25/03/2016 10:16, Peng Fan wrote:
Hi Stefano,
Gentle Ping on the three patches.
Thanks, Peng. On Wed, Mar 09, 2016 at 04:44:36PM +0800, Peng Fan wrote:
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them.
Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/armv7/mx6/soc.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bdd41b0..f29901f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -328,13 +328,18 @@ int arch_cpu_init(void) */ init_bandgap();
- /*
* When low freq boot is enabled, ROM will not set AHB* freq, so we need to ensure AHB freq is 132MHz in such* scenario.*/- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
if (!IS_ENABLED(CONFIG_MX6UL)) {
/** When low freq boot is enabled, ROM will not set AHB* freq, so we need to ensure AHB freq is 132MHz in such* scenario.** To i.MX6UL, when power up, default ARM core and* AHB rate is 396M and 132M.*/if (mxc_get_clock(MXC_ARM_CLK) == 396000000)set_ahb_rate(132000000);}
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
2.6.2
Appplied (whole series) to u-boot-imx, thanks !
Best regards, Stefano Babic
participants (2)
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Peng Fan -
Stefano Babic