[U-Boot] [PATCH v2 1/5] arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- Changes in v2: update to the lastest base. --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ board/freescale/ls1021aqds/ls1021aqds.c | 49 +----------------- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--------------- 5 files changed, 83 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2311468..0228300 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..0fdd6d4 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h> + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d889ad5..be3358a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> @@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; }
-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -205,40 +193,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4918c11..8eaff5f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> @@ -138,17 +139,6 @@ int checkboard(void) return 0; }
-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -394,8 +384,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -407,33 +395,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) {
Enable the IP feature's snoop signal to support hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal for various masters.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++ 2 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 0fdd6d4..6036473 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -62,5 +62,13 @@ int arch_soc_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); }
+ /* Enable all the snoop signal for various masters */ + out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | + SCFG_SNPCNFGCR_DCU_RD_WR | + SCFG_SNPCNFGCR_SATA_RD_WR | + SCFG_SNPCNFGCR_USB3_RD_WR | + SCFG_SNPCNFGCR_DBG_RD_WR | + SCFG_SNPCNFGCR_EDMA_SNP); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 09ed980..704d785 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -150,6 +150,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000
/* Supplemental Configuration Unit */
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 6036473..97ba6d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -40,8 +40,14 @@ int arch_soc_init(void)
/* * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) + * All the slave insterfaces. */ + out_le32(&cci->slave[0].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[1].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[2].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
This is a workaround for hardware erratum. Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- Changes in v2: Rewrite the commit message to explain why and what this patch does. --- arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 97ba6d5..b15cd60 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -76,5 +76,15 @@ int arch_soc_init(void) SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP);
+ /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 704d785..6b04674 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -228,7 +228,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr;
On 11/05/2015 02:26 AM, Yuan Yao wrote:
This is a workaround for hardware erratum. Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
Changes in v2: Rewrite the commit message to explain why and what this patch does.
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York
Hi york,
Is it for DDR4? LS1021A doesn't use this file.
Best Regards, Yuan Yao
-----Original Message----- From: York Sun [mailto:yorksun@freescale.com] Sent: Friday, November 06, 2015 2:05 AM To: Yuan Yao-B46683 yao.yuan@freescale.com Cc: Wang Huan-B18965 alison.wang@freescale.com; u-boot@lists.denx.de Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
On 11/05/2015 02:26 AM, Yuan Yao wrote:
This is a workaround for hardware erratum. Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
Changes in v2: Rewrite the commit message to explain why and what this patch does.
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York
On 11/09/2015 01:30 AM, Yuan Yao-B46683 wrote:
Hi york,
Is it for DDR4? LS1021A doesn't use this file.
LS1021A support both DDR3 and DDR4. DDR4 mode uses this driver, doesn't it? My concern is if the workaround is implemented in different places, it will be harder to maintain in future versions fix this erratum. Maybe moving the workaround out of DDR driver to SoC is not a bad idea.
York
Best Regards, Yuan Yao
-----Original Message----- From: York Sun [mailto:yorksun@freescale.com] Sent: Friday, November 06, 2015 2:05 AM To: Yuan Yao-B46683 yao.yuan@freescale.com Cc: Wang Huan-B18965 alison.wang@freescale.com; u-boot@lists.denx.de Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
On 11/05/2015 02:26 AM, Yuan Yao wrote:
This is a workaround for hardware erratum. Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
Changes in v2: Rewrite the commit message to explain why and what this patch does.
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York
Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4. And It should be as a workaround for the SOC.
________________________________________ From: York Sun yorksun@freescale.com Sent: Tuesday, November 10, 2015 1:01 To: Yuan Yao-B46683 Cc: Wang Huan-B18965; u-boot@lists.denx.de Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
On 11/09/2015 01:30 AM, Yuan Yao-B46683 wrote:
Hi york,
Is it for DDR4? LS1021A doesn't use this file.
LS1021A support both DDR3 and DDR4. DDR4 mode uses this driver, doesn't it? My concern is if the workaround is implemented in different places, it will be harder to maintain in future versions fix this erratum. Maybe moving the workaround out of DDR driver to SoC is not a bad idea.
York
Best Regards, Yuan Yao
-----Original Message----- From: York Sun [mailto:yorksun@freescale.com] Sent: Friday, November 06, 2015 2:05 AM To: Yuan Yao-B46683 yao.yuan@freescale.com Cc: Wang Huan-B18965 alison.wang@freescale.com; u-boot@lists.denx.de Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
On 11/05/2015 02:26 AM, Yuan Yao wrote:
This is a workaround for hardware erratum. Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
Changes in v2: Rewrite the commit message to explain why and what this patch does.
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
Workaround for A008514 is already implemented in DDR driver drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround into it.
York
On 11/10/2015 05:18 AM, Yuan Yao-B46683 wrote:
Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4. And It should be as a workaround for the SOC.
Please make the patch if you are comfortable. Please gate the code with the macro CONFIG_SYS_FSL_ERRATUM_A008514.
York
Hi York,
Thanks, And is there any other comments for this set of patches? Or could I send v3 for review?
Best Regards,
Yuan Yao ________________________________________ From: York Sun yorksun@freescale.com Sent: Wednesday, November 11, 2015 0:43 To: Yuan Yao-B46683 Cc: Wang Huan-B18965; u-boot@lists.denx.de Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
On 11/10/2015 05:18 AM, Yuan Yao-B46683 wrote:
Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC. I think the workaround is not just only for ddr4. And It should be as a workaround for the SOC.
Please make the patch if you are comfortable. Please gate the code with the macro CONFIG_SYS_FSL_ERRATUM_A008514.
York
Erratum number: ERR008514 EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0 silicon for LS1021A.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- Changes in v2: Add the Erratum number. --- arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b15cd60..98d4acd 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -25,7 +25,7 @@ int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; + unsigned int major, reg;
#ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20002);
+ /* + * EDDRTQCFG Registers are Integration Strap values which controls + * performance parameters for DDR Controller. + * The bit 25 is used for disable priorities within DDR. + * This is a workaround because of the DDR are connected backwards + * on Rev2.0. + */ + reg = in_be32(&scfg->eddrtqcfg); + reg |= 1 << 6; + out_be32(&scfg->eddrtqcfg, reg); + return 0; }
participants (3)
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Yao Yuan -
York Sun -
Yuan Yao