[U-Boot] [PATCH 0/7] arm64: zynqmp: Switch to use dt-binding headers

newer
[U-Boot] [PATCH 1/2] arm64:...

older
[U-Boot] [PATCH] arm64: zynqmp:...

Michal Simek

14 Oct 2019 14 Oct '19

4:19 p.m.

Hi,

use macros from headers and sync dtses with latest description.

Thanks, Michal

Michal Simek (6): arm64: zynqmp: Switch to xlnx-zynqmp-clk header arm64: zynqmp: Use backward compatible string for gem dt-bindings: arm64: zynqmp: Add power and reset headers arm64: zynqmp: Use reset header in zynqmp.dtsi arm64: zynqmp: Use power header in zynqmp.dtsi arm64: zynqmp: List lpd watchdog in dtsi

Rajan Vaja (1): dt-bindings: clock: zynqmp: Add clk header

arch/arm/dts/zynqmp-clk-ccf.dtsi | 166 ++++++++---------- arch/arm/dts/zynqmp-clk.dtsi | 4 + arch/arm/dts/zynqmp.dtsi | 85 ++++++++- drivers/clk/clk_zynqmp.c | 1 - include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 +++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 39 ++++ .../dt-bindings/reset/xlnx-zynqmp-resets.h | 130 ++++++++++++++ 7 files changed, 450 insertions(+), 101 deletions(-) create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

-- 2.17.1

Show replies by date

Michal Simek

14 Oct 14 Oct

4:19 p.m.

New subject: [U-Boot] [PATCH 1/7] dt-bindings: clock: zynqmp: Add clk header

From: Rajan Vaja rajan.vaja@xilinx.com

Add dt clock header which can be included by dtses. And also use zynqmp-clk compatible string.

Signed-off-by: Rajan Vaja rajan.vaja@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 ++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h

diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h new file mode 100644 index 000000000000..cdc4c0b9a374 --- /dev/null +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +#define _DT_BINDINGS_CLK_ZYNQMP_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 2/7] arm64: zynqmp: Switch to xlnx-zynqmp-clk header

Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-clk-ccf.dtsi | 164 ++++++++++++++----------------- arch/arm/dts/zynqmp.dtsi | 2 +- drivers/clk/clk_zynqmp.c | 1 - 3 files changed, 73 insertions(+), 94 deletions(-)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 247a35f9219d..bd0f8eb22c5f 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -7,29 +7,30 @@ * Michal Simek michal.simek@xilinx.com */

+#include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { fclk0: fclk0 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 71>; + clocks = <&zynqmp_clk PL0_REF>; };

fclk1: fclk1 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 72>; + clocks = <&zynqmp_clk PL1_REF>; };

fclk2: fclk2 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 73>; + clocks = <&zynqmp_clk PL2_REF>; };

fclk3: fclk3 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <&clkc 74>; + clocks = <&zynqmp_clk PL3_REF>; };

pss_ref_clk: pss_ref_clk { @@ -67,35 +68,6 @@ clock-frequency = <27000000>; };

- clkc: clkc { - u-boot,dm-pre-reloc; - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clkc"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; - clock-output-names = "iopll", "rpll", "apll", "dpll", - "vpll", "iopll_to_fpd", "rpll_to_fpd", - "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", - "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", - "dbg_trace", "dbg_tstmp", "dp_video_ref", - "dp_audio_ref", "dp_stc_ref", "gdma_ref", - "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", - "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", - "topsw_main", "topsw_lsbus", "gtgref0_ref", - "lpd_switch", "lpd_lsbus", "usb0_bus_ref", - "usb1_bus_ref", "usb3_dual_ref", "usb0", - "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", - "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", - "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", - "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", - "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", - "uart0_ref", "uart1_ref", "spi0_ref", - "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", - "can0_ref", "can1_ref", "can0", "can1", - "dll_ref", "adma_ref", "timestamp_ref", - "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; - }; - dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -104,202 +76,210 @@ }; };

+&zynqmp_firmware { + zynqmp_clk: clock-controller { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <&gt_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; +}; + &can0 { - clocks = <&clkc 63>, <&clkc 31>; + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; };

&can1 { - clocks = <&clkc 64>, <&clkc 31>; + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; };

&cpu0 { - clocks = <&clkc 10>; + clocks = <&zynqmp_clk ACPU>; };

&fpd_dma_chan1 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan2 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan3 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan4 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan5 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan6 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan7 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&fpd_dma_chan8 { - clocks = <&clkc 19>, <&clkc 31>; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&gpu { - clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; };

&lpd_dma_chan1 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan2 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan3 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan4 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan5 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan6 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan7 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&lpd_dma_chan8 { - clocks = <&clkc 68>, <&clkc 31>; + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; };

&nand0 { - clocks = <&clkc 60>, <&clkc 31>; + clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; };

&gem0 { - clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, + <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; };

&gem1 { - clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, + <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; };

&gem2 { - clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, + <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; };

&gem3 { - clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, + <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; };

&gpio { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; };

&i2c0 { - clocks = <&clkc 61>; + clocks = <&zynqmp_clk I2C0_REF>; };

&i2c1 { - clocks = <&clkc 62>; + clocks = <&zynqmp_clk I2C1_REF>; };

&pcie { - clocks = <&clkc 23>; + clocks = <&zynqmp_clk PCIE_REF>; };

&qspi { - clocks = <&clkc 53>, <&clkc 31>; + clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; };

&sata { - clocks = <&clkc 22>; + clocks = <&zynqmp_clk SATA_REF>; };

&sdhci0 { - clocks = <&clkc 54>, <&clkc 31>; + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; };

&sdhci1 { - clocks = <&clkc 55>, <&clkc 31>; + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; };

&spi0 { - clocks = <&clkc 58>, <&clkc 31>; + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; };

&spi1 { - clocks = <&clkc 59>, <&clkc 31>; + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; };

&ttc0 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; };

&ttc1 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; };

&ttc2 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; };

&ttc3 { - clocks = <&clkc 31>; + clocks = <&zynqmp_clk LPD_LSBUS>; };

&uart0 { - clocks = <&clkc 56>, <&clkc 31>; + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; };

&uart1 { - clocks = <&clkc 57>, <&clkc 31>; + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; };

&usb0 { - clocks = <&clkc 32>, <&clkc 34>; + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; };

&usb1 { - clocks = <&clkc 33>, <&clkc 34>; + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; };

&watchdog0 { - clocks = <&clkc 75>; + clocks = <&zynqmp_clk WDT>; };

&xilinx_ams { - clocks = <&clkc 70>; -}; - -&xilinx_drm { - clocks = <&clkc 16>; -}; - -&xlnx_dp { - clocks = <&dp_aclk>, <&clkc 17>; + clocks = <&zynqmp_clk AMS_REF>; };

&xlnx_dpdma { - clocks = <&clkc 20>; + clocks = <&zynqmp_clk DPDMA_REF>; };

&xlnx_dp_snd_codec0 { - clocks = <&clkc 17>; + clocks = <&zynqmp_clk DP_AUDIO_REF>; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 337922f8a966..854608c9382b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -140,7 +140,7 @@ };

firmware { - zynqmp-firmware { + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; #power-domain-cells = <0x1>; diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 167f3f75a19c..72fc39fa47a8 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -702,7 +702,6 @@ static struct clk_ops zynqmp_clk_ops = {

static const struct udevice_id zynqmp_clk_ids[] = { { .compatible = "xlnx,zynqmp-clk" }, - { .compatible = "xlnx,zynqmp-clkc" }, { } };

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 3/7] arm64: zynqmp: Use backward compatible string for gem

Add backward compatible string for gem ("cdns,gem").

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 854608c9382b..dea918a0419a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -539,7 +539,7 @@ };

gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -552,7 +552,7 @@ };

gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -565,7 +565,7 @@ };

gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -578,7 +578,7 @@ };

gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>;

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 4/7] dt-bindings: arm64: zynqmp: Add power and reset headers

Add power and reset headers to be sources by ZynqMP dtses.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

include/dt-bindings/power/xlnx-zynqmp-power.h | 39 ++++++ .../dt-bindings/reset/xlnx-zynqmp-resets.h | 130 ++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h new file mode 100644 index 000000000000..0d9a412fd5e0 --- /dev/null +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +#define _DT_BINDINGS_ZYNQMP_POWER_H + +#define PD_USB_0 22 +#define PD_USB_1 23 +#define PD_TTC_0 24 +#define PD_TTC_1 25 +#define PD_TTC_2 26 +#define PD_TTC_3 27 +#define PD_SATA 28 +#define PD_ETH_0 29 +#define PD_ETH_1 30 +#define PD_ETH_2 31 +#define PD_ETH_3 32 +#define PD_UART_0 33 +#define PD_UART_1 34 +#define PD_SPI_0 35 +#define PD_SPI_1 36 +#define PD_I2C_0 37 +#define PD_I2C_1 38 +#define PD_SD_0 39 +#define PD_SD_1 40 +#define PD_DP 41 +#define PD_GDMA 42 +#define PD_ADMA 43 +#define PD_NAND 44 +#define PD_QSPI 45 +#define PD_GPIO 46 +#define PD_CAN_0 47 +#define PD_CAN_1 48 +#define PD_GPU 58 +#define PD_PCIE 59 + +#endif diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h new file mode 100644 index 000000000000..d44525b9f8db --- /dev/null +++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H +#define _DT_BINDINGS_ZYNQMP_RESETS_H + +#define ZYNQMP_RESET_PCIE_CFG 0 +#define ZYNQMP_RESET_PCIE_BRIDGE 1 +#define ZYNQMP_RESET_PCIE_CTRL 2 +#define ZYNQMP_RESET_DP 3 +#define ZYNQMP_RESET_SWDT_CRF 4 +#define ZYNQMP_RESET_AFI_FM5 5 +#define ZYNQMP_RESET_AFI_FM4 6 +#define ZYNQMP_RESET_AFI_FM3 7 +#define ZYNQMP_RESET_AFI_FM2 8 +#define ZYNQMP_RESET_AFI_FM1 9 +#define ZYNQMP_RESET_AFI_FM0 10 +#define ZYNQMP_RESET_GDMA 11 +#define ZYNQMP_RESET_GPU_PP1 12 +#define ZYNQMP_RESET_GPU_PP0 13 +#define ZYNQMP_RESET_GPU 14 +#define ZYNQMP_RESET_GT 15 +#define ZYNQMP_RESET_SATA 16 +#define ZYNQMP_RESET_ACPU3_PWRON 17 +#define ZYNQMP_RESET_ACPU2_PWRON 18 +#define ZYNQMP_RESET_ACPU1_PWRON 19 +#define ZYNQMP_RESET_ACPU0_PWRON 20 +#define ZYNQMP_RESET_APU_L2 21 +#define ZYNQMP_RESET_ACPU3 22 +#define ZYNQMP_RESET_ACPU2 23 +#define ZYNQMP_RESET_ACPU1 24 +#define ZYNQMP_RESET_ACPU0 25 +#define ZYNQMP_RESET_DDR 26 +#define ZYNQMP_RESET_APM_FPD 27 +#define ZYNQMP_RESET_SOFT 28 +#define ZYNQMP_RESET_GEM0 29 +#define ZYNQMP_RESET_GEM1 30 +#define ZYNQMP_RESET_GEM2 31 +#define ZYNQMP_RESET_GEM3 32 +#define ZYNQMP_RESET_QSPI 33 +#define ZYNQMP_RESET_UART0 34 +#define ZYNQMP_RESET_UART1 35 +#define ZYNQMP_RESET_SPI0 36 +#define ZYNQMP_RESET_SPI1 37 +#define ZYNQMP_RESET_SDIO0 38 +#define ZYNQMP_RESET_SDIO1 39 +#define ZYNQMP_RESET_CAN0 40 +#define ZYNQMP_RESET_CAN1 41 +#define ZYNQMP_RESET_I2C0 42 +#define ZYNQMP_RESET_I2C1 43 +#define ZYNQMP_RESET_TTC0 44 +#define ZYNQMP_RESET_TTC1 45 +#define ZYNQMP_RESET_TTC2 46 +#define ZYNQMP_RESET_TTC3 47 +#define ZYNQMP_RESET_SWDT_CRL 48 +#define ZYNQMP_RESET_NAND 49 +#define ZYNQMP_RESET_ADMA 50 +#define ZYNQMP_RESET_GPIO 51 +#define ZYNQMP_RESET_IOU_CC 52 +#define ZYNQMP_RESET_TIMESTAMP 53 +#define ZYNQMP_RESET_RPU_R50 54 +#define ZYNQMP_RESET_RPU_R51 55 +#define ZYNQMP_RESET_RPU_AMBA 56 +#define ZYNQMP_RESET_OCM 57 +#define ZYNQMP_RESET_RPU_PGE 58 +#define ZYNQMP_RESET_USB0_CORERESET 59 +#define ZYNQMP_RESET_USB1_CORERESET 60 +#define ZYNQMP_RESET_USB0_HIBERRESET 61 +#define ZYNQMP_RESET_USB1_HIBERRESET 62 +#define ZYNQMP_RESET_USB0_APB 63 +#define ZYNQMP_RESET_USB1_APB 64 +#define ZYNQMP_RESET_IPI 65 +#define ZYNQMP_RESET_APM_LPD 66 +#define ZYNQMP_RESET_RTC 67 +#define ZYNQMP_RESET_SYSMON 68 +#define ZYNQMP_RESET_AFI_FM6 69 +#define ZYNQMP_RESET_LPD_SWDT 70 +#define ZYNQMP_RESET_FPD 71 +#define ZYNQMP_RESET_RPU_DBG1 72 +#define ZYNQMP_RESET_RPU_DBG0 73 +#define ZYNQMP_RESET_DBG_LPD 74 +#define ZYNQMP_RESET_DBG_FPD 75 +#define ZYNQMP_RESET_APLL 76 +#define ZYNQMP_RESET_DPLL 77 +#define ZYNQMP_RESET_VPLL 78 +#define ZYNQMP_RESET_IOPLL 79 +#define ZYNQMP_RESET_RPLL 80 +#define ZYNQMP_RESET_GPO3_PL_0 81 +#define ZYNQMP_RESET_GPO3_PL_1 82 +#define ZYNQMP_RESET_GPO3_PL_2 83 +#define ZYNQMP_RESET_GPO3_PL_3 84 +#define ZYNQMP_RESET_GPO3_PL_4 85 +#define ZYNQMP_RESET_GPO3_PL_5 86 +#define ZYNQMP_RESET_GPO3_PL_6 87 +#define ZYNQMP_RESET_GPO3_PL_7 88 +#define ZYNQMP_RESET_GPO3_PL_8 89 +#define ZYNQMP_RESET_GPO3_PL_9 90 +#define ZYNQMP_RESET_GPO3_PL_10 91 +#define ZYNQMP_RESET_GPO3_PL_11 92 +#define ZYNQMP_RESET_GPO3_PL_12 93 +#define ZYNQMP_RESET_GPO3_PL_13 94 +#define ZYNQMP_RESET_GPO3_PL_14 95 +#define ZYNQMP_RESET_GPO3_PL_15 96 +#define ZYNQMP_RESET_GPO3_PL_16 97 +#define ZYNQMP_RESET_GPO3_PL_17 98 +#define ZYNQMP_RESET_GPO3_PL_18 99 +#define ZYNQMP_RESET_GPO3_PL_19 100 +#define ZYNQMP_RESET_GPO3_PL_20 101 +#define ZYNQMP_RESET_GPO3_PL_21 102 +#define ZYNQMP_RESET_GPO3_PL_22 103 +#define ZYNQMP_RESET_GPO3_PL_23 104 +#define ZYNQMP_RESET_GPO3_PL_24 105 +#define ZYNQMP_RESET_GPO3_PL_25 106 +#define ZYNQMP_RESET_GPO3_PL_26 107 +#define ZYNQMP_RESET_GPO3_PL_27 108 +#define ZYNQMP_RESET_GPO3_PL_28 109 +#define ZYNQMP_RESET_GPO3_PL_29 110 +#define ZYNQMP_RESET_GPO3_PL_30 111 +#define ZYNQMP_RESET_GPO3_PL_31 112 +#define ZYNQMP_RESET_RPU_LS 113 +#define ZYNQMP_RESET_PS_ONLY 114 +#define ZYNQMP_RESET_PL 115 +#define ZYNQMP_RESET_PS_PL0 116 +#define ZYNQMP_RESET_PS_PL1 117 +#define ZYNQMP_RESET_PS_PL2 118 +#define ZYNQMP_RESET_PS_PL3 119 + +#endif

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 5/7] arm64: zynqmp: Use reset header in zynqmp.dtsi

Wire reset-controller and use macros from reset header.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index dea918a0419a..a498ff9af623 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -12,6 +12,8 @@ * the License, or (at your option) any later version. */

+#include <dt-bindings/reset/xlnx-zynqmp-resets.h> + / { compatible = "xlnx,zynqmp"; #address-cells = <2>; @@ -154,6 +156,11 @@ mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; }; };

@@ -700,10 +707,18 @@ reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; - resets = <&rst 16>, <&rst 59>, <&rst 60>, - <&rst 61>, <&rst 62>, <&rst 63>, - <&rst 64>, <&rst 3>, <&rst 29>, - <&rst 30>, <&rst 31>, <&rst 32>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, + <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, + <&zynqmp_reset ZYNQMP_RESET_DP>, + <&zynqmp_reset ZYNQMP_RESET_GEM0>, + <&zynqmp_reset ZYNQMP_RESET_GEM1>, + <&zynqmp_reset ZYNQMP_RESET_GEM2>, + <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst",

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 6/7] arm64: zynqmp: Use power header in zynqmp.dtsi

Use power header and add power-domains property.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a498ff9af623..6f81909043aa 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -12,6 +12,7 @@ * the License, or (at your option) any later version. */

+#include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

/ { @@ -286,6 +287,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_0>; };

can1: can@ff070000 { @@ -297,6 +299,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_1>; };

cci: cci@fd6e0000 { @@ -329,6 +332,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan2: dma@fd510000 { @@ -341,6 +345,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan3: dma@fd520000 { @@ -353,6 +358,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan4: dma@fd530000 { @@ -365,6 +371,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan5: dma@fd540000 { @@ -377,6 +384,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan6: dma@fd550000 { @@ -389,6 +397,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan7: dma@fd560000 { @@ -401,6 +410,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

fpd_dma_chan8: dma@fd570000 { @@ -413,6 +423,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; + power-domains = <&zynqmp_firmware PD_GDMA>; };

gpu: gpu@fd4b0000 { @@ -423,6 +434,7 @@ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; + power-domains = <&zynqmp_firmware PD_GPU>; };

/* LPDDMA default allows only secured access. inorder to enable @@ -439,6 +451,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan2: dma@ffa90000 { @@ -451,6 +464,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan3: dma@ffaa0000 { @@ -463,6 +477,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan4: dma@ffab0000 { @@ -475,6 +490,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan5: dma@ffac0000 { @@ -487,6 +503,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan6: dma@ffad0000 { @@ -499,6 +516,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan7: dma@ffae0000 { @@ -511,6 +529,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

lpd_dma_chan8: dma@ffaf0000 { @@ -523,6 +542,7 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; + power-domains = <&zynqmp_firmware PD_ADMA>; };

mc: memory-controller@fd070000 { @@ -543,6 +563,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; + power-domains = <&zynqmp_firmware PD_NAND>; };

gem0: ethernet@ff0b0000 { @@ -556,6 +577,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; + power-domains = <&zynqmp_firmware PD_ETH_0>; };

gem1: ethernet@ff0c0000 { @@ -569,6 +591,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; + power-domains = <&zynqmp_firmware PD_ETH_1>; };

gem2: ethernet@ff0d0000 { @@ -582,6 +605,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; + power-domains = <&zynqmp_firmware PD_ETH_2>; };

gem3: ethernet@ff0e0000 { @@ -595,6 +619,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; + power-domains = <&zynqmp_firmware PD_ETH_3>; };

gpio: gpio@ff0a0000 { @@ -607,6 +632,7 @@ #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; + power-domains = <&zynqmp_firmware PD_GPIO>; };

i2c0: i2c@ff020000 { @@ -617,6 +643,7 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_0>; };

i2c1: i2c@ff030000 { @@ -627,6 +654,7 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_1>; };

ocm: memory-controller@ff960000 { @@ -665,6 +693,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -686,6 +715,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; + power-domains = <&zynqmp_firmware PD_QSPI>; };

rtc: rtc@ffa60000 { @@ -743,6 +773,7 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; + power-domains = <&zynqmp_firmware PD_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -760,6 +791,7 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; + power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -808,6 +840,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_0>; };

spi1: spi@ff050000 { @@ -819,6 +852,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_1>; };

ttc0: timer@ff110000 { @@ -828,6 +862,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_0>; };

ttc1: timer@ff120000 { @@ -837,6 +872,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_1>; };

ttc2: timer@ff130000 { @@ -846,6 +882,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_2>; };

ttc3: timer@ff140000 { @@ -855,6 +892,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_3>; };

uart0: serial@ff000000 { @@ -865,6 +903,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_0>; };

uart1: serial@ff010000 { @@ -875,6 +914,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_1>; };

usb0: usb0@ff9d0000 { @@ -884,6 +924,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; + power-domains = <&zynqmp_firmware PD_USB_0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -909,6 +950,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; + power-domains = <&zynqmp_firmware PD_USB_1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1001,6 +1043,7 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; + power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel {

-- 2.17.1

Michal Simek

4:19 p.m.

New subject: [U-Boot] [PATCH 7/7] arm64: zynqmp: List lpd watchdog in dtsi

There are use cases where lpd watchdog can be configured for APU use. By design this IP should be listed in zynqmp.dtsi to make sure that node is properly enabled by DTG.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp-clk.dtsi | 4 ++++ arch/arm/dts/zynqmp.dtsi | 9 +++++++++ 3 files changed, 17 insertions(+)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index bd0f8eb22c5f..998298cc9bee 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -272,6 +272,10 @@ clocks = <&zynqmp_clk WDT>; };

+&lpd_watchdog { + clocks = <&zynqmp_clk LPD_WDT>; +}; + &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index c70f85a43020..9ef55ad0d18e 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -223,6 +223,10 @@ clocks = <&clk100>; };

+&lpd_watchdog { + clocks = <&clk250>; +}; + &xilinx_drm { clocks = <&drm_clock>; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6f81909043aa..2bc49c391249 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -979,6 +979,15 @@ reset-on-timeout; };

+ lpd_watchdog: watchdog@ff150000 { + compatible = "cdns,wdt-r1p2"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 52 1>; + reg = <0x0 0xff150000 0x0 0x1000>; + timeout-sec = <10>; + }; + xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled";

-- 2.17.1

Michal Simek

24 Oct 24 Oct

1:25 p.m.

New subject: [U-Boot] [PATCH 0/7] arm64: zynqmp: Switch to use dt-binding headers

po 14. 10. 2019 v 16:19 odesílatel Michal Simek michal.simek@xilinx.com napsal:

...

Hi,

use macros from headers and sync dtses with latest description.

Thanks, Michal

Michal Simek (6): arm64: zynqmp: Switch to xlnx-zynqmp-clk header arm64: zynqmp: Use backward compatible string for gem dt-bindings: arm64: zynqmp: Add power and reset headers arm64: zynqmp: Use reset header in zynqmp.dtsi arm64: zynqmp: Use power header in zynqmp.dtsi arm64: zynqmp: List lpd watchdog in dtsi

Rajan Vaja (1): dt-bindings: clock: zynqmp: Add clk header

arch/arm/dts/zynqmp-clk-ccf.dtsi | 166 ++++++++---------- arch/arm/dts/zynqmp-clk.dtsi | 4 + arch/arm/dts/zynqmp.dtsi | 85 ++++++++- drivers/clk/clk_zynqmp.c | 1 - include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 +++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 39 ++++ .../dt-bindings/reset/xlnx-zynqmp-resets.h | 130 ++++++++++++++ 7 files changed, 450 insertions(+), 101 deletions(-) create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

-- 2.17.1

Applied but with also adding power domain for SD1 in "arm64: zynqmp: Use power header in zynqmp.dtsi"

-- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

2032

Age (days ago)

2042

Last active (days ago)

List overview

Download

8 comments

2 participants

tags (0)

participants (2)

Michal Simek
Michal Simek