SMI driver fails because of low timeout values. Increasing the erase and write timeouts to 3 seconds

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/spr_smi.h | 6 +++--- drivers/mtd/spr_smi.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h index 06df745..e2e5e8f 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/arch/arm/include/asm/arch-spear/spr_smi.h @@ -108,8 +108,8 @@ struct flash_dev { ushort sector_count; };

-#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ +#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ +#define XFER_FINISH_TOUT (3 * CONFIG_SYS_HZ) +#define WMODE_TOUT (3 * CONFIG_SYS_HZ)

#endif diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c index 9a70a19..189ee6d 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/spr_smi.c @@ -60,11 +60,11 @@ static struct flash_dev flash_ids[] = { */ static void smi_wait_xfer_finish(int timeout) { - while (timeout--) { + do { if (readl(&smicntl->smi_sr) & TFF) break; udelay(1000); - } + } while (timeout--); }

/* @@ -215,11 +215,11 @@ static int smi_write_enable(int bank) /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1);

- while (timeout--) { + do { if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) break; udelay(1000); - } + } while (timeout--);

if (timeout) return 0;

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- include/configs/spear-common.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index cc52e39..b526558 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -208,6 +208,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_MAXSIZE 0x40000000 +#define PHYS_SDRAM_1_MAXSIZE 0x08000000

#endif

Designware network driver support added. This is a Synopsys ethernet controller

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- drivers/net/Makefile | 1 + drivers/net/designware.c | 537 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/designware.h | 264 +++++++++++++++++++++++ include/netdev.h | 1 + 4 files changed, 803 insertions(+), 0 deletions(-) create mode 100644 drivers/net/designware.c create mode 100644 drivers/net/designware.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ec0ba1..82df908 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o +COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c new file mode 100644 index 0000000..9361f77 --- /dev/null +++ b/drivers/net/designware.c @@ -0,0 +1,537 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * (C) Copyright 2008 + * Deepak Sikri, ST Micoelectronics, deepak.sikri@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Designware ethernet IP driver for u-boot + */ + +#include <common.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/io.h> +#include "designware.h" + +static void tx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ + DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); + + desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; + desc_p->dmamac_cntl = 0; + desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); +#else + desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; + desc_p->txrx_status = 0; +#endif + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); +} + +static void rx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + + desc_p->dmamac_cntl = + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + DESC_RXCTRL_RXCHAIN; + + desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); +} + +static void descs_init(struct eth_device *dev) +{ + tx_descs_init(dev); + rx_descs_init(dev); +} + +static int mac_reset(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + int timeout = CONFIG_MACRESET_TIMEOUT; + + writel(DMAMAC_SRST, &dma_p->busmode); + writel(MII_PORTSELECT, &mac_p->conf); + + do { + if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) + break; + udelay(1000); + } while (timeout--); + + if (timeout < 0) + return -1; + + return 0; +} + +static void program_mac(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + \ + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); +} + +static int dw_eth_init(struct eth_device *dev, bd_t *bis) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf; + + /* Reset ethernet hardware */ + if (mac_reset(dev) < 0) + return -1; + + program_mac(dev); + + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + &dma_p->busmode); + + writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); + writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + + conf = FRAMEBURSTENABLE | DISABLERXOWN; + + if (priv->speed != SPEED_1000M) + conf |= MII_PORTSELECT; + + if (priv->duplex == FULL_DUPLEX) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + descs_init(dev); + + /* + * Start/Enable xfer at dma as well as mac level + */ + writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); + writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + + writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + + return 0; +} + +static int dw_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + + /* Check if the descriptor is owned by CPU */ + if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -1; + } + + memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK; + + desc_p->txrx_status &= ~(DESC_TXSTS_MSK); + desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#else + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + DESC_TXCTRL_TXFIRST; + + desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; +#endif + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + return 0; +} + +static int dw_eth_recv(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + + u32 status = desc_p->txrx_status; + int length = 0; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + + length = (status & DESC_RXSTS_FRMLENMSK) >> \ + DESC_RXSTS_FRMLENSHFT; + + NetReceive(desc_p->dmamac_addr, length); + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + } + + priv->rx_currdescnum = desc_num; + + return length; +} + +static void dw_eth_halt(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + + mac_reset(dev); + priv->tx_currdescnum = priv->rx_currdescnum = 0; +} + +static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + break; + udelay(1000); + } while (timeout--); + + *val = readl(&mac_p->miidata); + + if (timeout < 0) + return -1; + + return 0; +} + +static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + u16 value; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + break; + udelay(1000); + } while (timeout--); + + /* Needed as a fix for ST-Phy */ + eth_mdio_read(dev, addr, reg, &value); + + if (timeout < 0) + return -1; + + return 0; +} + +static int find_phy(struct eth_device *dev) +{ + int phy_addr = 0; + u16 ctrl, oldctrl; + + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + oldctrl = ctrl & PHY_BMCR_AUTON; + + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + ctrl &= PHY_BMCR_AUTON; + + if (ctrl == oldctrl) { + phy_addr++; + } else { + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + + return phy_addr; + } + } while (phy_addr < 32); + + return -1; +} + +static int dw_reset_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u16 ctrl; + int timeout = CONFIG_PHYRESET_TIMEOUT; + u32 phy_addr = priv->address; + + eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + if (!(ctrl & PHY_BMCR_RESET)) + break; + udelay(1000); + } while (timeout--); + + if (timeout < 0) + return -1; + +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); +#endif + return 0; +} + +static int configure_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + int phy_addr; + u16 bmcr, ctrl; +#if defined(CONFIG_DW_AUTONEG) + u16 bmsr; + u32 timeout; + u16 anlpar, btsr; +#endif + phy_addr = find_phy(dev); + priv->address = phy_addr; + + if (phy_addr < 0) + return -1; + + if (dw_reset_phy(dev) < 0) + return -1; + +#if defined(CONFIG_DW_AUTONEG) + bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ + PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; +#else + bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + +#if defined(CONFIG_DW_SPEED10M) + bmcr &= ~PHY_BMCR_100MB; +#endif +#if defined(CONFIG_DW_DUPLEXHALF) + bmcr &= ~PHY_BMCR_DPLX; +#endif +#endif + if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + return -1; + + /* Read the phy status register and populate priv structure */ +#if defined(CONFIG_DW_AUTONEG) + timeout = CONFIG_AUTONEG_TIMEOUT; + do { + eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); + if (bmsr & PHY_BMSR_AUTN_COMP) + break; + udelay(1000); + } while (timeout--); + + eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); + eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + + if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + priv->speed = SPEED_1000M; + if (btsr & PHY_1000BTSR_1000FD) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } else { + if (anlpar & PHY_ANLPAR_100) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; + + if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } +#else + if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + return -1; + + if (ctrl & PHY_BMCR_DPLX) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + + if (ctrl & PHY_BMCR_1000_MBPS) + priv->speed = SPEED_1000M; + else if (ctrl & PHY_BMCR_100_MBPS) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; +#endif + return 0; +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_read(dev, addr, reg, val); + + return 0; +} + +static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_write(dev, addr, reg, val); + + return 0; +} +#endif + +int designware_initialize(u32 id, ulong base_addr) +{ + struct eth_device *dev; + struct dw_eth_dev *priv; + + dev = (struct eth_device *) malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_eth_dev)); + + sprintf(dev->name, "mii%d", id); + dev->iobase = (int)base_addr; + dev->priv = priv; + + eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]); + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + + if (mac_reset(dev) < 0) + return -1; + + if (configure_phy(dev) < 0) { + printf("Phy could not be configured\n"); + return -1; + } + + dev->init = dw_eth_init; + dev->send = dw_eth_send; + dev->recv = dw_eth_recv; + dev->halt = dw_eth_halt; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, dw_mii_read, dw_mii_write); +#endif + return 1; +} diff --git a/drivers/net/designware.h b/drivers/net/designware.h new file mode 100644 index 0000000..8f7e1ef --- /dev/null +++ b/drivers/net/designware.h @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DW_ETH_H +#define _DW_ETH_H + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 framefilt; /* 0x04 */ + u32 hashtablehigh; /* 0x08 */ + u32 hashtablelow; /* 0x0c */ + u32 miiaddr; /* 0x10 */ + u32 miidata; /* 0x14 */ + u32 flowcontrol; /* 0x18 */ + u32 vlantag; /* 0x1c */ + u32 version; /* 0x20 */ + u8 reserved_1[0x38 - 0x24]; + u32 intreg; /* 0x38 */ + u32 intmask; /* 0x3c */ + u32 macaddr0hi; /* 0x40 */ + u32 macaddr0lo; /* 0x44 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 21) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 13) +#define FULLDPLXMODE (1 << 11) +#define RXENABLE (1 << 2) +#define TXENABLE (1 << 3) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x4) +#define MII_CLKRANGE_20_35M (0x8) +#define MII_CLKRANGE_35_60M (0xC) +#define MII_CLKRANGE_150_250M (0x10) +#define MII_CLKRANGE_250_300M (0x14) + +#define MIIADDRSHIFT (11) +#define MIIREGSHIFT (6) +#define MII_REGMSK (0x1F << 6) +#define MII_ADDRMSK (0x1F << 11) + + +struct eth_dma_regs { + u32 busmode; /* 0x00 */ + u32 txpolldemand; /* 0x04 */ + u32 rxpolldemand; /* 0x08 */ + u32 rxdesclistaddr; /* 0x0c */ + u32 txdesclistaddr; /* 0x10 */ + u32 status; /* 0x14 */ + u32 opmode; /* 0x18 */ + u32 intenable; /* 0x1c */ + u8 reserved[0x48 - 0x20]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Bus mode register definitions */ +#define FIXEDBURST (1 << 16) +#define PRIORXTX_41 (3 << 14) +#define PRIORXTX_31 (2 << 14) +#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_11 (0 << 14) +#define BURST_1 (1 << 8) +#define BURST_2 (2 << 8) +#define BURST_4 (4 << 8) +#define BURST_8 (8 << 8) +#define BURST_16 (16 << 8) +#define BURST_32 (32 << 8) +#define RXHIGHPRIO (1 << 1) +#define DMAMAC_SRST (1 << 0) + +/* Poll demand definitions */ +#define POLL_DATA (0xFFFFFFFF) + +/* Operation mode definitions */ +#define STOREFORWARD (1 << 21) +#define FLUSHTXFIFO (1 << 20) +#define TXSTART (1 << 13) +#define TXSECONDFRAME (1 << 2) +#define RXSTART (1 << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (2048) + +struct dmamacdescr { + u32 txrx_status; + u32 dmamac_cntl; + void *dmamac_addr; + struct dmamacdescr *dmamac_next; +}; + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_TXINT (1 << 30) +#define DESC_TXSTS_TXLAST (1 << 29) +#define DESC_TXSTS_TXFIRST (1 << 28) +#define DESC_TXSTS_TXCRCDIS (1 << 27) + +#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) +#define DESC_TXSTS_TXRINGEND (1 << 21) +#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#else + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#endif + +/* rx status bits definitions */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) +#define DESC_RXSTS_FRMLENSHFT (16) + +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_RXTRUNCATED (1 << 14) +#define DESC_RXSTS_SAFILTERFAIL (1 << 13) +#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) +#define DESC_RXSTS_RXDAMAGED (1 << 11) +#define DESC_RXSTS_RXVLANTAG (1 << 10) +#define DESC_RXSTS_RXFIRST (1 << 9) +#define DESC_RXSTS_RXLAST (1 << 8) +#define DESC_RXSTS_RXIPC_GIANT (1 << 7) +#define DESC_RXSTS_RXCOLLISION (1 << 6) +#define DESC_RXSTS_RXFRAMEETHER (1 << 5) +#define DESC_RXSTS_RXWATCHDOG (1 << 4) +#define DESC_RXSTS_RXMIIERROR (1 << 3) +#define DESC_RXSTS_RXDRIBBLING (1 << 2) +#define DESC_RXSTS_RXCRC (1 << 1) + +/* + * dmamac_cntl definitions + */ + +/* tx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_TXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_TXCTRL_TXINT (1 << 31) +#define DESC_TXCTRL_TXLAST (1 << 30) +#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) +#define DESC_TXCTRL_TXCRCDIS (1 << 26) +#define DESC_TXCTRL_TXRINGEND (1 << 25) +#define DESC_TXCTRL_TXCHAIN (1 << 24) + +#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_TXCTRL_SIZE2SHFT (11) + +#endif + +/* rx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 15) +#define DESC_RXCTRL_RXCHAIN (1 << 14) + +#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_RXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 25) +#define DESC_RXCTRL_RXCHAIN (1 << 24) + +#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_RXCTRL_SIZE2SHFT (11) + +#endif + +struct dw_eth_dev { + u32 address; + u32 speed; + u32 duplex; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 padding; + + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + + char txbuffs[TX_TOTAL_BUFSIZE]; + char rxbuffs[RX_TOTAL_BUFSIZE]; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; + + struct eth_device *dev; +} __attribute__ ((aligned(8))); + +/* Speed specific definitions */ +#define SPEED_10M 1 +#define SPEED_100M 2 +#define SPEED_1000M 3 + +/* Duplex mode specific definitions */ +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +#endif diff --git a/include/netdev.h b/include/netdev.h index 1dd80f0..808fdde 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -47,6 +47,7 @@ int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); int davinci_emac_initialize(void); +int designware_initialize(u32 id, ulong base_addr); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis);

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/clk.h | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-spear/hardware.h | 7 +++++++ board/spear/spear310/spear310.c | 9 ++++++++- board/spear/spear320/spear320.c | 6 +++++- include/configs/spear3xx.h | 13 +++++++++++++ 5 files changed, 60 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-spear/clk.h

diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000..343c6ce --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 39d64b6..9f1e154 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -56,6 +56,11 @@ #define CONFIG_SPEAR_EMIBASE (0x4F000000) #define CONFIG_SPEAR_RASBASE (0xB4000000)

+#define CONFIG_SYS_MACB0_BASE (0xB0000000) +#define CONFIG_SYS_MACB1_BASE (0xB0800000) +#define CONFIG_SYS_MACB2_BASE (0xB1000000) +#define CONFIG_SYS_MACB3_BASE (0xB1800000) + #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SPEAR_FSMCBASE (0x4C000000) @@ -63,5 +68,7 @@ #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000)

+#define CONFIG_SYS_MACB0_BASE (0xAA000000) + #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index e8a6552..1207709 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -61,5 +61,12 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) { - return dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE); + dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE); + + macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, CONFIG_MACB0_PHY); + macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, CONFIG_MACB1_PHY); + macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, CONFIG_MACB2_PHY); + macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, CONFIG_MACB3_PHY); + + return 0; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 72bc9a5..efc9a99 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -61,5 +61,9 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) { - return dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE); + dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE); + + macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, CONFIG_MACB0_PHY); + + return 0; } diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 502c50f..689d914 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -44,6 +44,19 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR 1

+#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 + +#endif + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000

Since FSMC is a standard IP and it supports different memory interfaces the FSMC is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/hardware.h | 8 +- arch/arm/include/asm/arch-spear/spr_nand.h | 57 ------------- board/spear/spear300/spear300.c | 4 +- board/spear/spear310/spear310.c | 4 +- board/spear/spear320/spear320.c | 4 +- board/spear/spear600/spear600.c | 4 +- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/spr_nand.c | 124 ---------------------------- include/configs/spear-common.h | 2 +- include/configs/spear3xx.h | 4 + include/configs/spear6xx.h | 3 + 11 files changed, 20 insertions(+), 195 deletions(-) delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h delete mode 100644 drivers/mtd/nand/spr_nand.c

diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 9f1e154..52037b6 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -38,15 +38,15 @@

#if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_FSMC_BASE (0xD1800000)

#elif defined(CONFIG_SPEAR300) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_FSMC_BASE (0x94000000)

#elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_FSMC_BASE (0x44000000)

#undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE @@ -63,7 +63,7 @@

#elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_FSMC_BASE (0x4C000000)

#define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7..0000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index cd24247..bb98161 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -52,7 +52,7 @@ int board_nand_init(struct nand_chip *nand) ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); }

return -1; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 1207709..dfb7728 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -53,7 +53,7 @@ int board_nand_init(struct nand_chip *nand) ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); }

return -1; diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index efc9a99..a15ffc4 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -53,7 +53,7 @@ int board_nand_init(struct nand_chip *nand) ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); }

return -1; diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index 6d921bd..f7f25d2 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -48,7 +48,7 @@ int board_nand_init(struct nand_chip *nand) (struct misc_regs *)CONFIG_SPEAR_MISCBASE;

if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); + return fsmc_nand_init(nand);

return -1; } diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 4c6b54f..36fc8b3 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -48,7 +48,6 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c deleted file mode 100644 index 097d0c6..0000000 --- a/drivers/mtd/nand/spr_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <nand.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_nand.h> - -static struct fsmc_regs *const fsmc_regs_p = - (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; - -static struct nand_ecclayout spear_nand_ecclayout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->genmemctrl_pc) | - FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } else { - writel(readl(&fsmc_regs_p->genmemctrl_pc) & - ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int spear_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char ecc[3]) -{ - u_int ecc_tmp; - - /* read the h/w ECC */ - ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); - - ecc[0] = (u_char) (ecc_tmp & 0xFF); - ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); - ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); - - return 0; -} - -void spear_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); -} - -int spear_nand_init(struct nand_chip *nand) -{ - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->genmemctrl_pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_attrib); - - nand->options = 0; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &spear_nand_ecclayout; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.calculate = spear_read_hwecc; - nand->ecc.hwctl = spear_enable_hwecc; - nand->ecc.correct = nand_correct_data; - nand->cmd_ctrl = spear_nand_hwcontrol; - return 0; -} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ecb1fd1..3eaa086 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -90,7 +90,7 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NAND FLASH Configuration */ -#define CONFIG_NAND_SPEAR 1 +#define CONFIG_NAND_FSMC 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1

diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 689d914..fde505c 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -133,6 +133,10 @@

#endif

+/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 + #if defined(CONFIG_SPEAR300) #define CONFIG_SYS_NAND_BASE (0x80000000)

diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2ad5beb..2532344 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -38,6 +38,9 @@ #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1 }

+/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 #define CONFIG_SYS_NAND_BASE (0xD2000000)

#endif /* __CONFIG_H */

The smi IP used by spear platform is a ST serial memory interface controller The earlier driver adds the driver of this controller as if it is specific to spear platform. The driver files are now moved into drivers/mtd folder for reusability by other platforms

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- drivers/mtd/Makefile | 2 +- drivers/mtd/{spr_smi.c => st_smi.c} | 2 +- .../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 4 ++-- include/configs/spear-common.h | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/mtd/{spr_smi.c => st_smi.c} (99%) rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (99%)

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index cbf6f15..d868d27 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,7 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/st_smi.c similarity index 99% rename from drivers/mtd/spr_smi.c rename to drivers/mtd/st_smi.c index 189ee6d..80d9fee 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/st_smi.c @@ -27,7 +27,7 @@

#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_smi.h> +#include "st_smi.h"

#if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/drivers/mtd/st_smi.h similarity index 99% rename from arch/arm/include/asm/arch-spear/spr_smi.h rename to drivers/mtd/st_smi.h index e2e5e8f..37ed503 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/drivers/mtd/st_smi.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */

-#ifndef SPR_SMI_H -#define SPR_SMI_H +#ifndef ST_SMI_H +#define ST_SMI_H

/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index e49f267..99923de 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -57,10 +57,10 @@ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_SPEAR_EMI 1 #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI 1 #endif

-#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI)

#define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) @@ -125,7 +125,7 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /* * Environment is in serial NOR flash */

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 112 ++++++++ arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 99 +++++++ arch/arm/cpu/arm_cortexa8/spear13xx/reset.c | 47 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 136 ++++++++++ arch/arm/include/asm/arch-spear13xx/hardware.h | 40 +++ arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++++ arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 +++++++++++++++++++++++ arch/arm/include/asm/arch-spear13xx/sys_proto.h | 32 +++ 9 files changed, 920 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c create mode 100755 arch/arm/cpu/arm_cortexa8/spear13xx/reset.c create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/sys_proto.h

diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile new file mode 100644 index 0000000..4157164 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS += timer.o +COBJS += reset.o +COBJS += cpu.o + +SOBJS = cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S new file mode 100644 index 0000000..b3d1fb0 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.global invalidate_dcache + +/* + * invalidate_dcache() + * + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +.global l2_cache_enable +/* + * l2_cache_enable + */ +l2_cache_enable: + bx r14 + +.global l2_cache_disable +/* + * l2_cache_disable + */ +l2_cache_disable: + bx r14 diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c new file mode 100644 index 0000000..5a0ae56 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +u32 get_device_type(void) +{ + return 0; +} + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 perip1_clk_enb, perip2_clk_enb; +#if defined(CONFIG_NAND_FSMC) + u32 fsmc_cfg; +#endif + perip1_clk_enb = readl(&misc_p->perip1_clk_enb); + perip2_clk_enb = readl(&misc_p->perip2_clk_enb); + + perip1_clk_enb |= GPT1_CLKEN; + +#if defined(CONFIG_PL011_SERIAL) + perip1_clk_enb |= UART_CLKEN; +#endif + +#if defined(CONFIG_DESIGNWARE_ETH) + /* writel(SYNT_CLK_ENB | SYNT_FIN_FULL | SYNT_X_1 | SYNT_Y_5, + &misc_p->gmac_clk_synt); */ + writel(PHY_IF_GMII | CLK_SEL_OSCI3, &misc_p->gmac_clk_cfg); + + perip1_clk_enb |= GETH_CLKEN; +#endif + +#if defined(CONFIG_DW_UDC) + perip1_clk_enb |= UDC_UPD_CLKEN; +#endif + +#if defined(CONFIG_DW_I2C) + perip1_clk_enb |= I2C_CLKEN; +#endif + +#if defined(CONFIG_ST_SMI) + perip1_clk_enb |= SMI_CLKEN; +#endif + +#if defined(CONFIG_NAND_FSMC) + fsmc_cfg = readl(&misc_p->fsmc_cfg); + fsmc_cfg &= ~DEV_SEL_MSK; + fsmc_cfg |= DEV_SEL_NAND; +#if defined(CONFIG_BOARD_NAND_16BIT) + fsmc_cfg |= DEV_WIDTH_16; +#elif defined(CONFIG_BOARD_NAND_8BIT) + fsmc_cfg |= DEV_WIDTH_8; +#endif + writel(fsmc_cfg, &misc_p->fsmc_cfg); + + perip1_clk_enb |= FSMC_CLKEN; +#endif + + writel(perip1_clk_enb, &misc_p->perip1_clk_enb); + writel(perip2_clk_enb, &misc_p->perip2_clk_enb); + + return 0; +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: SPEAr1300\n"); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c new file mode 100755 index 0000000..9a43f85 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +void reset_cpu(ulong ignored) +{ + struct misc_regs *misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + writel(0x01, &misc_regs_p->sys_sw_res); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c new file mode 100644 index 0000000..d114a4a --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_gpt.h> +#include <asm/arch/spr_misc.h> + +#define GPT_TICKS (CONFIG_SPEAR_HZ_CLOCK / (1 << prescaler)) +#define GPT_RESOLUTION (GPT_TICKS / CONFIG_SPEAR_HZ) +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) + +static struct gpt_regs *const gpt_regs_p = + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; + +static ulong timestamp; +static ulong lastdec; +static const u32 prescaler = GPT_PRESCALER_16; + +int timer_init(void) +{ + /* disable timers */ + writel(prescaler | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); + + /* auto reload, start timer */ + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = GPT_TICKS / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SPEAR_HZ; +} diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h new file mode 100644 index 0000000..384260a --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SPEAR_TIMERBASE (0xE0380000) +#define CONFIG_SPEAR_MISCBASE (0xE0700000) +#define CONFIG_SYS_I2C_BASE (0xE0280000) +#define CONFIG_SPEAR_ETHBASE (0xE2000000) +#define CONFIG_SYS_FSMC_BASE (0xB0000000) + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/spr_gpt.h b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h new file mode 100644 index 0000000..ad464cb --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ (1000) +#define CONFIG_SPEAR_HZ_CLOCK (24000000) + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spr_misc.h b/arch/arm/include/asm/arch-spear13xx/spr_misc.h new file mode 100644 index 0000000..0b24843 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_misc.h @@ -0,0 +1,317 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR13XX_MISC_H +#define __SPR13XX_MISC_H + +struct misc_regs { + u32 soc_cfg; /* 0x000 */ + u32 bootstrap_cfg; /* 0x004 */ + u8 reserved_1[0x100 - 0x8]; + u32 pcm_cfg; /* 0x100 */ + u32 pcm_wkup_cfg; /* 0x104 */ + u32 switch_ctr; /* 0x108 */ + u8 reserved_2[0x200 - 0x10c]; + u32 sys_clk_ctrl; /* 0x200 */ + u32 sys_sw_res; /* 0x204 */ + u32 sys_clk_plltimer; /* 0x208 */ + u32 sys_clk_oscitimer; /* 0x20c */ + u32 pll_cfg; /* 0x210 */ + u32 pll1_ctr; /* 0x214 */ + u32 pll1_frq; /* 0x218 */ + u32 pll1_mod; /* 0x21c */ + u32 pll2_ctr; /* 0x220 */ + u32 pll2_frq; /* 0x224 */ + u32 pll2_mod; /* 0x228 */ + u32 pll3_ctr; /* 0x22c */ + u32 pll3_frq; /* 0x230 */ + u32 pll3_mod; /* 0x234 */ + u32 pll4_ctr; /* 0x238 */ + u32 pll4_frq; /* 0x23C */ + u32 pll4_mod; /* 0x240 */ + u32 perip_clk_cfg; /* 0x244 */ + u32 gmac_clk_cfg; /* 0x248 */ + u32 c3_clk_synt; /* 0x24c */ + u32 clcd_clk_synt; /* 0x250 */ + u32 uart_clk_synt; /* 0x254 */ + u32 gmac_clk_synt; /* 0x258 */ + u32 mcif_sd_clk_synt; /* 0x25c */ + u32 mcif_cfxd_clk_synt; /* 0x260 */ + u32 ras_clk_synt0; /* 0x264 */ + u32 ras_clk_synt1; /* 0x268 */ + u32 ras_clk_synt2; /* 0x26c */ + u32 ras_clk_synt3; /* 0x270 */ + u32 perip1_clk_enb; /* 0x274 */ + u32 perip2_clk_enb; /* 0x278 */ + u32 perip1_sw_rst; /* 0x27c */ + u32 perip2_sw_rst; /* 0x280 */ + u32 ras_clk_enb; /* 0x284 */ + u32 ras_sw_rst; /* 0x288 */ + u32 pll1_synt; /* 0x28c */ + u32 i2s_clk_cfg; /* 0x290 */ + u8 reserved_3[0x300 - 0x294]; + u32 dmac_hs_sel; /* 0x300 */ + u32 dmac_sel; /* 0x304 */ + u32 dmac_flow_sel; /* 0x308 */ + u32 dmac_dir_sel; /* 0x30c */ + u32 dmac_cfg; /* 0x310 */ + u32 usbphy_gen_cfg; /* 0x314 */ + u32 usbphy_p1_cfg; /* 0x318 */ + u32 usbphy_p2_cfg; /* 0x31c */ + u32 usbphy_p3_cfg; /* 0x320 */ + u32 pcie_cfg; /* 0x324 */ + u32 pcie_miphy_cfg; /* 0x328 */ + u32 perip_cfg; /* 0x32c */ + u32 fsmc_cfg; /* 0x330 */ + u32 mpmc_ctr_sts; /* 0x334 */ + u8 reserved_4[0x400 - 0x338]; + u32 expi_clk_cfg; /* 0x400 */ + u32 expi_cfg; /* 0x404 */ + u32 expi_dmachs_flex; /* 0x408 */ + u8 reserved_5[0x500 - 0x40C]; + u32 prc1_lock_ctr; /* 0x500 */ + u32 prc2_lock_ctr; /* 0x504 */ + u32 prc1_irq_ctr; /* 0x508 */ + u8 reserved_6[0x51c - 0x50c]; + u32 prc2_irq_ctr; /* 0x51c */ + u8 reserved_7[0x600 - 0x520]; + u32 pad_pu_cfg_1; /* 0x600 */ + u32 pad_pu_cfg_2; /* 0x604 */ + u32 pad_pu_cfg_3; /* 0x608 */ + u32 pad_pu_cfg_4; /* 0x60c */ + u32 pad_pu_cfg_5; /* 0x610 */ + u32 pad_pu_cfg_6; /* 0x614 */ + u32 pad_pu_cfg_7; /* 0x618 */ + u32 pad_pu_cfg_8; /* 0x61c */ + u32 pad_pd_cfg_1; /* 0x620 */ + u32 pad_pd_cfg_2; /* 0x624 */ + u32 pad_pd_cfg_3; /* 0x628 */ + u32 pad_pd_cfg_4; /* 0x62c */ + u32 pad_pd_cfg_5; /* 0x630 */ + u32 pad_pd_cfg_6; /* 0x634 */ + u32 pad_pd_cfg_7; /* 0x638 */ + u32 pad_pd_cfg_8; /* 0x63c */ + u32 pad_sleep_cfg; /* 0x640 */ + u32 pad_hyst_cfg; /* 0x644 */ + u32 pad_drv_cfg; /* 0x648 */ + u32 pad_slew_cfg; /* 0x64c */ + u32 pad_function_en_1; /* 0x650 */ + u32 pad_function_en_2; /* 0x654 */ + u32 pad_function_en_3; /* 0x658 */ + u32 ddr_pad_cfg; /* 0x65c */ + u8 reserved_8[0x6C4 - 0x660]; + u32 thsens_cfg; /* 0x6C4 */ + u8 reserved_9[0x700 - 0x6C8]; + u32 comp_1_cfg; /* 0x700 */ + u32 comp_2_cfg; /* 0x704 */ + u32 comp3v3_1_cfg; /* 0x708 */ + u32 comp3v3_2_cfg; /* 0x70c */ + u32 compddr_cfg; /* 0x710 */ + u8 reserved_10[0x800 - 0x714]; + u32 otp_prog_ctr; /* 0x800 */ + u32 otp_wdata1_1; /* 0x804 */ + u32 otp_wdata1_2; /* 0x808 */ + u32 otp_wdata1_3; /* 0x80c */ + u32 otp_wdata1_4; /* 0x810 */ + u32 otp_wdata1_5; /* 0x814 */ + u32 otp_wdata1_6; /* 0x818 */ + u32 otp_wdata1_7; /* 0x81c */ + u32 otp_wdata1_8; /* 0x820 */ + u32 otp_wdata2_1; /* 0x824 */ + u32 otp_wdata2_2; /* 0x828 */ + u32 otp_wdata2_3; /* 0x82c */ + u32 otp_wdata2_4; /* 0x830 */ + u32 otp_wdata2_5; /* 0x834 */ + u32 otp_wdata2_6; /* 0x838 */ + u32 otp_wdata2_7; /* 0x83c */ + u32 otp_wdata2_8; /* 0x840 */ + u32 otp_mask_1; /* 0x844 */ + u32 otp_mask_2; /* 0x848 */ + u32 otp_mask_3; /* 0x84c */ + u32 otp_mask_4; /* 0x850 */ + u32 otp_mask_5; /* 0x854 */ + u32 otp_mask_6; /* 0x858 */ + u32 otp_mask_7; /* 0x85c */ + u32 otp_mask_8; /* 0x860 */ + u32 otp_rdata1_1; /* 0x864 */ + u32 otp_rdata1_2; /* 0x868 */ + u32 otp_rdata1_3; /* 0x86c */ + u32 otp_rdata1_4; /* 0x870 */ + u32 otp_rdata1_5; /* 0x874 */ + u32 otp_rdata1_6; /* 0x878 */ + u32 otp_rdata1_7; /* 0x87c */ + u32 otp_rdata1_8; /* 0x880 */ + u32 otp_rdata2_1; /* 0x884 */ + u32 otp_rdata2_2; /* 0x888 */ + u32 otp_rdata2_3; /* 0x88c */ + u32 otp_rdata2_4; /* 0x890 */ + u32 otp_rdata2_5; /* 0x894 */ + u32 otp_rdata2_6; /* 0x898 */ + u32 otp_rdata2_7; /* 0x89c */ + u32 otp_rdata2_8; /* 0x8a0 */ + u32 otp_rdatam_1; /* 0x8a4 */ + u32 otp_rdatam_2; /* 0x8a8 */ + u32 otp_rdatam_3; /* 0x8ac */ + u32 otp_rdatam_4; /* 0x8b0 */ + u32 otp_rdatam_5; /* 0x8b4 */ + u32 otp_rdatam_6; /* 0x8b8 */ + u32 otp_rdatam_7; /* 0x8bc */ + u32 otp_rdatam_8; /* 0x8c0 */ + u8 reserved_11[0x900 - 0x8c4]; + u32 a9sm_clusterid; /* 0x900 */ + u32 a9sm_status; /* 0x904 */ + u32 a9sm_debug; /* 0x908 */ + u32 a9sm_filter; /* 0x90c */ + u32 a9sm_parity_cfg; /* 0x910 */ + u32 a9sm_parity_err; /* 0x914 */ + u8 reserved_12[0xa00 - 0x918]; + u32 die_id_1; /* 0xa00 */ + u32 die_id_2; /* 0xa04 */ + u32 die_id_3; /* 0xa08 */ + u32 die_id_4; /* 0xa0c */ + u32 die_id_valid; /* 0xa10 */ + u8 reserved_13[0xb00 - 0xa14]; + u32 ras1_gpp_inp; /* 0xb00 */ + u32 ras2_gpp_inp; /* 0xb04 */ + u32 ras1_gpp_out; /* 0xb08 */ + u32 ras2_gpp_out; /* 0xb0c */ + u8 reserved_14[0x1000 - 0xb10]; + u32 miphy_test; /* 0x1000 */ + u32 pcie_mstr_p1; /* 0x1004 */ + u32 pcie_awmisc_p1; /* 0x1008 */ + u32 pcie_armisc_p1; /* 0x100c */ + u32 pcie_mstr_p2; /* 0x1010 */ + u32 pcie_awmisc_p2; /* 0x1014 */ + u32 pcie_armisc_p2; /* 0x1018 */ + u32 pcie_mstr_p3; /* 0x101c */ + u32 pcie_awmisc_p3; /* 0x1020 */ + u32 pcie_armisc_p3; /* 0x1024 */ +}; + +/* sys_clk_ctrl definitions */ +#define SYS_MODE_MASK (7 << 0) +#define SYS_MODE_REQ_DOZE (1 << 0) +#define SYS_MODE_REQ_SLOW (2 << 0) +#define SYS_MODE_REQ_NORMAL (4 << 0) +#define PLL_TIMEOUT_ENB (1 << 3) +#define XTAL_TIMEOUT_ENB (1 << 4) +#define SYS_STATE_MASK (0xF << 16) +#define SYS_STATE_NORMAL (0xF << 16) + +/* sys_clk_*timer definitions */ +#define PLL_TIM (0xff << 3) +#define OSCI_TIM (0xff << 3) + +/* pll_freq definitions in MHz */ +#define FREQ_1000 (0xFA000106) +#define FREQ_996 (0x53000004) +#define FREQ_332 (0x53000203) + +/* pll_ctr definitions */ +#define PLLLOCK (1 << 0) +#define PLLENABLE (1 << 1) + +/* perip_clk_cfg definitions */ +#define MPMC_CLK_PLL4 (1 << 10) + +/* perip*_[clk_enb/sw_rst] definitions */ +#define BUS_CLKEN (1 << 0) /* perip1 */ +#define SYSROM_CLKEN (1 << 1) +#define AORAM_CLKEN (1 << 2) +#define SYSRAM_CLKEN (1 << 3) +#define FSMC_CLKEN (1 << 4) +#define SMI_CLKEN (1 << 5) +#define SD_CLKEN (1 << 6) +#define CFXD_CLKEN (1 << 7) +#define GETH_CLKEN (1 << 8) +#define UHC1_CLKEN (1 << 9) +#define UHC2_CLKEN (1 << 10) +#define UDC_UPD_CLKEN (1 << 11) +#define PCI1_CLKEN (1 << 12) +#define PCI2_CLKEN (1 << 13) +#define PCI3_CLKEN (1 << 14) +#define UART_CLKEN (1 << 15) +#define SSP_CLKEN (1 << 17) +#define I2C_CLKEN (1 << 18) +#define I2S_SLV_CLKEN (1 << 19) +#define I2S_MST_CLKEN (1 << 20) +#define GPT1_CLKEN (1 << 21) +#define GPT2_CLKEN (1 << 22) +#define GPIO1_CLKEN (1 << 23) +#define GPIO2_CLKEN (1 << 24) +#define DMA1_CLKEN (1 << 25) +#define DMA2_CLKEN (1 << 26) +#define CLCD_CLKEN (1 << 27) +#define JPEG_CLKEN (1 << 28) +#define C3_CLKEN (1 << 29) +#define ADC_CLKEN (1 << 30) +#define RTC_CLKEN (1 << 31) + +#define DDR_CTRL_CLKEN (1 << 0) /* perip2 */ +#define DDR_CORE_CLKEN (1 << 1) +#define CPU_DBG_CLKEN (1 << 2) +#define KBD_CLKEN (1 << 3) +#define GPT3_CLKEN (1 << 4) +#define GPT4_CLKEN (1 << 5) +#define ACP_CLKEN (1 << 6) +#define I2S_REFOUT_CLKEN (1 << 7) +#define THSENS_CLKEN (1 << 8) + +/* fsmc_cfg definitions */ +#define DEV_SEL_NOR (0 << 0) +#define DEV_SEL_NAND (1 << 0) +#define DEV_SEL_SRAM (2 << 0) +#define DEV_SEL_MSK (3 << 0) +#define NAND_BANK_0 (0 << 2) +#define NAND_BANK_1 (1 << 2) +#define NAND_BANK_2 (2 << 2) +#define NAND_BANK_3 (3 << 2) +#define DEV_WIDTH_8 (0 << 4) +#define DEV_WIDTH_16 (1 << 4) + +/* usbphy_gen_cfg definitions */ +#define COMMON_PWDN (1 << 0) +#define USBPHY_POR (1 << 12) +#define USBPHY_RST (1 << 13) +#define UTMI_XFER_RST0 (1 << 14) +#define UTMI_XFER_RST1 (1 << 15) +#define UTMI_XFER_RST2 (1 << 16) +#define USB_PLL_LOCK (1 << 27) + +/* synth registers definitions */ +#define SYNT_CLK_ENB (1 << 31) +#define SYNT_FIN_FULL (1 << 30) +#define SYNT_X_1 (1 << 16) +#define SYNT_Y_2 (2 << 0) +#define SYNT_Y_5 (5 << 0) + +/* gmac_clk_cfg definitions */ +#define PHY_IF_GMII (0 << 4) +#define PHY_IF_RGMII (1 << 4) +#define PHY_IF_RMII (4 << 4) +#define GMII_SYNT_ENB (1 << 3) +#define CLK_SEL_PAD (0 << 0) +#define CLK_SEL_PLL2 (1 << 0) +#define CLK_SEL_OSCI3 (2 << 0) + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/sys_proto.h b/arch/arm/include/asm/arch-spear13xx/sys_proto.h new file mode 100644 index 0000000..e6cc3a9 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/sys_proto.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_device_type(void); +void invalidate_dcache(u32); +void l2_cache_disable(void); +void l2_cache_enable(void); + +#endif

spear3xx and 6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. console on usb device 3. console on usb device with environment placed in NAND

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- Makefile | 16 ++++++++++++++-- board/spear/spear300/config.mk | 11 ----------- board/spear/spear310/config.mk | 11 ----------- board/spear/spear320/config.mk | 11 ----------- board/spear/spear600/config.mk | 11 ----------- include/configs/spear3xx.h | 10 ++++++++++ include/configs/spear6xx.h | 10 ++++++++++ 7 files changed, 34 insertions(+), 46 deletions(-)

diff --git a/Makefile b/Makefile index 0b6a151..4cc9913 100644 --- a/Makefile +++ b/Makefile @@ -3034,11 +3034,23 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

spear300_config \ +spear300_nand_config \ +spear300_usbtty_config \ +spear300_usbtty_nand_config \ spear310_config \ -spear320_config : unconfig +spear310_nand_config \ +spear310_usbtty_config \ +spear310_usbtty_nand_config \ +spear320_config \ +spear320_nand_config \ +spear320_usbtty_config \ +spear320_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear

-spear600_config : unconfig +spear600_config \ +spear600_nand_config \ +spear600_usbtty_config \ +spear600_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear

spear1300_config \ diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear300/config.mk +++ b/board/spear/spear300/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear310/config.mk +++ b/board/spear/spear310/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear320/config.mk +++ b/board/spear/spear320/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear600/config.mk +++ b/board/spear/spear600/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index fde505c..f0c915e 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -39,6 +39,16 @@ #define CONFIG_SPEAR320 1 #endif

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h>

/* Ethernet driver configuration */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2532344..82d24df 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -30,6 +30,16 @@ */ #define CONFIG_SPEAR600 1

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h>

/* Serial Configuration (PL011) */

On 5/3/2010 6:08 AM, Tom Rix wrote:

Vipin KUMAR wrote:

...

spear3xx and 6xx boards can be compiled in following configurations

1. Environment placed in NAND
2. console on usb device
3. console on usb device with environment placed in NAND

Add the new configs to the README.spear Tom

OK. Would be done in patch v3

...

Signed-off-by: Vipin Kumar vipin.kumar@st.com

Makefile | 16 ++++++++++++++-- board/spear/spear300/config.mk | 11 ----------- board/spear/spear310/config.mk | 11 ----------- board/spear/spear320/config.mk | 11 ----------- board/spear/spear600/config.mk | 11 ----------- include/configs/spear3xx.h | 10 ++++++++++ include/configs/spear6xx.h | 10 ++++++++++ 7 files changed, 34 insertions(+), 46 deletions(-)

diff --git a/Makefile b/Makefile index 0b6a151..4cc9913 100644 --- a/Makefile +++ b/Makefile @@ -3034,11 +3034,23 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

spear300_config \ +spear300_nand_config \ +spear300_usbtty_config \ +spear300_usbtty_nand_config \ spear310_config \ -spear320_config : unconfig +spear310_nand_config \ +spear310_usbtty_config \ +spear310_usbtty_nand_config \ +spear320_config \ +spear320_nand_config \ +spear320_usbtty_config \ +spear320_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear

-spear600_config : unconfig +spear600_config \ +spear600_nand_config \ +spear600_usbtty_config \ +spear600_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear

spear1300_config \ diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear300/config.mk +++ b/board/spear/spear300/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif

-ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear310/config.mk +++ b/board/spear/spear310/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif

# Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif

-ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear320/config.mk +++ b/board/spear/spear320/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif

# Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif

-ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear600/config.mk +++ b/board/spear/spear600/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif

-ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index fde505c..f0c915e 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -39,6 +39,16 @@ #define CONFIG_SPEAR320 1 #endif

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif

+#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif

#include <configs/spear-common.h>

/* Ethernet driver configuration */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2532344..82d24df 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -30,6 +30,16 @@ */ #define CONFIG_SPEAR600 1

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif

+#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif

#include <configs/spear-common.h>

/* Serial Configuration (PL011) */

On 5/3/2010 6:07 AM, Tom Rix wrote:

Vipin KUMAR wrote:

...

SPEAr1300 SoC support contains basic spear1300 support along with the usage of following drivers

• serial driver(UART)
• i2c driver
• smi driver
• nand driver(FSMC)
• usbd driver

Signed-off-by: Vipin Kumar vipin.kumar@st.com

Makefile | 6 +

Need MAINTAINERS MAKEALL

OK. Would be done in patch v3

...

arch/arm/include/asm/arch-spear13xx/hardware.h | 8 +- board/spear/common/Makefile | 10 +- board/spear/spear1300/Makefile | 51 ++++++ board/spear/spear1300/config.mk | 28 ++++ board/spear/spear1300/spear1300.c | 86 ++++++++++ board/spear/spear1300/spr_lowlevel_init.S | 38 +++++ include/configs/spear13xx.h | 199 ++++++++++++++++++++++++ 8 files changed, 420 insertions(+), 6 deletions(-) create mode 100644 board/spear/spear1300/Makefile create mode 100644 board/spear/spear1300/config.mk create mode 100644 board/spear/spear1300/spear1300.c create mode 100644 board/spear/spear1300/spr_lowlevel_init.S create mode 100644 include/configs/spear13xx.h

diff --git a/Makefile b/Makefile index 7bfdfd3..0b6a151 100644 --- a/Makefile +++ b/Makefile @@ -3041,6 +3041,12 @@ spear320_config : unconfig spear600_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear

+spear1300_config \ +spear1300_nand_config \ +spear1300_usbtty_config \ +spear1300_usbtty_nand_config : unconfig

• @$(MKCONFIG) -n $@ -t $(@:_config=) spear13xx arm arm_cortexa8

spear1300 spear spear13xx

suen3_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood

diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h index 384260a..7a1cedb 100644 --- a/arch/arm/include/asm/arch-spear13xx/hardware.h +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -24,10 +24,10 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H

-#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SYS_USBD_BASE (0xE3800000) +#define CONFIG_SYS_PLUG_BASE (0xE2800000) +#define CONFIG_SYS_FIFO_BASE (0xE3000800) +#define CONFIG_SYS_SMI_BASE (0xEA000000) #define CONFIG_SPEAR_TIMERBASE (0xE0380000) #define CONFIG_SPEAR_MISCBASE (0xE0700000) #define CONFIG_SYS_I2C_BASE (0xE0280000) diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 4f8959f..1ae4fd4 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,14 @@ endif

LIB = $(obj)lib$(VENDOR).a

-COBJS := spr_misc.o -SOBJS := spr_lowlevel_init.o +COBJS-$(CONFIG_SPEAR3XX) += spr_misc.o +COBJS-$(CONFIG_SPEAR600) += spr_misc.o

+SOBJS-$(CONFIG_SPEAR3XX) += spr_lowlevel_init.o +SOBJS-$(CONFIG_SPEAR600) += spr_lowlevel_init.o

+COBJS := $(COBJS-y) +SOBJS := $(SOBJS-y)

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/spear1300/Makefile b/board/spear/spear1300/Makefile new file mode 100644 index 0000000..fb66895 --- /dev/null +++ b/board/spear/spear1300/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(BOARD).a

+COBJS := spear1300.o +SOBJS := spr_lowlevel_init.o

+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))

+$(LIB): $(obj).depend $(OBJS) $(SOBJS)

• $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

+clean:

• rm -f $(SOBJS) $(OBJS)

+distclean: clean

• rm -f $(LIB) core *.bak $(obj).depend

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+#########################################################################

diff --git a/board/spear/spear1300/config.mk b/board/spear/spear1300/config.mk new file mode 100644 index 0000000..0bbb40f --- /dev/null +++ b/board/spear/spear1300/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+#########################################################################

+TEXT_BASE = 0x00700000

+ALL += $(obj)u-boot.img diff --git a/board/spear/spear1300/spear1300.c b/board/spear/spear1300/spear1300.c new file mode 100644 index 0000000..89ddc9c --- /dev/null +++ b/board/spear/spear1300/spear1300.c @@ -0,0 +1,86 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <netdev.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h>

+DECLARE_GLOBAL_DATA_PTR;

+int board_init(void) +{

• gd->bd->bi_arch_number = MACH_TYPE_SPEAR1300;
• gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
• return 0;

+}

+int dram_init(void) +{

• gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
• gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1,

•                       PHYS_SDRAM_1_MAXSIZE);
  

• return 0;

+}

+int misc_init_r(void) +{

• setenv("verify", "n");

+#if defined(CONFIG_SPEAR_USBTTY)

• setenv("stdin", "usbtty");
• setenv("stdout", "usbtty");
• setenv("stderr", "usbtty");

+#endif

• return 0;

+}

+/*

• • board_nand_init - Board specific NAND initialization
• • @nand: mtd private chip structure
• • Called by nand_init_chip to initialize the board specific functions
• */

+int board_nand_init(struct nand_chip *nand) +{ +#if defined(CONFIG_NAND_FSMC)

• return fsmc_nand_init(nand);

+#endif

Broken if CONFIG_NAND_FSMC is not set.

OK. Adding a return -1 in case CONFIG_NAND_FSMC is not defined

...

+}

+#if defined(CONFIG_CMD_NET) +int board_eth_init(bd_t *bis) +{

• /*

• * Board specific ethernet initialization comes here. eg. gmac clock
  

• * configuration etc
  

• */
  

• return designware_initialize(0, CONFIG_SPEAR_ETHBASE);

+} +#endif diff --git a/board/spear/spear1300/spr_lowlevel_init.S b/board/spear/spear1300/spr_lowlevel_init.S new file mode 100644 index 0000000..ba93922 --- /dev/null +++ b/board/spear/spear1300/spr_lowlevel_init.S @@ -0,0 +1,38 @@ +/*

• • (C) Copyright 2006
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <config.h>

+/*

• • platform specific initializations are already done in Xloader
• • Initializations already done include
• • DDR, PLLs, IP's clock enable and reset release etc
• */

+.globl lowlevel_init +lowlevel_init:

• /* By default, U-Boot switches CPU to low-vector */
• /* Revert this as we work in high vector even in U-Boot */
• mrc p15, 0, r0, c1, c0, 0
• orr r0, r0, #0x00002000
• mcr p15, 0, r0, c1, c0, 0
• mov pc, lr

diff --git a/include/configs/spear13xx.h b/include/configs/spear13xx.h new file mode 100644 index 0000000..3880e0a --- /dev/null +++ b/include/configs/spear13xx.h @@ -0,0 +1,199 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, STMicroelectronics, vipin.kumar@st.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __CONFIG_H +#define __CONFIG_H

+#if defined(CONFIG_MK_spear1300) +#define CONFIG_SPEAR13XX 1 +#define CONFIG_SPEAR1300 1 +#endif

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif

+#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif

+/* Ethernet configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR 1 +#define CONFIG_PHY_RESET_DELAY (10000) /* in usec */

+/* USBD driver configuration */ +#define CONFIG_DW_UDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY

+#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"

+#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"

Should be conditional on CONFIG_SPEAR_USBTTY Similar changes for spear3xx and spear6xxx

CONFIG_SPEAR_USBTTY is a special case where tty over usb terminal is used for downloading and flashing images. usbtty environment variable should normally also be set as cdc_acm to make sure that we can switch to tty over usb terminal directly from uboot prompt by simply running setenv stdout usbtty; setenv stdin usbtty

So, I am not making it conditional to CONFIG_EXTRA_ENV_USBTTY

...

+/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ (1000)

+/* Flash configuration */ +#define CONFIG_ST_SMI 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xE6000000) +#define CONFIG_SYS_CS1_FLASH_BASE (0xE7000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \

•                    CONFIG_SYS_CS1_FLASH_BASE}
  

+#define CONFIG_SYS_MAX_FLASH_SECT 128

+#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)

+/*

• • Serial Configuration (PL011)
• */

+#define CONFIG_PL011_SERIAL +#define CONFIG_SYS_SERIAL0 0xE0000000 +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \

•                    57600, 115200 }
  

+#define CONFIG_SYS_LOADS_BAUD_CHANGE +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}

+/*

• • NAND FLASH Configuration
• */

+#define CONFIG_NAND_FSMC 1 +#define CONFIG_SYS_FSMC_NAND_LP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_NAND_BASE (0xA0000000)

+/*

• • Command support defines
• */

+#define CONFIG_CMD_NAND +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP

+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h>

+/*

• • Default Environment Varible definitions
• */

+#if defined(CONFIG_SPEAR_USBTTY) +#define CONFIG_BOOTDELAY -1

Add comment that this disables autoboot

OK. Would be done in patch v3

Tom

...

+#else +#define CONFIG_BOOTDELAY 1 +#endif

+/*

• • Environment placing
• */

+#if defined(CONFIG_ENV_IS_IN_FLASH) +/*

• • Environment is in serial NOR flash
• */

+#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_FSMTDBLK "/dev/mtdblock8 "

+#define CONFIG_BOOTCOMMAND "bootm 0xe6050000"

+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \

•                    CONFIG_SYS_MONITOR_LEN)
  

+#elif defined(CONFIG_ENV_IS_IN_NAND) +/*

• • Environment is in NAND
• */

+#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_RANGE 0x10000 +#define CONFIG_FSMTDBLK "/dev/mtdblock12 "

+#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \

•                    "0x80000 0x4C0000; " \
  

•                    "bootm 0x1600000"
  

+#endif

+#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \

•                    "console=ttyAMA0 init=/bin/sh"
  

+#define CONFIG_BOOTARGS "console=ttyAMA0 mem=128M " \

•                    "root="CONFIG_FSMTDBLK \
  

•                    "rootfstype=jffs2"
  

+#define CONFIG_ENV_SIZE 0x02000

+/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1

+#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \

•    "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
  

+#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \

•                    sizeof(CONFIG_SYS_PROMPT) + 16)
  

+#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1

+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY

+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000

+#endif

On 5/3/2010 6:03 AM, Tom Rix wrote:

Expand the commit log to describe this new part. Include a URL reference to where it can be reviewed.

OK would be done in patch v3

Vipin KUMAR wrote:

...

Signed-off-by: Vipin Kumar vipin.kumar@st.com

arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 112 ++++++++ arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 99 +++++++ arch/arm/cpu/arm_cortexa8/spear13xx/reset.c | 47 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 136 ++++++++++ arch/arm/include/asm/arch-spear13xx/hardware.h | 40 +++ arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++++ arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 +++++++++++++++++++++++ arch/arm/include/asm/arch-spear13xx/sys_proto.h | 32 +++ 9 files changed, 920 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c create mode 100755 arch/arm/cpu/arm_cortexa8/spear13xx/reset.c create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/sys_proto.h

diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile new file mode 100644 index 0000000..4157164 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(SOC).a

+COBJS += timer.o +COBJS += reset.o +COBJS += cpu.o

+SOBJS = cache.o

+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

+all: $(obj).depend $(LIB)

+$(LIB): $(OBJS)

• $(AR) $(ARFLAGS) $@ $(OBJS)

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+#########################################################################

diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S new file mode 100644 index 0000000..b3d1fb0 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S @@ -0,0 +1,112 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.

This cache.S is extremely similar to s5pc1xx/cache.S And to a lesser degree the omap3/cache.S. When a work is based on another work, the original work MUST be acknowledged.

Sure. Would be done in v3 patch

Ideally, this is effectively cpu specific code. Cortex-A9 needs data cache invalidation before enabling data cache. Ideally, this common code should be moved to a generic cache.S within arch/arm/cpu/cortexa8/ Please comment more

...

• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+.global invalidate_dcache

+/*

• • invalidate_dcache()
• • Invalidate the whole D-cache.
• • Corrupted registers: r0-r5, r7, r9-r11
• • • mm - mm_struct describing address space
• */

+invalidate_dcache:

• stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
• mrc p15, 1, r0, c0, c0, 1 @ read clidr
• ands r3, r0, #0x7000000 @ extract loc from clidr
• mov r3, r3, lsr #23 @ left align loc bit field
• beq finished_inval @ if loc is 0, then no need to

•                    @ clean
  

• mov r10, #0 @ start clean at cache level 0

+inval_loop1:

• add r2, r10, r10, lsr #1 @ work out 3x current cache

•                    @ level
  

• mov r1, r0, lsr r2 @ extract cache type bits from

•                    @ clidr
  

• and r1, r1, #7 @ mask of the bits for current

•                    @ cache only
  

• cmp r1, #2 @ see what cache we have at

•                    @ this level
  

• blt skip_inval @ skip if no cache, or just

•                    @ i-cache
  

• mcr p15, 2, r10, c0, c0, 0 @ select current cache level

•                    @ in cssr
  

• mov r2, #0 @ operand for mcr SBZ
• mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to

•                    @ sych the new cssr&csidr,
  

•                    @ with armv7 this is 'isb',
  

•                    @ but we compile with armv5
  

• mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
• and r2, r1, #7 @ extract the length of the

•                    @ cache lines
  

• add r2, r2, #4 @ add 4 (line length offset)
• ldr r4, =0x3ff
• ands r4, r4, r1, lsr #3 @ find maximum number on the

•                    @ way size
  

• clz r5, r4 @ find bit position of way

•                    @ size increment
  

• ldr r7, =0x7fff
• ands r7, r7, r1, lsr #13 @ extract max number of the

•                    @ index size
  

+inval_loop2:

• mov r9, r4 @ create working copy of max

•                    @ way size
  

+inval_loop3:

• orr r11, r10, r9, lsl r5 @ factor way and cache number

•                    @ into r11
  

• orr r11, r11, r7, lsl r2 @ factor index number into r11
• mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
• subs r9, r9, #1 @ decrement the way
• bge inval_loop3
• subs r7, r7, #1 @ decrement the index
• bge inval_loop2

+skip_inval:

• add r10, r10, #2 @ increment cache number
• cmp r3, r10
• bgt inval_loop1

+finished_inval:

• mov r10, #0 @ swith back to cache level 0
• mcr p15, 2, r10, c0, c0, 0 @ select current cache level

•                    @ in cssr
  

• mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,

•                    @ with armv7 this is 'isb',
  

•                    @ but we compile with armv5
  

• ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}

+.global l2_cache_enable +/*

• • l2_cache_enable
• */

+l2_cache_enable:

• bx r14

+.global l2_cache_disable +/*

• • l2_cache_disable
• */

+l2_cache_disable:

• bx r14

diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c new file mode 100644 index 0000000..5a0ae56 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c @@ -0,0 +1,99 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h>

+u32 get_device_type(void) +{

• return 0;

+}

This is needed for omap3. Remove

Actually, a genric file arch/arm/arm_cortexa8/cpu.c calls a function in the following way. invalidate_dcache(get_device_type()); This forces each platform using cpu code for arm_cortexa8 to define get_device_type(). Should I change the generic file as well ?

...

+#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{

• struct misc_regs *const misc_p =

•    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  

• u32 perip1_clk_enb, perip2_clk_enb;

+#if defined(CONFIG_NAND_FSMC)

• u32 fsmc_cfg;

+#endif

• perip1_clk_enb = readl(&misc_p->perip1_clk_enb);
• perip2_clk_enb = readl(&misc_p->perip2_clk_enb);
• perip1_clk_enb |= GPT1_CLKEN;

+#if defined(CONFIG_PL011_SERIAL)

• perip1_clk_enb |= UART_CLKEN;

+#endif

+#if defined(CONFIG_DESIGNWARE_ETH)

• /* writel(SYNT_CLK_ENB | SYNT_FIN_FULL | SYNT_X_1 | SYNT_Y_5,

•        &misc_p->gmac_clk_synt); */
  

This is dead code Remove.

OK

...

• writel(PHY_IF_GMII | CLK_SEL_OSCI3, &misc_p->gmac_clk_cfg);
• perip1_clk_enb |= GETH_CLKEN;

+#endif

+#if defined(CONFIG_DW_UDC)

• perip1_clk_enb |= UDC_UPD_CLKEN;

+#endif

+#if defined(CONFIG_DW_I2C)

• perip1_clk_enb |= I2C_CLKEN;

+#endif

+#if defined(CONFIG_ST_SMI)

• perip1_clk_enb |= SMI_CLKEN;

+#endif

+#if defined(CONFIG_NAND_FSMC)

• fsmc_cfg = readl(&misc_p->fsmc_cfg);
• fsmc_cfg &= ~DEV_SEL_MSK;
• fsmc_cfg |= DEV_SEL_NAND;

+#if defined(CONFIG_BOARD_NAND_16BIT)

• fsmc_cfg |= DEV_WIDTH_16;

Similar 16BIT is never defined. Remove dead code

These can be defined in the board configuration file and recompiled to support NAND 16 bit devices. The idea is to define either one of CONFIG_BOARD_NAND_8BIT or CONFIG_BOARD_NAND_16BIT to support the NAND device

...

+#elif defined(CONFIG_BOARD_NAND_8BIT)

• fsmc_cfg |= DEV_WIDTH_8;

+#endif

• writel(fsmc_cfg, &misc_p->fsmc_cfg);
• perip1_clk_enb |= FSMC_CLKEN;

+#endif

• writel(perip1_clk_enb, &misc_p->perip1_clk_enb);
• writel(perip2_clk_enb, &misc_p->perip2_clk_enb);
• return 0;

+} +#endif

+#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{

• printf("CPU: SPEAr1300\n");
• return 0;

+} +#endif diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c new file mode 100755 index 0000000..9a43f85 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c @@ -0,0 +1,47 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h>

+void reset_cpu(ulong ignored) +{

• struct misc_regs *misc_regs_p =

•    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  

• printf("System is going to reboot ...\n");
• /*

• * This 1 second delay will allow the above message
  

• * to be printed before reset
  

• */
  

• udelay((1000 * 1000));
• writel(0x01, &misc_regs_p->sys_sw_res);
• /* system will restart */
• while (1)

•    ;
  

+} diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c new file mode 100644 index 0000000..d114a4a --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c @@ -0,0 +1,136 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.

Looks like this was based on ../arm926ejs/spear/timer.c Please state this even if you are the author of both

OK.

...

• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_gpt.h> +#include <asm/arch/spr_misc.h>

+#define GPT_TICKS (CONFIG_SPEAR_HZ_CLOCK / (1 << prescaler)) +#define GPT_RESOLUTION (GPT_TICKS / CONFIG_SPEAR_HZ) +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)

+static struct gpt_regs *const gpt_regs_p =

• (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;

+static ulong timestamp; +static ulong lastdec; +static const u32 prescaler = GPT_PRESCALER_16;

+int timer_init(void) +{

• /* disable timers */
• writel(prescaler | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
• /* load value for free running */
• writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
• /* auto reload, start timer */
• writel(readl(&gpt_regs_p->control) | GPT_ENABLE,

&gpt_regs_p->control);

• reset_timer_masked();
• return 0;

+}

+/*

• • timer without interrupts
• */

+void reset_timer(void) +{

• reset_timer_masked();

+}

+ulong get_timer(ulong base) +{

• return (get_timer_masked() / GPT_RESOLUTION) - base;

+}

+void set_timer(ulong t) +{

• timestamp = t;

+}

+void __udelay(unsigned long usec) +{

• ulong tmo;
• ulong start = get_timer_masked();
• ulong tenudelcnt = GPT_TICKS / (1000 * 100);

Expand this variable name so it means something. This is a concatenation of abbreviations

OK. I would use ticks_in_ten_us in v3 patch

May consider using unsigned long long if exceeding 32 bits

...

• ulong rndoff;
• rndoff = (usec % 10) ? 1 : 0;
• /* tenudelcnt timer tick gives 10 microsecconds delay */
• tmo = ((usec / 10) + rndoff) * tenudelcnt;
• while ((ulong) (get_timer_masked() - start) < tmo)

•    ;
  

+}

+void reset_timer_masked(void) +{

• /* reset time */
• lastdec = READ_TIMER();
• timestamp = 0;

+}

+ulong get_timer_masked(void) +{

• ulong now = READ_TIMER();
• if (now >= lastdec) {

•    /* normal mode */
  

•    timestamp += now - lastdec;
  

• } else {

•    /* we have an overflow ... */
  

•    timestamp += now + GPT_FREE_RUNNING - lastdec;
  

• }
• lastdec = now;
• return timestamp;

+}

+void udelay_masked(unsigned long usec) +{

• return udelay(usec);

+}

+/*

• • This function is derived from PowerPC code (read timebase as long

long).

• • On ARM it just returns the timer value.
• */

+unsigned long long get_ticks(void) +{

• return get_timer(0);

+}

+/*

• • This function is derived from PowerPC code (timebase clock

frequency).

• • On ARM it returns the number of timer ticks per second.
• */

+ulong get_tbclk(void) +{

• return CONFIG_SPEAR_HZ;

+} diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h new file mode 100644 index 0000000..384260a --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -0,0 +1,40 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, STMicroelectronics, vipin.kumar@st.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H

Change this to something non generic with SPEAR13XX in it somewhere.

OK

...

+#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SPEAR_TIMERBASE (0xE0380000) +#define CONFIG_SPEAR_MISCBASE (0xE0700000) +#define CONFIG_SYS_I2C_BASE (0xE0280000) +#define CONFIG_SPEAR_ETHBASE (0xE2000000) +#define CONFIG_SYS_FSMC_BASE (0xB0000000)

+#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17)

+#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/spr_gpt.h b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h new file mode 100644 index 0000000..ad464cb --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h @@ -0,0 +1,85 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef _SPR_GPT_H +#define _SPR_GPT_H

+struct gpt_regs {

• u8 reserved[0x80];
• u32 control;
• u32 status;
• u32 compare;
• u32 count;
• u32 capture_re;
• u32 capture_fe;

+};

+/*

• • TIMER_CONTROL register settings
• */

+#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008

+#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000

+#define GPT_ENABLE 0x0020

+#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0

+#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400

+/*

• • TIMER_STATUS register settings
• */

+#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004

+/*

• • TIMER_COMPARE register settings
• */

+#define GPT_FREE_RUNNING 0xFFFF

+/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ (1000) +#define CONFIG_SPEAR_HZ_CLOCK (24000000)

+#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spr_misc.h b/arch/arm/include/asm/arch-spear13xx/spr_misc.h new file mode 100644 index 0000000..0b24843 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_misc.h @@ -0,0 +1,317 @@ +/*

• • (C) Copyright 2000-2009
• • Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __SPR13XX_MISC_H +#define __SPR13XX_MISC_H

+struct misc_regs {

• u32 soc_cfg; /* 0x000 */
• u32 bootstrap_cfg; /* 0x004 */
• u8 reserved_1[0x100 - 0x8];
• u32 pcm_cfg; /* 0x100 */
• u32 pcm_wkup_cfg; /* 0x104 */
• u32 switch_ctr; /* 0x108 */
• u8 reserved_2[0x200 - 0x10c];
• u32 sys_clk_ctrl; /* 0x200 */
• u32 sys_sw_res; /* 0x204 */
• u32 sys_clk_plltimer; /* 0x208 */
• u32 sys_clk_oscitimer; /* 0x20c */
• u32 pll_cfg; /* 0x210 */
• u32 pll1_ctr; /* 0x214 */
• u32 pll1_frq; /* 0x218 */
• u32 pll1_mod; /* 0x21c */
• u32 pll2_ctr; /* 0x220 */
• u32 pll2_frq; /* 0x224 */
• u32 pll2_mod; /* 0x228 */
• u32 pll3_ctr; /* 0x22c */
• u32 pll3_frq; /* 0x230 */
• u32 pll3_mod; /* 0x234 */
• u32 pll4_ctr; /* 0x238 */
• u32 pll4_frq; /* 0x23C */
• u32 pll4_mod; /* 0x240 */
• u32 perip_clk_cfg; /* 0x244 */
• u32 gmac_clk_cfg; /* 0x248 */
• u32 c3_clk_synt; /* 0x24c */
• u32 clcd_clk_synt; /* 0x250 */
• u32 uart_clk_synt; /* 0x254 */
• u32 gmac_clk_synt; /* 0x258 */
• u32 mcif_sd_clk_synt; /* 0x25c */
• u32 mcif_cfxd_clk_synt; /* 0x260 */
• u32 ras_clk_synt0; /* 0x264 */
• u32 ras_clk_synt1; /* 0x268 */
• u32 ras_clk_synt2; /* 0x26c */
• u32 ras_clk_synt3; /* 0x270 */
• u32 perip1_clk_enb; /* 0x274 */
• u32 perip2_clk_enb; /* 0x278 */
• u32 perip1_sw_rst; /* 0x27c */
• u32 perip2_sw_rst; /* 0x280 */
• u32 ras_clk_enb; /* 0x284 */
• u32 ras_sw_rst; /* 0x288 */
• u32 pll1_synt; /* 0x28c */
• u32 i2s_clk_cfg; /* 0x290 */
• u8 reserved_3[0x300 - 0x294];
• u32 dmac_hs_sel; /* 0x300 */
• u32 dmac_sel; /* 0x304 */
• u32 dmac_flow_sel; /* 0x308 */
• u32 dmac_dir_sel; /* 0x30c */
• u32 dmac_cfg; /* 0x310 */
• u32 usbphy_gen_cfg; /* 0x314 */
• u32 usbphy_p1_cfg; /* 0x318 */
• u32 usbphy_p2_cfg; /* 0x31c */
• u32 usbphy_p3_cfg; /* 0x320 */
• u32 pcie_cfg; /* 0x324 */
• u32 pcie_miphy_cfg; /* 0x328 */
• u32 perip_cfg; /* 0x32c */
• u32 fsmc_cfg; /* 0x330 */
• u32 mpmc_ctr_sts; /* 0x334 */
• u8 reserved_4[0x400 - 0x338];
• u32 expi_clk_cfg; /* 0x400 */
• u32 expi_cfg; /* 0x404 */
• u32 expi_dmachs_flex; /* 0x408 */
• u8 reserved_5[0x500 - 0x40C];
• u32 prc1_lock_ctr; /* 0x500 */
• u32 prc2_lock_ctr; /* 0x504 */
• u32 prc1_irq_ctr; /* 0x508 */
• u8 reserved_6[0x51c - 0x50c];
• u32 prc2_irq_ctr; /* 0x51c */
• u8 reserved_7[0x600 - 0x520];
• u32 pad_pu_cfg_1; /* 0x600 */
• u32 pad_pu_cfg_2; /* 0x604 */
• u32 pad_pu_cfg_3; /* 0x608 */
• u32 pad_pu_cfg_4; /* 0x60c */
• u32 pad_pu_cfg_5; /* 0x610 */
• u32 pad_pu_cfg_6; /* 0x614 */
• u32 pad_pu_cfg_7; /* 0x618 */
• u32 pad_pu_cfg_8; /* 0x61c */
• u32 pad_pd_cfg_1; /* 0x620 */
• u32 pad_pd_cfg_2; /* 0x624 */
• u32 pad_pd_cfg_3; /* 0x628 */
• u32 pad_pd_cfg_4; /* 0x62c */
• u32 pad_pd_cfg_5; /* 0x630 */
• u32 pad_pd_cfg_6; /* 0x634 */
• u32 pad_pd_cfg_7; /* 0x638 */
• u32 pad_pd_cfg_8; /* 0x63c */
• u32 pad_sleep_cfg; /* 0x640 */
• u32 pad_hyst_cfg; /* 0x644 */
• u32 pad_drv_cfg; /* 0x648 */
• u32 pad_slew_cfg; /* 0x64c */
• u32 pad_function_en_1; /* 0x650 */
• u32 pad_function_en_2; /* 0x654 */
• u32 pad_function_en_3; /* 0x658 */
• u32 ddr_pad_cfg; /* 0x65c */
• u8 reserved_8[0x6C4 - 0x660];
• u32 thsens_cfg; /* 0x6C4 */
• u8 reserved_9[0x700 - 0x6C8];
• u32 comp_1_cfg; /* 0x700 */
• u32 comp_2_cfg; /* 0x704 */
• u32 comp3v3_1_cfg; /* 0x708 */
• u32 comp3v3_2_cfg; /* 0x70c */
• u32 compddr_cfg; /* 0x710 */
• u8 reserved_10[0x800 - 0x714];
• u32 otp_prog_ctr; /* 0x800 */
• u32 otp_wdata1_1; /* 0x804 */
• u32 otp_wdata1_2; /* 0x808 */
• u32 otp_wdata1_3; /* 0x80c */
• u32 otp_wdata1_4; /* 0x810 */
• u32 otp_wdata1_5; /* 0x814 */
• u32 otp_wdata1_6; /* 0x818 */
• u32 otp_wdata1_7; /* 0x81c */
• u32 otp_wdata1_8; /* 0x820 */
• u32 otp_wdata2_1; /* 0x824 */
• u32 otp_wdata2_2; /* 0x828 */
• u32 otp_wdata2_3; /* 0x82c */
• u32 otp_wdata2_4; /* 0x830 */
• u32 otp_wdata2_5; /* 0x834 */
• u32 otp_wdata2_6; /* 0x838 */
• u32 otp_wdata2_7; /* 0x83c */
• u32 otp_wdata2_8; /* 0x840 */
• u32 otp_mask_1; /* 0x844 */
• u32 otp_mask_2; /* 0x848 */
• u32 otp_mask_3; /* 0x84c */
• u32 otp_mask_4; /* 0x850 */
• u32 otp_mask_5; /* 0x854 */
• u32 otp_mask_6; /* 0x858 */
• u32 otp_mask_7; /* 0x85c */
• u32 otp_mask_8; /* 0x860 */
• u32 otp_rdata1_1; /* 0x864 */
• u32 otp_rdata1_2; /* 0x868 */
• u32 otp_rdata1_3; /* 0x86c */
• u32 otp_rdata1_4; /* 0x870 */
• u32 otp_rdata1_5; /* 0x874 */
• u32 otp_rdata1_6; /* 0x878 */
• u32 otp_rdata1_7; /* 0x87c */
• u32 otp_rdata1_8; /* 0x880 */
• u32 otp_rdata2_1; /* 0x884 */
• u32 otp_rdata2_2; /* 0x888 */
• u32 otp_rdata2_3; /* 0x88c */
• u32 otp_rdata2_4; /* 0x890 */
• u32 otp_rdata2_5; /* 0x894 */
• u32 otp_rdata2_6; /* 0x898 */
• u32 otp_rdata2_7; /* 0x89c */
• u32 otp_rdata2_8; /* 0x8a0 */
• u32 otp_rdatam_1; /* 0x8a4 */
• u32 otp_rdatam_2; /* 0x8a8 */
• u32 otp_rdatam_3; /* 0x8ac */
• u32 otp_rdatam_4; /* 0x8b0 */
• u32 otp_rdatam_5; /* 0x8b4 */
• u32 otp_rdatam_6; /* 0x8b8 */
• u32 otp_rdatam_7; /* 0x8bc */
• u32 otp_rdatam_8; /* 0x8c0 */
• u8 reserved_11[0x900 - 0x8c4];
• u32 a9sm_clusterid; /* 0x900 */
• u32 a9sm_status; /* 0x904 */
• u32 a9sm_debug; /* 0x908 */
• u32 a9sm_filter; /* 0x90c */
• u32 a9sm_parity_cfg; /* 0x910 */
• u32 a9sm_parity_err; /* 0x914 */
• u8 reserved_12[0xa00 - 0x918];
• u32 die_id_1; /* 0xa00 */
• u32 die_id_2; /* 0xa04 */
• u32 die_id_3; /* 0xa08 */
• u32 die_id_4; /* 0xa0c */
• u32 die_id_valid; /* 0xa10 */
• u8 reserved_13[0xb00 - 0xa14];
• u32 ras1_gpp_inp; /* 0xb00 */
• u32 ras2_gpp_inp; /* 0xb04 */
• u32 ras1_gpp_out; /* 0xb08 */
• u32 ras2_gpp_out; /* 0xb0c */
• u8 reserved_14[0x1000 - 0xb10];
• u32 miphy_test; /* 0x1000 */
• u32 pcie_mstr_p1; /* 0x1004 */
• u32 pcie_awmisc_p1; /* 0x1008 */
• u32 pcie_armisc_p1; /* 0x100c */
• u32 pcie_mstr_p2; /* 0x1010 */
• u32 pcie_awmisc_p2; /* 0x1014 */
• u32 pcie_armisc_p2; /* 0x1018 */
• u32 pcie_mstr_p3; /* 0x101c */
• u32 pcie_awmisc_p3; /* 0x1020 */
• u32 pcie_armisc_p3; /* 0x1024 */

+};

+/* sys_clk_ctrl definitions */ +#define SYS_MODE_MASK (7 << 0) +#define SYS_MODE_REQ_DOZE (1 << 0) +#define SYS_MODE_REQ_SLOW (2 << 0) +#define SYS_MODE_REQ_NORMAL (4 << 0) +#define PLL_TIMEOUT_ENB (1 << 3) +#define XTAL_TIMEOUT_ENB (1 << 4) +#define SYS_STATE_MASK (0xF << 16) +#define SYS_STATE_NORMAL (0xF << 16)

+/* sys_clk_*timer definitions */ +#define PLL_TIM (0xff << 3) +#define OSCI_TIM (0xff << 3)

+/* pll_freq definitions in MHz */ +#define FREQ_1000 (0xFA000106) +#define FREQ_996 (0x53000004) +#define FREQ_332 (0x53000203)

+/* pll_ctr definitions */ +#define PLLLOCK (1 << 0) +#define PLLENABLE (1 << 1)

+/* perip_clk_cfg definitions */ +#define MPMC_CLK_PLL4 (1 << 10)

+/* perip*_[clk_enb/sw_rst] definitions */ +#define BUS_CLKEN (1 << 0) /* perip1 */ +#define SYSROM_CLKEN (1 << 1) +#define AORAM_CLKEN (1 << 2) +#define SYSRAM_CLKEN (1 << 3) +#define FSMC_CLKEN (1 << 4) +#define SMI_CLKEN (1 << 5) +#define SD_CLKEN (1 << 6) +#define CFXD_CLKEN (1 << 7) +#define GETH_CLKEN (1 << 8) +#define UHC1_CLKEN (1 << 9) +#define UHC2_CLKEN (1 << 10) +#define UDC_UPD_CLKEN (1 << 11) +#define PCI1_CLKEN (1 << 12) +#define PCI2_CLKEN (1 << 13) +#define PCI3_CLKEN (1 << 14) +#define UART_CLKEN (1 << 15) +#define SSP_CLKEN (1 << 17) +#define I2C_CLKEN (1 << 18) +#define I2S_SLV_CLKEN (1 << 19) +#define I2S_MST_CLKEN (1 << 20) +#define GPT1_CLKEN (1 << 21) +#define GPT2_CLKEN (1 << 22) +#define GPIO1_CLKEN (1 << 23) +#define GPIO2_CLKEN (1 << 24) +#define DMA1_CLKEN (1 << 25) +#define DMA2_CLKEN (1 << 26) +#define CLCD_CLKEN (1 << 27) +#define JPEG_CLKEN (1 << 28) +#define C3_CLKEN (1 << 29) +#define ADC_CLKEN (1 << 30) +#define RTC_CLKEN (1 << 31)

+#define DDR_CTRL_CLKEN (1 << 0) /* perip2 */ +#define DDR_CORE_CLKEN (1 << 1) +#define CPU_DBG_CLKEN (1 << 2) +#define KBD_CLKEN (1 << 3) +#define GPT3_CLKEN (1 << 4) +#define GPT4_CLKEN (1 << 5) +#define ACP_CLKEN (1 << 6) +#define I2S_REFOUT_CLKEN (1 << 7) +#define THSENS_CLKEN (1 << 8)

+/* fsmc_cfg definitions */ +#define DEV_SEL_NOR (0 << 0) +#define DEV_SEL_NAND (1 << 0) +#define DEV_SEL_SRAM (2 << 0) +#define DEV_SEL_MSK (3 << 0) +#define NAND_BANK_0 (0 << 2) +#define NAND_BANK_1 (1 << 2) +#define NAND_BANK_2 (2 << 2) +#define NAND_BANK_3 (3 << 2) +#define DEV_WIDTH_8 (0 << 4) +#define DEV_WIDTH_16 (1 << 4)

+/* usbphy_gen_cfg definitions */ +#define COMMON_PWDN (1 << 0) +#define USBPHY_POR (1 << 12) +#define USBPHY_RST (1 << 13) +#define UTMI_XFER_RST0 (1 << 14) +#define UTMI_XFER_RST1 (1 << 15) +#define UTMI_XFER_RST2 (1 << 16) +#define USB_PLL_LOCK (1 << 27)

+/* synth registers definitions */ +#define SYNT_CLK_ENB (1 << 31) +#define SYNT_FIN_FULL (1 << 30) +#define SYNT_X_1 (1 << 16) +#define SYNT_Y_2 (2 << 0) +#define SYNT_Y_5 (5 << 0)

+/* gmac_clk_cfg definitions */ +#define PHY_IF_GMII (0 << 4) +#define PHY_IF_RGMII (1 << 4) +#define PHY_IF_RMII (4 << 4) +#define GMII_SYNT_ENB (1 << 3) +#define CLK_SEL_PAD (0 << 0) +#define CLK_SEL_PLL2 (1 << 0) +#define CLK_SEL_OSCI3 (2 << 0)

+#endif diff --git a/arch/arm/include/asm/arch-spear13xx/sys_proto.h b/arch/arm/include/asm/arch-spear13xx/sys_proto.h new file mode 100644 index 0000000..e6cc3a9 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/sys_proto.h @@ -0,0 +1,32 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, STMicroelectronics, vipin.kumar@st.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_

+u32 get_device_type(void);

This is needed for omap3. Remove

Again, this becomes necessary if I want to use the generic cpu code

Regards Vipin

Tom

...

+void invalidate_dcache(u32); +void l2_cache_disable(void); +void l2_cache_enable(void);

+#endif

Vipin KUMAR wrote:

The smi IP used by spear platform is a ST serial memory interface controller The earlier driver adds the driver of this controller as if it is specific to spear platform. The driver files are now moved into drivers/mtd folder for reusability by other platforms

Similar cleanup of 'IP' and 'ST'

Tom

Signed-off-by: Vipin Kumar vipin.kumar@st.com

drivers/mtd/Makefile | 2 +- drivers/mtd/{spr_smi.c => st_smi.c} | 2 +- .../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 4 ++-- include/configs/spear-common.h | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/mtd/{spr_smi.c => st_smi.c} (99%) rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (99%)

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index cbf6f15..d868d27 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,7 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/st_smi.c similarity index 99% rename from drivers/mtd/spr_smi.c rename to drivers/mtd/st_smi.c index 189ee6d..80d9fee 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/st_smi.c @@ -27,7 +27,7 @@

#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_smi.h> +#include "st_smi.h"

#if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/drivers/mtd/st_smi.h similarity index 99% rename from arch/arm/include/asm/arch-spear/spr_smi.h rename to drivers/mtd/st_smi.h index e2e5e8f..37ed503 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/drivers/mtd/st_smi.h @@ -21,8 +21,8 @@

• MA 02111-1307 USA

*/

-#ifndef SPR_SMI_H -#define SPR_SMI_H +#ifndef ST_SMI_H +#define ST_SMI_H

/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index e49f267..99923de 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -57,10 +57,10 @@ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_SPEAR_EMI 1 #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI 1 #endif

-#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI)

#define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) @@ -125,7 +125,7 @@

• U-Boot Environment placing definitions.

*/ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /*

• Environment is in serial NOR flash

*/

Vipin KUMAR wrote:

The i2c IP used by spear platform is a synopsys i2c controller

'IP' expand.

What is the connection between 'synopsys' and 'designware' ? If the part is synopsys, that should be the string used instead of 'dw' or 'designware'

The earlier driver adds the driver of this controller as if it is specific to spear platform. The driver files are now moved into drivers/i2c folder for reusability by other

Maybe something like 'The earlier i2c driver was specific to spear platforms. This driver has been moved to the common driver directory drivers/i2c where it can be used by other platforms'

Tom

platforms

Signed-off-by: Vipin Kumar vipin.kumar@st.com

drivers/i2c/Makefile | 2 +- drivers/i2c/{spr_i2c.c => designware_i2c.c} | 4 ++-- .../spr_i2c.h => drivers/i2c/designware_i2c.h | 6 +++--- include/configs/spear-common.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/i2c/{spr_i2c.c => designware_i2c.c} (98%) rename arch/arm/include/asm/arch-spear/spr_i2c.h => drivers/i2c/designware_i2c.h (98%)

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d2c2515..099a6cd 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libi2c.a

COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o +COBJS-$(CONFIG_DW_I2C) += designware_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o @@ -38,7 +39,6 @@ COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o -COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o

COBJS := $(COBJS-y) diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/designware_i2c.c similarity index 98% rename from drivers/i2c/spr_i2c.c rename to drivers/i2c/designware_i2c.c index eabfe84..d352146 100644 --- a/drivers/i2c/spr_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_i2c.h> +#include "designware_i2c.h"

static struct i2c_regs *const i2c_regs_p = (struct i2c_regs *)CONFIG_SYS_I2C_BASE; @@ -113,7 +113,7 @@ int i2c_get_bus_speed(void) /*

• i2c_init - Init function
• @speed: required i2c speed

• • @slaveadd: slave address for the spear device

• • @slaveadd: slave address for the device
  • Initialization function.
  */

diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/drivers/i2c/designware_i2c.h similarity index 98% rename from arch/arm/include/asm/arch-spear/spr_i2c.h rename to drivers/i2c/designware_i2c.h index 7521ebc..03b520e 100644 --- a/arch/arm/include/asm/arch-spear/spr_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -21,8 +21,8 @@

• MA 02111-1307 USA

*/

-#ifndef __SPR_I2C_H_ -#define __SPR_I2C_H_ +#ifndef __DW_I2C_H_ +#define __DW_I2C_H_

struct i2c_regs { u32 ic_con; @@ -143,4 +143,4 @@ struct i2c_regs { #define I2C_FAST_SPEED 400000 #define I2C_STANDARD_SPEED 100000

-#endif /* __SPR_I2C_H_ */ +#endif /* __DW_I2C_H_ */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 3eaa086..e49f267 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -44,7 +44,7 @@

/* I2C driver configuration */ #define CONFIG_HARD_I2C -#define CONFIG_SPEAR_I2C +#define CONFIG_DW_I2C #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02

...

-extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index cd24247..bb98161 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -52,7 +52,7 @@ int board_nand_init(struct nand_chip *nand) ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

•    return spear_nand_init(nand);
  

•    return fsmc_nand_init(nand);
  

Can make this conditionally compiled with CONFIG_NAND_FSMC

OK. Please find these changes in v3

Regards Vipin

Vipin KUMAR wrote:

Flexible static memory controller is an IP which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM. This is an ST peripheral. This patch adds the driver support for FSMC controller interfacing with NAND memory.

IP, ST ? Add meaning of IP and something to say ST is manufacturer and not a class of peripherals.

Signed-off-by: Vipin Kumar vipin.kumar@st.com

drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsmc_nand.c | 365 +++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/fsmc_nand.h | 104 ++++++++++++ 3 files changed, 470 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsmc_nand.c create mode 100644 include/linux/mtd/fsmc_nand.h

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 28f27da..4c6b54f 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c new file mode 100644 index 0000000..bad5606 --- /dev/null +++ b/drivers/mtd/nand/fsmc_nand.c @@ -0,0 +1,365 @@ +/*

• • (C) Copyright 2009

2009?

• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h>

+static u32 fsmc_version; +static struct fsmc_regs *const fsmc_regs_p =

• (struct fsmc_regs *)CONFIG_SYS_FSMC_BASE;

CONFIG_SYS_FSMC_BASE is not defined until 11/17 This make this change non-bisectable. Fix.

+/*

• • ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
• • data. ECC4 can correct upto 8 bits in 512 bytes of data while ECC1 can

'upto' -> 'up to'

• • correct 1 bit in 512 bytes
• */

+#if defined(CONFIG_SYS_FSMC_NAND_LP) +static struct nand_ecclayout fsmc_ecc4_layout = {

• .eccbytes = 104,
• .eccpos = { 2, 3, 4, 5, 6, 7, 8,

• 9,  10,  11,  12,  13,  14,
  

• 18,  19,  20,  21,  22,  23,  24,
  

• 25,  26,  27,  28,  29,  30,
  

• 34,  35,  36,  37,  38,  39,  40,
  

• 41,  42,  43,  44,  45,  46,
  

• 50,  51,  52,  53,  54,  55,  56,
  

• 57,  58,  59,  60,  61,  62,
  

• 66,  67,  68,  69,  70,  71,  72,
  

• 73,  74,  75,  76,  77,  78,
  

• 82,  83,  84,  85,  86,  87,  88,
  

• 89,  90,  91,  92,  93,  94,
  

• 98,  99, 100, 101, 102, 103, 104,
  

• 105, 106, 107, 108, 109, 110,
  

• 114, 115, 116, 117, 118, 119, 120,
  

• 121, 122, 123, 124, 125, 126
  

• },
• .oobfree = {

• {.offset = 15, .length = 3},
  

• {.offset = 31, .length = 3},
  

• {.offset = 47, .length = 3},
  

• {.offset = 63, .length = 3},
  

• {.offset = 79, .length = 3},
  

• {.offset = 95, .length = 3},
  

• {.offset = 111, .length = 3},
  

• {.offset = 127, .length = 1}
  

• }

+};

+/*

• • ECC placement definitions in oobfree type format
• • There are 13 bytes of ecc for every 512 byte block and it has to be read
• • consicutively and immidiately after the 512 byte data block for hardware to

'consivutively, immidiately' fix spelling

• • generate the error bit offsets in 512 byte data
• • Managing the ecc bytes in the following way makes it easier for software to
• • read ecc bytes consicutive to data bytes. This way is similar to

'consicutive'

• • oobfree structure maintained already in u-boot nand driver
• */

+static struct fsmc_eccplace fsmc_eccpl = {

• .eccplace = {

• {.offset = 2, .length = 13},
  

• {.offset = 18, .length = 13},
  

• {.offset = 34, .length = 13},
  

• {.offset = 50, .length = 13},
  

• {.offset = 66, .length = 13},
  

• {.offset = 82, .length = 13},
  

• {.offset = 98, .length = 13},
  

• {.offset = 114, .length = 13}
  

• }

+};

+#elif defined(CONFIG_SYS_FSMC_NAND_SP) +static struct nand_ecclayout fsmc_ecc4_layout = {

• .eccbytes = 13,
• .eccpos = { 0, 1, 2, 3, 6, 7, 8,

• 9, 10, 11, 12, 13, 14
  

• },
• .oobfree = {

• {.offset = 15, .length = 1},
  

• }

+};

+static struct fsmc_eccplace fsmc_eccpl = {

• .eccplace = {

•     {.offset = 0, .length = 4},
  

•     {.offset = 6, .length = 9}
  

•     }
  

+};

+#else +#error Please define one of CONFIG_SYS_FSMC_NAND_SP or CONFIG_SYS_FSMC_NAND_LP

Good!

+#endif

+static struct nand_ecclayout fsmc_ecc1_layout = {

• .eccbytes = 24,
• .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,

•    66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
  

• .oobfree = {

•     {.offset = 8, .length = 8},
  

•     {.offset = 24, .length = 8},
  

•     {.offset = 40, .length = 8},
  

•     {.offset = 56, .length = 8},
  

•     {.offset = 72, .length = 8},
  

•     {.offset = 88, .length = 8},
  

•     {.offset = 104, .length = 8},
  

•     {.offset = 120, .length = 8}
  

•     }
  

+};

+static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{

• struct nand_chip *this = mtd->priv;
• ulong IO_ADDR_W;
• if (ctrl & NAND_CTRL_CHANGE) {

• IO_ADDR_W = (ulong)this->IO_ADDR_W;
  

• IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
  

• if (ctrl & NAND_CLE)
  

• 	IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
  

• if (ctrl & NAND_ALE)
  

• 	IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
  

• if (ctrl & NAND_NCE) {
  

• 	writel(readl(&fsmc_regs_p->pc) |
  

• 	       FSMC_ENABLE, &fsmc_regs_p->pc);
  

• } else {
  

• 	writel(readl(&fsmc_regs_p->pc) &
  

• 	       ~FSMC_ENABLE, &fsmc_regs_p->pc);
  

• }
  

• this->IO_ADDR_W = (void *)IO_ADDR_W;
  

• }
• if (cmd != NAND_CMD_NONE)

• writeb(cmd, this->IO_ADDR_W);
  

+}

+static int fsmc_correct_data(struct mtd_info *mtd, u_char *dat,

•       u_char *read_ecc, u_char *calc_ecc)
  

+{

• /* The calculated ecc is actually the correction index in data */
• u16 err_idx[8];
• u64 ecc_data[2];
• u32 num_err, i;
• memcpy(ecc_data, calc_ecc, 13);
• for (i = 0; i < 8; i++) {

• if (i == 4) {
  

• 	err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
  

• 	ecc_data[1] >>= 1;
  

• 	continue;
  

• }
  

• err_idx[i] = (ecc_data[i/4] & 0x1FFF);
  

• ecc_data[i/4] >>= 13;
  

• }
• num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
• if (num_err == 0xF)

• return -EBADMSG;
  

• i = 0;
• while (num_err--) {

• change_bit(0, &err_idx[i]);
  

• change_bit(1, &err_idx[i]);
  

• if (err_idx[i] <= 512 * 8) {
  

• 	change_bit(err_idx[i], dat);
  

• 	i++;
  

• }
  

• }
• return i;

+}

+static int fsmc_read_hwecc(struct mtd_info *mtd,

• 	    const u_char *data, u_char *ecc)
  

+{

• u_int ecc_tmp;
• switch (fsmc_version) {
• case FSMC_VER8:

• while (!(readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY))
  

• 	;
  

Add a comment that this is a busy wait.

• ecc_tmp = readl(&fsmc_regs_p->ecc1);
  

• ecc[0] = (u_char) (ecc_tmp >> 0);
  

• ecc[1] = (u_char) (ecc_tmp >> 8);
  

• ecc[2] = (u_char) (ecc_tmp >> 16);
  

• ecc[3] = (u_char) (ecc_tmp >> 24);
  

• ecc_tmp = readl(&fsmc_regs_p->ecc2);
  

• ecc[4] = (u_char) (ecc_tmp >> 0);
  

• ecc[5] = (u_char) (ecc_tmp >> 8);
  

• ecc[6] = (u_char) (ecc_tmp >> 16);
  

• ecc[7] = (u_char) (ecc_tmp >> 24);
  

• ecc_tmp = readl(&fsmc_regs_p->ecc3);
  

• ecc[8] = (u_char) (ecc_tmp >> 0);
  

• ecc[9] = (u_char) (ecc_tmp >> 8);
  

• ecc[10] = (u_char) (ecc_tmp >> 16);
  

• ecc[11] = (u_char) (ecc_tmp >> 24);
  

• ecc_tmp = readl(&fsmc_regs_p->sts);
  

• ecc[12] = (u_char) (ecc_tmp >> 16);
  

• break;
  

• default:

• ecc_tmp = readl(&fsmc_regs_p->ecc1);
  

• ecc[0] = (u_char) (ecc_tmp >> 0);
  

• ecc[1] = (u_char) (ecc_tmp >> 8);
  

• ecc[2] = (u_char) (ecc_tmp >> 16);
  

• break;
  

• }
• return 0;

+}

+void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) +{

• writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,

•       &fsmc_regs_p->pc);
  

• writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,

•       &fsmc_regs_p->pc);
  

• writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,

•       &fsmc_regs_p->pc);
  

+}

+/**

extra '*'

• • fsmc_read_page_hwecc
• • @mtd: mtd info structure
• • @chip: nand chip info structure
• • @buf: buffer to store read data
• • @page: page number to read
• • This routine is needed for fsmc verison 8 as reading from NAND chip has to be
• • performed in a strict sequence as follows:
• • data(512 byte) -> ecc(13 byte)
• • After this read, fsmc hardware generates and reports error data bits(upto a
• • max of 8 bits)
• */

+static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

• 		 uint8_t *buf, int page)
  

+{

• int i, j, s, stat, eccsize = chip->ecc.size;
• int eccbytes = chip->ecc.bytes;
• int eccsteps = chip->ecc.steps;
• uint8_t *p = buf;
• uint8_t *ecc_calc = chip->buffers->ecccalc;
• uint8_t *ecc_code = chip->buffers->ecccode;
• int off, len;
• /*

• * ecc_oob is intentionally taken as u16. In 16bit devices, we end up
  

• * reading 14 bytes (7 words) from oob. The local array is to maintain
  

• * word alignment
  

• */
  

• uint16_t ecc_oob[7];
• for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {

• chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
  

• chip->ecc.hwctl(mtd, NAND_ECC_READ);
  

• chip->read_buf(mtd, p, eccsize);
  

• for (j = 0; j < eccbytes;) {
  

• 	off = fsmc_eccpl.eccplace[s].offset;
  

• 	len = fsmc_eccpl.eccplace[s].length;
  

• 	/*
  

• 	 * length is intentionally kept a higher multiple of 2
  

• 	 * to read at least 13 bytes even in case of 16 bit NAND
  

• 	 * devices
  

• 	 */
  

• 	len = roundup(len, 2);
  

• 	chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
  

• 	chip->read_buf(mtd, (uint8_t *)&ecc_oob[j], len);
  

• 	j += len;
  

• }
  

• memcpy(&ecc_code[i], ecc_oob, 13);
  

• chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  

• stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  

• if (stat < 0)
  

• 	mtd->ecc_stats.failed++;
  

• else
  

• 	mtd->ecc_stats.corrected += stat;
  

• }
• return 0;

+}

+int fsmc_nand_init(struct nand_chip *nand) +{

• u32 peripid2 = readl(&fsmc_regs_p->peripid2);
• fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &

•        FSMC_REVISION_MSK;
  

+#if defined(CONFIG_SYS_FSMC_NAND_16BIT)

16BIT is never defined This is dead code Remove

• writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,

•       &fsmc_regs_p->pc);
  

+#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)

• writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,

•       &fsmc_regs_p->pc);
  

+#else +#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT +#endif

• writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,

•       &fsmc_regs_p->pc);
  

• writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,

•       &fsmc_regs_p->comm);
  

• writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,

•       &fsmc_regs_p->attrib);
  

• nand->options = 0;

+#if defined(CONFIG_SYS_FSMC_NAND_16BIT)

• nand->options |= NAND_BUSWIDTH_16;

+#endif

• nand->ecc.mode = NAND_ECC_HW;
• nand->ecc.size = 512;
• nand->ecc.calculate = fsmc_read_hwecc;
• nand->ecc.hwctl = fsmc_enable_hwecc;
• nand->cmd_ctrl = fsmc_nand_hwcontrol;
• switch (fsmc_version) {
• case FSMC_VER8:

• nand->ecc.bytes = 13;
  

• nand->ecc.layout = &fsmc_ecc4_layout;
  

• nand->ecc.correct = fsmc_correct_data;
  

• nand->ecc.read_page = fsmc_read_page_hwecc;
  

• break;
  

• default:

• nand->ecc.bytes = 3;
  

• nand->ecc.layout = &fsmc_ecc1_layout;
  

• nand->ecc.correct = nand_correct_data;
  

• break;
  

• }
• return 0;

+} diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h new file mode 100644 index 0000000..fd7059e --- /dev/null +++ b/include/linux/mtd/fsmc_nand.h @@ -0,0 +1,104 @@ +/*

• • (C) Copyright 2009
• • Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __FSMC_NAND_H__ +#define __FSMC_NAND_H__

+struct fsmc_regs {

• u8 reserved_1[0x40];
• u32 pc; /* 0x40 */
• u32 sts; /* 0x44 */
• u32 comm; /* 0x48 */
• u32 attrib; /* 0x4c */
• u32 ioata; /* 0x50 */
• u32 ecc1; /* 0x54 */
• u32 ecc2; /* 0x58 */
• u32 ecc3; /* 0x5c */
• u8 reserved_2[0xfe0 - 0x60];
• u32 peripid0; /* 0xfe0 */
• u32 peripid1; /* 0xfe4 */
• u32 peripid2; /* 0xfe8 */
• u32 peripid3; /* 0xfec */
• u32 pcellid0; /* 0xff0 */
• u32 pcellid1; /* 0xff4 */
• u32 pcellid2; /* 0xff8 */
• u32 pcellid3; /* 0xffc */

+};

+/* pc register definitions */ +#define FSMC_RESET (1 << 0) +#define FSMC_WAITON (1 << 1) +#define FSMC_ENABLE (1 << 2) +#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_DEVWID_8 (0 << 4) +#define FSMC_DEVWID_16 (1 << 4) +#define FSMC_ECCEN (1 << 6) +#define FSMC_ECCPLEN_512 (0 << 7) +#define FSMC_ECCPLEN_256 (1 << 7) +#define FSMC_TCLR_1 (1 << 9) +#define FSMC_TAR_1 (1 << 13)

+/* sts register definitions */ +#define FSMC_CODE_RDY (1 << 15)

+/* comm register definitions */ +#define FSMC_TSET_0 (0 << 0) +#define FSMC_TWAIT_6 (6 << 8) +#define FSMC_THOLD_4 (4 << 16) +#define FSMC_THIZ_1 (1 << 24)

+/* peripid2 register definitions */ +#define FSMC_REVISION_MSK (0xf) +#define FSMC_REVISION_SHFT (0x4)

+enum {

• FSMC_VER1 = 1,
• FSMC_VER2,
• FSMC_VER3,
• FSMC_VER4,
• FSMC_VER5,
• FSMC_VER6,
• FSMC_VER7,
• FSMC_VER8,

+};

+/*

• • There are 13 bytes of ecc for every 512 byte block and it has to be read
• • consicutively and immidiately after the 512 byte data block for hardware to

'consicutively' Please check spelling

Tom

• • generate the error bit offsets
• • Managing the ecc bytes in the following way is easier. This way is similar to
• • oobfree structure maintained already in u-boot nand driver
• */

+#define MAX_ECCPLACE_ENTRIES 32

+struct fsmc_nand_eccplace {

• u32 offset;
• u32 length;

+};

+struct fsmc_eccplace {

• struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];

+};

+extern int fsmc_nand_init(struct nand_chip *nand); +#endif

Vipin KUMAR wrote:

Add more detail in the commit to the what this change is and why it is needed.

Signed-off-by: Vipin Kumar vipin.kumar@st.com

arch/arm/include/asm/arch-spear/clk.h | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-spear/hardware.h | 7 +++++++ board/spear/spear310/spear310.c | 9 ++++++++- board/spear/spear320/spear320.c | 6 +++++- include/configs/spear3xx.h | 13 +++++++++++++ 5 files changed, 60 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-spear/clk.h

diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000..343c6ce --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/*

• • (C) Copyright 2009

2009 ? Maybe this should be 2010? Check globally.

• • Vipin Kumar, STMicroelectronics, vipin.kumar@st.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{

• return 83000000;

+} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 39d64b6..9f1e154 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -56,6 +56,11 @@ #define CONFIG_SPEAR_EMIBASE (0x4F000000) #define CONFIG_SPEAR_RASBASE (0xB4000000)

+#define CONFIG_SYS_MACB0_BASE (0xB0000000) +#define CONFIG_SYS_MACB1_BASE (0xB0800000) +#define CONFIG_SYS_MACB2_BASE (0xB1000000) +#define CONFIG_SYS_MACB3_BASE (0xB1800000)

#elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SPEAR_FSMCBASE (0x4C000000) @@ -63,5 +68,7 @@ #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000)

+#define CONFIG_SYS_MACB0_BASE (0xAA000000)

#endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index e8a6552..1207709 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -61,5 +61,12 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) {

• return dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE);

• dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE);

Previously, status of dw_mii_initialize was forward up to caller. Now it is ignored. Add a check if it passes fails. Foward check status to caller

• macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, CONFIG_MACB0_PHY);
• macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, CONFIG_MACB1_PHY);
• macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, CONFIG_MACB2_PHY);
• macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, CONFIG_MACB3_PHY);
• return 0;

} diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 72bc9a5..efc9a99 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -61,5 +61,9 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) {

• return dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE);

• dw_mii_initialize(0, CONFIG_SPEAR_ETHBASE);
• macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, CONFIG_MACB0_PHY);
• return 0;

} diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 502c50f..689d914 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -44,6 +44,19 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR 1

+#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07

+#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01

Is network not available for spear300 ?

Tom

+#endif

/* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000