[U-Boot] [PATCH v2 1/3] watchdog: Add Cadence watchdog driver
From: Shreenidhi Shedi imshedi@gmail.com
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
Signed-off-by: Shreenidhi Shedi imshedi@gmail.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v2: - s/int32/int/g - Extend CONFIG_WATCHDOG option to have option to disable it.
drivers/watchdog/Kconfig | 16 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cdns_wdt.c | 276 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 drivers/watchdog/cdns_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index fc46b6774d57..8a66e479ab84 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1,5 +1,13 @@ menu "Watchdog Timer Support"
+config WATCHDOG + bool "Enable U-Boot watchdog reset" + help + This option enables U-Boot watchdog support where U-Boot is using + watchdog_reset function to service watchdog device in U-Boot. Enable + this option if you want to service enabled watchdog by U-Boot. Disable + this option if you want U-Boot to start watchdog but never service it. + config HW_WATCHDOG bool
@@ -78,4 +86,12 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips.
+config WDT_CDNS + bool "Cadence watchdog timer support" + depends on WDT + imply WATCHDOG + help + Select this to enable Cadence watchdog timer, which can be found on some + Xilinx Microzed Platform. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ab6a6b79e1d7..4b97df3ab67b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o +obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c new file mode 100644 index 000000000000..71733cf8ba1f --- /dev/null +++ b/drivers/watchdog/cdns_wdt.c @@ -0,0 +1,276 @@ +/* + * Cadence WDT driver - Used by Xilinx Zynq + * Reference: Linux kernel Cadence watchdog driver. + * + * Author(s): Shreenidhi Shedi yesshedi@gmail.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <wdt.h> +#include <clk.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct cdns_regs { + u32 zmr; /* WD Zero mode register, offset - 0x0 */ + u32 ccr; /* Counter Control Register offset - 0x4 */ + u32 restart; /* Restart key register, offset - 0x8 */ + u32 status; /* Status Register, offset - 0xC */ +}; + +struct cdns_wdt_priv { + bool rst; + u32 timeout; + void __iomem *reg; + struct cdns_regs *regs; +}; + +#define CDNS_WDT_DEFAULT_TIMEOUT 10 + +/* Supports 1 - 516 sec */ +#define CDNS_WDT_MIN_TIMEOUT 1 +#define CDNS_WDT_MAX_TIMEOUT 516 + +/* Restart key */ +#define CDNS_WDT_RESTART_KEY 0x00001999 + +/* Counter register access key */ +#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000 + +/* Counter value divisor */ +#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000 + +/* Clock prescaler value and selection */ +#define CDNS_WDT_PRESCALE_64 64 +#define CDNS_WDT_PRESCALE_512 512 +#define CDNS_WDT_PRESCALE_4096 4096 +#define CDNS_WDT_PRESCALE_SELECT_64 1 +#define CDNS_WDT_PRESCALE_SELECT_512 2 +#define CDNS_WDT_PRESCALE_SELECT_4096 3 + +/* Input clock frequency */ +#define CDNS_WDT_CLK_75MHZ 75000000 + +/* Counter maximum value */ +#define CDNS_WDT_COUNTER_MAX 0xFFF + +/********************* Register Map **********************************/ + +/* + * Zero Mode Register - This register controls how the time out is indicated + * and also contains the access code to allow writes to the register (0xABC). + */ +#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */ +#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */ +#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */ +#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */ +#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */ + +/* + * Counter Control register - This register controls how fast the timer runs + * and the reset value and also contains the access code to allow writes to + * the register. + */ +#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */ + +/* Write access to Registers */ +static inline void cdns_wdt_writereg(u32 *addr, u32 val) +{ + writel(val, addr); +} + +/** + * cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog). + * + * @dev: Watchdog device + * + * Write the restart key value (0x00001999) to the restart register. + * + * Return: Always 0 + */ +static int cdns_wdt_reset(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + +/** + * cdns_wdt_start - Enable and start the watchdog. + * + * @dev: Watchdog device + * @timeout: Timeout value + * @flags: Driver flags + * + * The counter value is calculated according to the formula: + * count = (timeout * clock) / prescaler + 1. + * + * The calculated count is divided by 0x1000 to obtain the field value + * to write to counter control register. + * + * Clears the contents of prescaler and counter reset value. Sets the + * prescaler to 4096 and the calculated count and access key + * to write to CCR Register. + * + * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit) + * or Interrupt signal(IRQEN) with a specified cycles and the access + * key to write to ZMR Register. + * + * Return: Upon success 0, failure -1. + */ +static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + ulong clk_f; + u32 count, prescaler, ctrl_clksel, data = 0; + struct clk clock; + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + if (clk_get_by_index(dev, 0, &clock) < 0) { + dev_err(dev, "failed to get clock\n"); + return -1; + } + + clk_f = clk_get_rate(&clock); + if (IS_ERR_VALUE(clk_f)) { + dev_err(dev, "failed to get rate\n"); + return -1; + } + + debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout); + + if ((timeout < CDNS_WDT_MIN_TIMEOUT) || + (timeout > CDNS_WDT_MAX_TIMEOUT)) { + timeout = priv->timeout; + } + + if (clk_f <= CDNS_WDT_CLK_75MHZ) { + prescaler = CDNS_WDT_PRESCALE_512; + ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512; + } else { + prescaler = CDNS_WDT_PRESCALE_4096; + ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096; + } + + /* + * Counter value divisor to obtain the value of + * counter reset to be written to control register. + */ + count = (timeout * (clk_f / prescaler)) / + CDNS_WDT_COUNTER_VALUE_DIVISOR + 1; + + if (count > CDNS_WDT_COUNTER_MAX) + count = CDNS_WDT_COUNTER_MAX; + + cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL); + + count = (count << 2) & CDNS_WDT_CCR_CRV_MASK; + + /* Write counter access key first to be able write to register */ + data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel; + cdns_wdt_writereg(&priv->regs->ccr, data); + + data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 | + CDNS_WDT_ZMR_ZKEY_VAL; + + /* Reset on timeout if specified in device tree. */ + if (priv->rst) { + data |= CDNS_WDT_ZMR_RSTEN_MASK; + data &= ~CDNS_WDT_ZMR_IRQEN_MASK; + } else { + data &= ~CDNS_WDT_ZMR_RSTEN_MASK; + data |= CDNS_WDT_ZMR_IRQEN_MASK; + } + + cdns_wdt_writereg(&priv->regs->zmr, data); + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + +/** + * cdns_wdt_stop - Stop the watchdog. + * + * @dev: Watchdog device + * + * Read the contents of the ZMR register, clear the WDEN bit in the register + * and set the access key for successful write. + * + * Return: Always 0 + */ +static int cdns_wdt_stop(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + cdns_wdt_writereg(&priv->regs->zmr, + CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK)); + + return 0; +} + +/** + * cdns_wdt_probe - Probe call for the device. + * + * @dev: Handle to the udevice structure. + * + * Return: Always 0. + */ +static int cdns_wdt_probe(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs)); + + cdns_wdt_stop(dev); + + return 0; +} + +static int cdns_wdt_ofdata_to_platdata(struct udevice *dev) +{ + int node = dev_of_offset(dev); + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec", + CDNS_WDT_DEFAULT_TIMEOUT); + + priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout"); + + debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst); + + return 0; +} + +static const struct wdt_ops cdns_wdt_ops = { + .start = cdns_wdt_start, + .reset = cdns_wdt_reset, + .stop = cdns_wdt_stop, +}; + +static const struct udevice_id cdns_wdt_ids[] = { + { .compatible = "cdns,wdt-r1p2" }, + {} +}; + +U_BOOT_DRIVER(cdns_wdt) = { + .name = "cdns_wdt", + .id = UCLASS_WDT, + .of_match = cdns_wdt_ids, + .probe = cdns_wdt_probe, + .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv), + .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata, + .ops = &cdns_wdt_ops, +};
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v2: - Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL + select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NET diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT) + /* bss is not cleared at time when watchdog_reset() is called */ + watchdog_dev = NULL; +# endif + + return 0; +} +#endif + int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Watchdog: Not found!\n"); + } else { + wdt_start(watchdog_dev, 0, 0); + puts("Watchdog: Started\n"); + } +# endif + #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD) + static ulong next_reset; + ulong now; + + if (!watchdog_dev) + return; + + now = timer_get_us(); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + wdt_reset(watchdog_dev); + next_reset = now + 1000; + } +# endif +} +#endif
On Mon, 26 Feb 2018 10:09:55 +0100 Michal Simek michal.simek@xilinx.com wrote:
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL
- select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NET
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT)
- /* bss is not cleared at time when watchdog_reset() is
called */
- watchdog_dev = NULL;
+# endif
- return 0;
+} +#endif
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
- if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
puts("Watchdog: Not found!\n");- } else {
wdt_start(watchdog_dev, 0, 0);puts("Watchdog: Started\n");- }
+# endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif
+#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD)
- static ulong next_reset;
- ulong now;
- if (!watchdog_dev)
return;- now = timer_get_us();
- /* Do not reset the watchdog too often */
- if (now > next_reset) {
wdt_reset(watchdog_dev);next_reset = now + 1000;- }
+# endif
I do have two questions if you don't mind:
1. It seems like a lot of code added to a board file to provide WDT support. Normally we just call a few functions - like hw_watchdog_init(); WATCHDOG_RESET();
2. Is there any good reason for Watchdog_reset not being put into driver, being wrapped, so it would provide WATCHDOG_RESET() macro, which is used to refresh WDT in several places?
+} +#endif
Best regards,
Lukasz Majewski
--
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HI,
2018-02-28 9:55 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Mon, 26 Feb 2018 10:09:55 +0100 Michal Simek michal.simek@xilinx.com wrote:
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL
select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NETdiff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT)
/* bss is not cleared at time when watchdog_reset() iscalled */
watchdog_dev = NULL;+# endif
return 0;+} +#endif
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");} else {wdt_start(watchdog_dev, 0, 0);puts("Watchdog: Started\n");}+# endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif
+#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD)
static ulong next_reset;ulong now;if (!watchdog_dev)return;now = timer_get_us();/* Do not reset the watchdog too often */if (now > next_reset) {wdt_reset(watchdog_dev);next_reset = now + 1000;}+# endif
I do have two questions if you don't mind:
- It seems like a lot of code added to a board file to provide WDT
support. Normally we just call a few functions - like hw_watchdog_init(); WATCHDOG_RESET();
Unfortunately I didn't find a way how to do it with less code. If you see a way to optimize it please let me know. hw_watchdog_init is not using DM. I used similar solution which is used by turris omnia.
Code needs to handle reference to watchdog_dev that's why the code is there.
- Is there any good reason for Watchdog_reset not being put into
driver, being wrapped, so it would provide WATCHDOG_RESET() macro, which is used to refresh WDT in several places?
The reason is that it depends how exactly you want to use it. Also adding dependency on WATCHDOG not WDT is reasonable because you can just start watchdog in u-boot but never service it. It should enable you and option to boot till certain time or reboot. I have tested that this setting is working. I haven't tested if Linux cadence driver can handle it but that's different topic.
Definitely please let me know if you see any issue with this patch.
Thanks, Michal
On Wed, 28 Feb 2018 10:29:24 +0100 Michal Simek monstr@monstr.eu wrote:
HI,
2018-02-28 9:55 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Mon, 26 Feb 2018 10:09:55 +0100 Michal Simek michal.simek@xilinx.com wrote:
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL
select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NETdiff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT)
/* bss is not cleared at time when watchdog_reset() iscalled */
watchdog_dev = NULL;+# endif
return 0;+} +#endif
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");} else {wdt_start(watchdog_dev, 0, 0);puts("Watchdog: Started\n");}+# endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif
+#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD)
static ulong next_reset;ulong now;if (!watchdog_dev)return;now = timer_get_us();/* Do not reset the watchdog too often */if (now > next_reset) {wdt_reset(watchdog_dev);next_reset = now + 1000;}+# endif
I do have two questions if you don't mind:
- It seems like a lot of code added to a board file to provide WDT
support. Normally we just call a few functions - like hw_watchdog_init(); WATCHDOG_RESET();
Unfortunately I didn't find a way how to do it with less code. If you see a way to optimize it please let me know.
I think that the problem is not with the code optimization - I'm a bit concern about reusability.
hw_watchdog_init is not using DM. I used similar solution which is used by turris omnia.
Code needs to handle reference to watchdog_dev that's why the code is there.
- Is there any good reason for Watchdog_reset not being put into
driver, being wrapped, so it would provide WATCHDOG_RESET() macro, which is used to refresh WDT in several places?
The reason is that it depends how exactly you want to use it. Also adding dependency on WATCHDOG not WDT is reasonable because you can just start watchdog in u-boot but never service it.
Isn't this a bit dangerous? For example the end user stop booting the board because wants to upload and flash some data.
During update the not serviced watchdog reset the board and you may end up with brick.
It should enable you and option to boot till certain time or reboot.
You can enable WDT in SPL and "refresh" it in u-boot if needed.
I have tested that this setting is working. I haven't tested if Linux cadence driver can handle it but that's different topic.
There are several options in Linux (with iMX6 at least).
You may disable WDT when driver is correctly setup, refresh it or leave as is, so user space program can take over the WDT control.
Definitely please let me know if you see any issue with this patch.
Thanks, Michal
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi,
2018-02-28 10:42 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Wed, 28 Feb 2018 10:29:24 +0100 Michal Simek monstr@monstr.eu wrote:
HI,
2018-02-28 9:55 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Mon, 26 Feb 2018 10:09:55 +0100 Michal Simek michal.simek@xilinx.com wrote:
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL
select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NETdiff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT)
/* bss is not cleared at time when watchdog_reset() iscalled */
watchdog_dev = NULL;+# endif
return 0;+} +#endif
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");} else {wdt_start(watchdog_dev, 0, 0);puts("Watchdog: Started\n");}+# endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif
+#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD)
static ulong next_reset;ulong now;if (!watchdog_dev)return;now = timer_get_us();/* Do not reset the watchdog too often */if (now > next_reset) {wdt_reset(watchdog_dev);next_reset = now + 1000;}+# endif
I do have two questions if you don't mind:
- It seems like a lot of code added to a board file to provide WDT
support. Normally we just call a few functions - like hw_watchdog_init(); WATCHDOG_RESET();
Unfortunately I didn't find a way how to do it with less code. If you see a way to optimize it please let me know.
I think that the problem is not with the code optimization - I'm a bit concern about reusability.
Probably this code could be move out of board file to more generic location but several things needs to be considered. Especially how to handle system with more watchdogs.
hw_watchdog_init is not using DM. I used similar solution which is used by turris omnia.
Code needs to handle reference to watchdog_dev that's why the code is there.
- Is there any good reason for Watchdog_reset not being put into
driver, being wrapped, so it would provide WATCHDOG_RESET() macro, which is used to refresh WDT in several places?
The reason is that it depends how exactly you want to use it. Also adding dependency on WATCHDOG not WDT is reasonable because you can just start watchdog in u-boot but never service it.
Isn't this a bit dangerous? For example the end user stop booting the board because wants to upload and flash some data.
It is user decision when this should be done. If you do this from Linux it should be fine because Linux service it.
During update the not serviced watchdog reset the board and you may end up with brick.
Depends on your setup and needs. If you have board with only one watchdog when you boot from qspi but reading variables from qspi failed (for whatever reason). it means u-boot ends in prompt watchdog is serviced properly and it will never expire. But in this case this is broken boot. In next reset variable read can be correct.
It should enable you and option to boot till certain time or reboot.
You can enable WDT in SPL and "refresh" it in u-boot if needed.
I didn't try SPL but I will look at it. Again depends on use case you have. Also which board you are using. If you have one or multiple watchdogs. I can imagine if you have 2 watchdogs available that one will cover full boot till linux and one just u-boot issues.
I have tested that this setting is working. I haven't tested if Linux cadence driver can handle it but that's different topic.
There are several options in Linux (with iMX6 at least).
You may disable WDT when driver is correctly setup, refresh it or leave as is, so user space program can take over the WDT control.
I expect this behaviour but I just didn't test that with cadence driver. Also initial u-boot setup can be different compare to OS setup.
Thanks, Michal
Hi Michal,
Hi,
2018-02-28 10:42 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Wed, 28 Feb 2018 10:29:24 +0100 Michal Simek monstr@monstr.eu wrote:
HI,
2018-02-28 9:55 GMT+01:00 Lukasz Majewski lukma@denx.de:
On Mon, 26 Feb 2018 10:09:55 +0100 Michal Simek michal.simek@xilinx.com wrote:
Watchdog is only enabled in full u-boot. Adoption for SPL should be also done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- Make watchdog_reset depends on CONFIG_WATCHDOG not WDT This will handle use cases where watchdog is cleared by OS
arch/arm/Kconfig | 1 + board/xilinx/zynq/board.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a22..a66d04eadfcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL
select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NETdiff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index fb8eab07d768..838ac0f4c4ea 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,11 @@ */
#include <common.h> +#include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) +static struct udevice *watchdog_dev; +#endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ +# if defined(CONFIG_WDT)
/* bss is not cleared at time when watchdog_reset() iscalled */
watchdog_dev = NULL;+# endif
return 0;+} +#endif
int board_init(void) { #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ @@ -75,6 +93,15 @@ int board_init(void) } #endif
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");} else {wdt_start(watchdog_dev, 0, 0);puts("Watchdog: Started\n");}+# endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); @@ -164,3 +191,25 @@ int dram_init(void) return 0; } #endif
+#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ +# if !defined(CONFIG_SPL_BUILD)
static ulong next_reset;ulong now;if (!watchdog_dev)return;now = timer_get_us();/* Do not reset the watchdog too often */if (now > next_reset) {wdt_reset(watchdog_dev);next_reset = now + 1000;}+# endif
I do have two questions if you don't mind:
- It seems like a lot of code added to a board file to provide
WDT support. Normally we just call a few functions - like hw_watchdog_init(); WATCHDOG_RESET();
Unfortunately I didn't find a way how to do it with less code. If you see a way to optimize it please let me know.
I think that the problem is not with the code optimization - I'm a bit concern about reusability.
Probably this code could be move out of board file to more generic location but several things needs to be considered. Especially how to handle system with more watchdogs.
hw_watchdog_init is not using DM. I used similar solution which is used by turris omnia.
Code needs to handle reference to watchdog_dev that's why the code is there.
- Is there any good reason for Watchdog_reset not being put
into driver, being wrapped, so it would provide WATCHDOG_RESET() macro, which is used to refresh WDT in several places?
The reason is that it depends how exactly you want to use it. Also adding dependency on WATCHDOG not WDT is reasonable because you can just start watchdog in u-boot but never service it.
Isn't this a bit dangerous? For example the end user stop booting the board because wants to upload and flash some data.
It is user decision when this should be done. If you do this from Linux it should be fine because Linux service it.
Ok.
During update the not serviced watchdog reset the board and you may end up with brick.
Depends on your setup and needs. If you have board with only one watchdog when you boot from qspi but reading variables from qspi failed (for whatever reason). it means u-boot ends in prompt watchdog is serviced properly and it will never expire.
The most WDT use cases is to reboot when the target device aborts (hangs) at program execution.
( As a remedy one can put reset if bootx fails ).
However, I do get your point.
But in this case this is broken boot. In next reset variable read can be correct.
It should enable you and option to boot till certain time or reboot.
You can enable WDT in SPL and "refresh" it in u-boot if needed.
I didn't try SPL but I will look at it. Again depends on use case you have. Also which board you are using. If you have one or multiple watchdogs. I can imagine if you have 2 watchdogs available that one will cover full boot till linux and one just u-boot issues.
I'm not sure if u-boot now supports two watchdogs in a generic way...
I have tested that this setting is working. I haven't tested if Linux cadence driver can handle it but that's different topic.
There are several options in Linux (with iMX6 at least).
You may disable WDT when driver is correctly setup, refresh it or leave as is, so user space program can take over the WDT control.
I expect this behaviour but I just didn't test that with cadence driver. Also initial u-boot setup can be different compare to OS setup.
Yes, agree. It is use case dependent.
Thanks, Michal
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi,
During update the not serviced watchdog reset the board and you may end up with brick.
Depends on your setup and needs. If you have board with only one watchdog when you boot from qspi but reading variables from qspi failed (for whatever reason). it means u-boot ends in prompt watchdog is serviced properly and it will never expire.
The most WDT use cases is to reboot when the target device aborts (hangs) at program execution.
( As a remedy one can put reset if bootx fails ).
However, I do get your point.
WDT is also wired with sysreset where you can use watchdog ability to reset the system. It can be in case of reset command itself or panic for example.
But it is not only about reboot. On ZynqMP it can be IRQ to different unit on the system.
But in this case this is broken boot. In next reset variable read can be correct.
It should enable you and option to boot till certain time or reboot.
You can enable WDT in SPL and "refresh" it in u-boot if needed.
I didn't try SPL but I will look at it. Again depends on use case you have. Also which board you are using. If you have one or multiple watchdogs. I can imagine if you have 2 watchdogs available that one will cover full boot till linux and one just u-boot issues.
I'm not sure if u-boot now supports two watchdogs in a generic way...
With DM based drivers this should be possible.
I have tested that this setting is working. I haven't tested if Linux cadence driver can handle it but that's different topic.
There are several options in Linux (with iMX6 at least).
You may disable WDT when driver is correctly setup, refresh it or leave as is, so user space program can take over the WDT control.
I expect this behaviour but I just didn't test that with cadence driver. Also initial u-boot setup can be different compare to OS setup.
Yes, agree. It is use case dependent.
Good.
Thanks, Michal
Enable watchdog with reset-on-timeout feature.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v2: None
arch/arm/dts/zynq-zc706.dts | 4 ++++ configs/zynq_zc706_defconfig | 2 ++ 2 files changed, 6 insertions(+)
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index d342306293b4..a88a83c16650 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -333,3 +333,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; + +&watchdog0 { + reset-on-timeout; +}; diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 7b2e072581f6..add40308f6bd 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -70,3 +70,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_WDT=y +CONFIG_WDT_CDNS=y
Hi Michal,
From: Shreenidhi Shedi imshedi@gmail.com
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
If I may ask - what is the purpose of adding separate WATCHDOG symbol?
Cannot HW_WATCHDOG or CONFIG_WDT be reused?
Please look into ULP_WATCHDOG as a reference.
Signed-off-by: Shreenidhi Shedi imshedi@gmail.com Signed-off-by: Michal Simek michal.simek@xilinx.com
Changes in v2:
- s/int32/int/g
- Extend CONFIG_WATCHDOG option to have option to disable it.
drivers/watchdog/Kconfig | 16 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cdns_wdt.c | 276 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 drivers/watchdog/cdns_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index fc46b6774d57..8a66e479ab84 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1,5 +1,13 @@ menu "Watchdog Timer Support"
+config WATCHDOG
- bool "Enable U-Boot watchdog reset"
- help
This option enables U-Boot watchdog support where U-Bootis using
watchdog_reset function to service watchdog device inU-Boot. Enable
this option if you want to service enabled watchdog byU-Boot. Disable
this option if you want U-Boot to start watchdog but neverservice it. + config HW_WATCHDOG bool
@@ -78,4 +86,12 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips.
+config WDT_CDNS
- bool "Cadence watchdog timer support"
- depends on WDT
- imply WATCHDOG
- help
Select this to enable Cadence watchdog timer, which canbe found on some
Xilinx Microzed Platform.endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ab6a6b79e1d7..4b97df3ab67b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o +obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c new file mode 100644 index 000000000000..71733cf8ba1f --- /dev/null +++ b/drivers/watchdog/cdns_wdt.c @@ -0,0 +1,276 @@ +/*
- Cadence WDT driver - Used by Xilinx Zynq
- Reference: Linux kernel Cadence watchdog driver.
- Author(s): Shreenidhi Shedi yesshedi@gmail.com
- SPDX-License-Identifier: GPL-2.0
- */
+#include <common.h> +#include <dm.h> +#include <wdt.h> +#include <clk.h> +#include <linux/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+struct cdns_regs {
- u32 zmr; /* WD Zero mode register, offset - 0x0 */
- u32 ccr; /* Counter Control Register offset - 0x4 */
- u32 restart; /* Restart key register, offset - 0x8 */
- u32 status; /* Status Register, offset - 0xC */
+};
+struct cdns_wdt_priv {
- bool rst;
- u32 timeout;
- void __iomem *reg;
- struct cdns_regs *regs;
+};
+#define CDNS_WDT_DEFAULT_TIMEOUT 10
+/* Supports 1 - 516 sec */ +#define CDNS_WDT_MIN_TIMEOUT 1 +#define CDNS_WDT_MAX_TIMEOUT 516
+/* Restart key */ +#define CDNS_WDT_RESTART_KEY 0x00001999
+/* Counter register access key */ +#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000
+/* Counter value divisor */ +#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
+/* Clock prescaler value and selection */ +#define CDNS_WDT_PRESCALE_64 64 +#define CDNS_WDT_PRESCALE_512 512 +#define CDNS_WDT_PRESCALE_4096 4096 +#define CDNS_WDT_PRESCALE_SELECT_64 1 +#define CDNS_WDT_PRESCALE_SELECT_512 2 +#define CDNS_WDT_PRESCALE_SELECT_4096 3
+/* Input clock frequency */ +#define CDNS_WDT_CLK_75MHZ 75000000
+/* Counter maximum value */ +#define CDNS_WDT_COUNTER_MAX 0xFFF
+/********************* Register Map **********************************/ + +/*
- Zero Mode Register - This register controls how the time out is
indicated
- and also contains the access code to allow writes to the register
(0xABC).
- */
+#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */ +#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */ +#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */ +#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */ +#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */
- +/*
- Counter Control register - This register controls how fast the
timer runs
- and the reset value and also contains the access code to allow
writes to
- the register.
- */
+#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */ + +/* Write access to Registers */ +static inline void cdns_wdt_writereg(u32 *addr, u32 val) +{
- writel(val, addr);
+}
+/**
- cdns_wdt_reset - Reload the watchdog timer (i.e. pat the
watchdog).
- @dev: Watchdog device
- Write the restart key value (0x00001999) to the restart register.
- Return: Always 0
- */
+static int cdns_wdt_reset(struct udevice *dev) +{
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
- debug("%s\n", __func__);
- cdns_wdt_writereg(&priv->regs->restart,
CDNS_WDT_RESTART_KEY); +
- return 0;
+}
+/**
- cdns_wdt_start - Enable and start the watchdog.
- @dev: Watchdog device
- @timeout: Timeout value
- @flags: Driver flags
- The counter value is calculated according to the formula:
count = (timeout * clock) / prescaler + 1.
- The calculated count is divided by 0x1000 to obtain the field
value
- to write to counter control register.
- Clears the contents of prescaler and counter reset value. Sets the
- prescaler to 4096 and the calculated count and access key
- to write to CCR Register.
- Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
- or Interrupt signal(IRQEN) with a specified cycles and the access
- key to write to ZMR Register.
- Return: Upon success 0, failure -1.
- */
+static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
- ulong clk_f;
- u32 count, prescaler, ctrl_clksel, data = 0;
- struct clk clock;
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
- if (clk_get_by_index(dev, 0, &clock) < 0) {
dev_err(dev, "failed to get clock\n");return -1;- }
- clk_f = clk_get_rate(&clock);
- if (IS_ERR_VALUE(clk_f)) {
dev_err(dev, "failed to get rate\n");return -1;- }
- debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f,
timeout); +
- if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
(timeout > CDNS_WDT_MAX_TIMEOUT)) {timeout = priv->timeout;- }
- if (clk_f <= CDNS_WDT_CLK_75MHZ) {
prescaler = CDNS_WDT_PRESCALE_512;ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;- } else {
prescaler = CDNS_WDT_PRESCALE_4096;ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;- }
- /*
* Counter value divisor to obtain the value of* counter reset to be written to control register.*/- count = (timeout * (clk_f / prescaler)) /
CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;- if (count > CDNS_WDT_COUNTER_MAX)
count = CDNS_WDT_COUNTER_MAX;- cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
- count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
- /* Write counter access key first to be able write to
register */
- data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel;
- cdns_wdt_writereg(&priv->regs->ccr, data);
- data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
CDNS_WDT_ZMR_ZKEY_VAL;- /* Reset on timeout if specified in device tree. */
- if (priv->rst) {
data |= CDNS_WDT_ZMR_RSTEN_MASK;data &= ~CDNS_WDT_ZMR_IRQEN_MASK;- } else {
data &= ~CDNS_WDT_ZMR_RSTEN_MASK;data |= CDNS_WDT_ZMR_IRQEN_MASK;- }
- cdns_wdt_writereg(&priv->regs->zmr, data);
- cdns_wdt_writereg(&priv->regs->restart,
CDNS_WDT_RESTART_KEY); +
- return 0;
+}
+/**
- cdns_wdt_stop - Stop the watchdog.
- @dev: Watchdog device
- Read the contents of the ZMR register, clear the WDEN bit in the
register
- and set the access key for successful write.
- Return: Always 0
- */
+static int cdns_wdt_stop(struct udevice *dev) +{
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
- cdns_wdt_writereg(&priv->regs->zmr,
CDNS_WDT_ZMR_ZKEY_VAL &(~CDNS_WDT_ZMR_WDEN_MASK)); +
- return 0;
+}
+/**
- cdns_wdt_probe - Probe call for the device.
- @dev: Handle to the udevice structure.
- Return: Always 0.
- */
+static int cdns_wdt_probe(struct udevice *dev) +{
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
- debug("%s: Probing wdt%u\n", __func__, dev->seq);
- priv->reg = ioremap((u32)priv->regs, sizeof(struct
cdns_regs)); +
- cdns_wdt_stop(dev);
- return 0;
+}
+static int cdns_wdt_ofdata_to_platdata(struct udevice *dev) +{
- int node = dev_of_offset(dev);
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
- priv->regs = devfdt_get_addr_ptr(dev);
- if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);- priv->timeout = fdtdec_get_int(gd->fdt_blob, node,
"timeout-sec",
CDNS_WDT_DEFAULT_TIMEOUT);- priv->rst = fdtdec_get_bool(gd->fdt_blob, node,
"reset-on-timeout"); +
- debug("%s: timeout %d, reset %d\n", __func__, priv->timeout,
priv->rst); +
- return 0;
+}
+static const struct wdt_ops cdns_wdt_ops = {
- .start = cdns_wdt_start,
- .reset = cdns_wdt_reset,
- .stop = cdns_wdt_stop,
+};
+static const struct udevice_id cdns_wdt_ids[] = {
- { .compatible = "cdns,wdt-r1p2" },
- {}
+};
+U_BOOT_DRIVER(cdns_wdt) = {
- .name = "cdns_wdt",
- .id = UCLASS_WDT,
- .of_match = cdns_wdt_ids,
- .probe = cdns_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
- .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
- .ops = &cdns_wdt_ops,
+};
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi,
2018-02-28 9:51 GMT+01:00 Lukasz Majewski lukma@denx.de:
Hi Michal,
From: Shreenidhi Shedi imshedi@gmail.com
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
If I may ask - what is the purpose of adding separate WATCHDOG symbol?
Cannot HW_WATCHDOG or CONFIG_WDT be reused?
Please look into ULP_WATCHDOG as a reference.
ULP_WATCHDOG hasn't been converted to DM that's why you use hw_watchdog wiring.
CONFIG_WDT is used for enabling watchdog uclass. CONFIG_WDT_CDNS - for enabling cadence DM watchdog driver CONFIG_WATCHDOG - for servicing watchdog by u-boot
It means there are some dependencies - WDT_CDNS depends on WDT. And WATCHDOG doesn't need to be enabled which depends on your setting which is described in Kconfig symbol.
Thanks, Michal
Hi Michal,
Hi,
2018-02-28 9:51 GMT+01:00 Lukasz Majewski lukma@denx.de:
Hi Michal,
From: Shreenidhi Shedi imshedi@gmail.com
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
If I may ask - what is the purpose of adding separate WATCHDOG symbol?
Cannot HW_WATCHDOG or CONFIG_WDT be reused?
Please look into ULP_WATCHDOG as a reference.
ULP_WATCHDOG hasn't been converted to DM that's why you use hw_watchdog wiring.
CONFIG_WDT is used for enabling watchdog uclass. CONFIG_WDT_CDNS - for enabling cadence DM watchdog driver CONFIG_WATCHDOG - for servicing watchdog by u-boot
^^^^^^^^^ - I'm just wondering about this one. How does it corresponds to CONFIG_HW_WATCHDOG?
It means there are some dependencies - WDT_CDNS depends on WDT. And WATCHDOG doesn't need to be enabled which depends on your setting which is described in Kconfig symbol.
Thanks, Michal
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
HI,
2018-02-28 12:06 GMT+01:00 Lukasz Majewski lukma@denx.de:
Hi Michal,
Hi,
2018-02-28 9:51 GMT+01:00 Lukasz Majewski lukma@denx.de:
Hi Michal,
From: Shreenidhi Shedi imshedi@gmail.com
This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
If I may ask - what is the purpose of adding separate WATCHDOG symbol?
Cannot HW_WATCHDOG or CONFIG_WDT be reused?
Please look into ULP_WATCHDOG as a reference.
ULP_WATCHDOG hasn't been converted to DM that's why you use hw_watchdog wiring.
CONFIG_WDT is used for enabling watchdog uclass. CONFIG_WDT_CDNS - for enabling cadence DM watchdog driver CONFIG_WATCHDOG - for servicing watchdog by u-boot
^^^^^^^^^ - I'm just wondering about this one. How does it corresponds to CONFIG_HW_WATCHDOG?
include/watchdog.h
32 #if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG) 33 # error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together." 34 #endif
HW_WATCHDOG - non DM drivers, WATCHDOG DM drivers.
M
participants (3)
-
Lukasz Majewski -
Michal Simek -
Michal Simek