NXP used to setup the gpmi clock root from gpmi_clk in early versions in their downstream BSP. [1] However on mainline the gpmi clock root was always setup from enfc since the beginning of the i.MX 6 series SoCs, which is still the same today. [2]

NXP followed the mainline approach at some point and changed setup_gpmi_io_clk to setup gpmi clock root from enfc which left faulty code behind in our board file. [3]

This commit follows the change of NXP as it improves the performance of the NAND from ~1.2 MiB/s to ~12 MiB/s. [3]

This change was verified to work in recovery-mode and u-boot loaded from NAND on all four Colibri iMX6ULL SKUs from Toradex.

The frequency used to read the NAND, measured on RE# (Read Enable): before this patch: 1.4 MHz after this patch: 22 MHz in Linux Kernel: 50 MHz

[1] https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/cpu/armv7... [2] commit 23608e23fd65 ("i.mx: add the initial support for freescale i.MX6Q processor") [3] https://source.codeaurora.org/external/imx/uboot-imx/commit/?id=7a82a19ceabf...

Signed-off-by: Philippe Schenker philippe.schenker@toradex.com

---

board/toradex/colibri-imx6ull/colibri-imx6ull.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 01f5561596..fd54688272 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -53,8 +53,9 @@ int dram_init(void) #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { - setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | - (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); } #endif /* CONFIG_NAND_MXS */