I am trying to port uboot on our own board running mpc8541E processor. Have all the board specfic stuff created and compiled in, did face a few issues early on, but right now it seem like it goes all the way till board_init_f and hangs. Bactracking through the startup code I see that my LBC register have not been initialized. I have the following settings in my board.config file

#define CFG_BR0_PRELIM 0xFE001801 #define CFG_OR0_PRELIM 0xFE006F35

2 * 16MB interleaved flashes configured on CS0

CCSRBAR config:

#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */

It does go through cpu_init_f with no exections etc but If I set a breakpoint or stop it at some later point and look at the OR0/BRO registes I do not see the above values being set. I am not quite sure how the CCSRBAR reloacation code in start.S seems to handle the relocation

I do see that we go through this part in the the debugger.

#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* Special sequence needed to update CCSRBAR itself */ lis r4, CFG_CCSRBAR_DEFAULT@h ori r4, r4, CFG_CCSRBAR_DEFAULT@l

lis r5, CFG_CCSRBAR@h ori r5, r5, CFG_CCSRBAR@l srwi r6,r5,12 stw r6, 0(r4) isync

lis r5, 0xffff ori r5,r5,0xf000 lwz r5, 0(r5) isync

lis r3, CFG_CCSRBAR@h lwz r5, CFG_CCSRBAR@l(r3) isync #endif

I was wondering if these two variables are being set properly

volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc;

since the statment below in cpu_init_f does not seem to take effect.

memctl->br0 = CFG_BR0_PRELIM; memctl->or0 = CFG_OR0_PRELIM;

I'd really appreciate any replies or suggestions.

thanks much, Rahul

TLB config below:

/* * TLB0 and TLB1 Entries * * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. * However, CCSRBAR is then relocated to CFG_CCSRBAR right after * these TLB entries are established. * * MAS0: tlbsel, esel, nv * MAS1: valid, iprot, tid, ts, tsize * MAS2: epn, sharen, x0, x1, w, i, m, g, e * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr */

#define entry_start \ mflr r1 ; \ bl 0f ;

#define entry_end \ 0: mflr r0 ; \ mtlr r1 ; \ blr ;

.section .bootpg, "ax" .globl tlb1_entry tlb1_entry: entry_start

/* * Number of TLB0 and TLB1 entries in the following table */ .long 13

#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* * TLB0 4K Non-cacheable, guarded * 0xff700000 4K Initial CCSRBAR mapping * * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) #else #error("Update the number of table entries in tlb1_entry") #endif

/* * TLB0 16K Cacheable, non-guarded * 0xd001_0000 16K Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory * controler and real memory have been configured. * * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)

.long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1)

.long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1)

.long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 0, 1: 32M Non-cacheable, guarded * 0xfe000000 32FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)

.long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 3: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 4: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 5: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 6: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 7: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ .long TLB1_MAS0(1, 7, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)

/* * TLB 8: 256M DDR, cache disabled (needed for memory test) * 0x00000000 256M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ .long TLB1_MAS0(1, 8, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)

entry_end

/* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G * 0xe000_0000 0xe000_ffff CCSR 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */

#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))

#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))

#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))

#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))

/* * Rapid IO at 0xc000_0000 for 512 M */ #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))

.section .bootpg, "ax" .globl law_entry law_entry: entry_start .long 0x05 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 .long LAWBAR4,LAWAR4 entry_end