Re: [U-Boot-Users] [RFC][FSL DDR 0/8] Freescale DDR rewrit
Kumar Gala-3 wrote:
This is a series of patches that are a work-in-progress towards a new DDR initialization for the Freescale 8{3,5,6}xxx devices that have a common DDR controller.
(Sorry for the previous "no subject" message - hit the "send" too soon...) Kumar, Does this RFC also include support for identifying and initializing more than one DDR module? David.
On Jul 6, 2008, at 3:04 AM, David Saada wrote:
Kumar Gala-3 wrote:
This is a series of patches that are a work-in-progress towards a new DDR initialization for the Freescale 8{3,5,6}xxx devices that have a common DDR controller.
(Sorry for the previous "no subject" message - hit the "send" too soon...) Kumar, Does this RFC also include support for identifying and initializing more than one DDR module?
I'm not sure I follow exactly what you are asking? Do you mean using different DDR modules on different chip selects of the same controller? or something else?
- k
<Does this RFC also include support for identifying and initializing < more than one DDR module?
I'm not sure I follow exactly what you are asking? Do you mean using different DDR modules on different chip selects of the same controller? or something else?
- k
Kumar - the current SPD DDR code assumes a single DIMM with a single fixed I2C address. Does your RFC add support for more than one DIMM on the same controller?
Yes, it should.
jdl
John - thanks, just wanted to elaborate to receive Kumar's ack.
Thanks, David.
On Jul 8, 2008, at 2:32 AM, David Saada wrote:
<Does this RFC also include support for identifying and initializing < more than one DDR module?
I'm not sure I follow exactly what you are asking? Do you mean using different DDR modules on different chip selects of the same controller? or something else?
- k
Kumar - the current SPD DDR code assumes a single DIMM with a single fixed I2C address. Does your RFC add support for more than one DIMM on the same controller?
Yes it should. The 8641 HPCN has 2-dimm slots per controller and both dimm slots are supported.
- k
<Does this RFC also include support for identifying and initializing < more than one DDR module?
I'm not sure I follow exactly what you are asking? Do you mean using different DDR modules on different chip selects of the same controller? or something else?
- k
Kumar - the current SPD DDR code assumes a single DIMM with a single fixed I2C address. Does your RFC add support for more than one DIMM on the same controller?
Yes it should. The 8641 HPCN has 2-dimm slots per controller and both dimm slots are supported.
- k
OK Thanks. David.
participants (2)
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David Saada -
Kumar Gala