[U-Boot] [PATCH] ARM: atmel: switch to usb ehci for sama5d3 boards
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com ---
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..0dab15d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,17 +20,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -95,13 +84,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..d3ab6e4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -24,17 +24,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR16 @@ -128,13 +117,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif
Hi,
On 19-05-15 12:54, Josh Wu wrote:
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com
I'm confused now, with the patch you just send the ohci code should work, right? And this way usb-1 devices like keyboards will not work, otoh you will get faster usb storage support.
What you should really do is convert the atmel usb glue to support the u-boot driver model and move to that, then you can build in both the ohci and ehci drivers and get the best of both worlds.
I've already done so for sunxi, ironing out all the handover bugs in the usb core and ehci code, paving the way for you :)
Regards,
Hans
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..0dab15d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,17 +20,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/*
- This needs to be defined for the OHCI code to work but it is defined as
- ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-/*
- Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
- /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
@@ -95,13 +84,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..d3ab6e4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -24,17 +24,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/*
- This needs to be defined for the OHCI code to work but it is defined as
- ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-/*
- Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
- /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR16
@@ -128,13 +117,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif
Hi, Hans
On 5/19/2015 6:57 PM, Hans de Goede wrote:
Hi,
On 19-05-15 12:54, Josh Wu wrote:
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com
I'm confused now, with the patch you just send the ohci code should work, right?
Right. I forget to amend the commit message. Sorry.
And this way usb-1 devices like keyboards will not work, otoh you will get faster usb storage support.
I didn't test the keyboard yet. Good to know this. thanks.
What you should really do is convert the atmel usb glue to support the u-boot driver model and move to that, then you can build in both the ohci and ehci drivers and get the best of both worlds.
Ok, that sounds nice.
I've already done so for sunxi, ironing out all the handover bugs in the usb core and ehci code, paving the way for you :)
Indeed, it seems convert to DM is the right way. Ok, I will do it. Thanks again.
Best Regards, Josh Wu
Regards,
Hans
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..0dab15d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,17 +20,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/*
- This needs to be defined for the OHCI code to work but it is
defined as
- ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-/*
- Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
- /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
@@ -95,13 +84,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..d3ab6e4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -24,17 +24,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU
-/*
- This needs to be defined for the OHCI code to work but it is
defined as
- ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-/*
- Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
- /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR16
@@ -128,13 +117,9 @@ #define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif
Dear "Wu, Josh",
Josh Wu Josh.wu@atmel.com writes:
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards, Andreas Bießmann
Hi Josh,
On 08/18/2015 01:46 PM, Andreas Bießmann wrote:
Dear "Wu, Josh",
Josh Wu Josh.wu@atmel.com writes:
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
applied to u-boot-atmel/master, thanks!
just saw the mails from Hans. I removed this patch again from u-boot-atmel/master. The USB-DM changes seems to be the better way and since the OHCI driver is fixed we should stay there.
Andreas
Hi, Andreas
On 8/18/2015 9:04 PM, Andreas Bießmann wrote:
Hi Josh,
On 08/18/2015 01:46 PM, Andreas Bießmann wrote:
Dear "Wu, Josh",
Josh Wu Josh.wu@atmel.com writes:
From: Bo Shen voice.shen@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.shen@atmel.com [rebase to mainline] Signed-off-by: Josh Wu josh.wu@atmel.com
include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-)
applied to u-boot-atmel/master, thanks!
just saw the mails from Hans. I removed this patch again from u-boot-atmel/master.
Yes, that's right.
The USB-DM changes seems to be the better way and since the OHCI driver is fixed we should stay there.
For the DM switch, I think the pinctrl dt support might be a big task. I've done the spi dm support on at91sam9m10g45ek. But as the pins configuration from dt is not support. So I just hard coded the pin configuration. I may send it out for review in future.
Best Regards, Josh Wu
Andreas
participants (3)
-
Andreas Bießmann -
Hans de Goede -
Josh Wu