[U-Boot] [PATCH 0/6] x86: Add some peripherals support to Intel Galileo
This series adds GPIO, SPI and SD/MMC support to Intel Galileo board. Intel's chipset controllers are normally compatible so that we can easily add peripherals support via existing drivers with minor modification.
Note this series depends on previous two series: series#1: http://patchwork.ozlabs.org/patch/435526/ series#2: http://patchwork.ozlabs.org/patch/435816/
With this patch series, the only left interfaces on Galileo board to be enabled are USB, 10/100M Ethernet and mini-PCIe.
Bin Meng (6): x86: quark: Initialize non-standard BARs x86: galileo: Add GPIO support x86: pci: Add pci ids for Quark SoC x86: Add SPI support to quark/galileo x86: Add SD/MMC support to quark/galileo x86: Add Intel Galileo instructions in README.x86
arch/x86/cpu/quark/quark.c | 74 +++++++++++++++++++++++++++++++++ arch/x86/dts/galileo.dts | 27 ++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 32 ++++++++++++++ doc/README.x86 | 24 +++++++++-- drivers/spi/ich.c | 3 +- include/configs/galileo.h | 7 ++++ include/pci_ids.h | 4 ++ 7 files changed, 166 insertions(+), 5 deletions(-)
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/quark/quark.c | 46 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 32 +++++++++++++++++++++++ 2 files changed, 78 insertions(+)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 47ba152..cf596e4 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -9,6 +9,46 @@ #include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> +#include <asm/arch/device.h> +#include <asm/arch/msg_port.h> +#include <asm/arch/quark.h> + +static void quark_setup_bars(void) +{ + /* GPIO - D31:F0:R44h */ + pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, + CONFIG_GPIO_BASE | IO_BAR_EN); + + /* ACPI PM1 Block - D31:F0:R48h */ + pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, + CONFIG_ACPI_PM1_BASE | IO_BAR_EN); + + /* GPE0 - D31:F0:R4Ch */ + pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, + CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); + + /* WDT - D31:F0:R84h */ + pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, + CONFIG_WDT_BASE | IO_BAR_EN); + + /* RCBA - D31:F0:RF0h */ + pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, + CONFIG_RCBA_BASE | MEM_BAR_EN); + + /* ACPI P Block - Msg Port 04:R70h */ + msg_port_write(MSG_PORT_RMU, PBLK_BA, + CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); + + /* SPI DMA - Msg Port 04:R7Ah */ + msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, + CONFIG_SPI_DMA_BASE | IO_BAR_EN); + + /* PCIe ECAM */ + msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, + CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); + msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, + CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); +}
int arch_cpu_init(void) { @@ -28,6 +68,12 @@ int arch_cpu_init(void) if (ret) return ret;
+ /* + * Quark SoC has some non-standard BARs (excluding PCI standard BARs) + * which need be initialized with suggested values + */ + quark_setup_bars(); + return 0; }
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index ebbcf77..ceb583e 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -14,9 +14,29 @@ #define MSG_PORT_MEM_MGR 0x05 #define MSG_PORT_SOC_UNIT 0x31
+/* Port 0x00: Memory Arbiter Message Port Registers */ + +/* Enhanced Configuration Space */ +#define AEC_CTRL 0x00 + +/* Port 0x03: Host Bridge Message Port Registers */ + /* Host Memory I/O Boundary */ #define HM_BOUND 0x08
+/* Extended Configuration Space */ +#define HEC_REG 0x09 + +/* Port 0x04: Remote Management Unit Message Port Registers */ + +/* ACPI PBLK Base Address Register */ +#define PBLK_BA 0x70 + +/* SPI DMA Base Address Register */ +#define SPI_DMA_BA 0x7a + +/* Port 0x05: Memory Manager Message Port Registers */ + /* eSRAM Block Page Control */ #define ESRAM_BLK_CTRL 0x82 #define ESRAM_BLOCK_MODE 0x10000000 @@ -37,4 +57,16 @@ /* 64KiB of RMU binary in flash */ #define RMU_BINARY_SIZE 0x10000
+/* Legacy Bridge PCI Configuration Registers */ +#define LB_GBA 0x44 +#define LB_PM1BLK 0x48 +#define LB_GPE0BLK 0x4c +#define LB_ACTL 0x58 +#define LB_PABCDRC 0x60 +#define LB_PEFGHRC 0x64 +#define LB_WDTBA 0x84 +#define LB_BCE 0xd4 +#define LB_BC 0xd8 +#define LB_RCBA 0xf0 + #endif /* _QUARK_H_ */
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 46 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 32 +++++++++++++++++++++++ 2 files changed, 78 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 46 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 32 +++++++++++++++++++++++ 2 files changed, 78 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/dts/galileo.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index d462221..2f60aeb 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -65,4 +65,18 @@ }; };
+ gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + };
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/galileo.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/galileo.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
Add pci ids for Intel Quark SoC.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h index 1012abe..dc2ca21 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2592,6 +2592,10 @@ #define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823 #define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824 #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F +#define PCI_DEVICE_ID_INTEL_QRK_SDIO 0x08A7 +#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 +#define PCI_DEVICE_ID_INTEL_QRK_EMAC 0x0937 +#define PCI_DEVICE_ID_INTEL_QRK_ILB 0x095E #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Add pci ids for Intel Quark SoC.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Add pci ids for Intel Quark SoC.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/quark/quark.c | 17 +++++++++++++++++ arch/x86/dts/galileo.dts | 13 +++++++++++++ drivers/spi/ich.c | 3 ++- 3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index cf596e4..0d593d9 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -13,6 +13,21 @@ #include <asm/arch/msg_port.h> #include <asm/arch/quark.h>
+/* + * TODO: + * + * This whole routine should be removed until we fully convert the ICH SPI + * driver to DM and make use of DT to pass the bios control register offset + */ +static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); +} + static void quark_setup_bars(void) { /* GPIO - D31:F0:R44h */ @@ -74,6 +89,8 @@ int arch_cpu_init(void) */ quark_setup_bars();
+ unprotect_spi_flash(); + return 0; }
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2f60aeb..66af64a 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -79,4 +79,17 @@ bank-name = "B"; };
+ spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + }; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index da85779..194e882 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -177,7 +177,8 @@ void spi_free_slave(struct spi_slave *slave) static int get_ich_version(uint16_t device_id) { if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || - device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) + device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || + device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) return 7;
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 17 +++++++++++++++++ arch/x86/dts/galileo.dts | 13 +++++++++++++ drivers/spi/ich.c | 3 ++- 3 files changed, 32 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 17 +++++++++++++++++ arch/x86/dts/galileo.dts | 13 +++++++++++++ drivers/spi/ich.c | 3 ++- 3 files changed, 32 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/quark/quark.c | 11 +++++++++++ include/configs/galileo.h | 7 +++++++ 2 files changed, 18 insertions(+)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 0d593d9..dccf7ac 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <mmc.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/post.h> @@ -13,6 +14,10 @@ #include <asm/arch/msg_port.h> #include <asm/arch/quark.h>
+static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, +}; + /* * TODO: * @@ -105,3 +110,9 @@ void reset_cpu(ulong addr) /* cold reset */ outb(0x08, PORT_RESET); } + +int cpu_mmc_init(bd_t *bis) +{ + return pci_mmc_init("Quark SDHCI", mmc_supported, + ARRAY_SIZE(mmc_supported)); +} diff --git a/include/configs/galileo.h b/include/configs/galileo.h index bead2fc..d745f4e 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -50,4 +50,11 @@ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE
+/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + #endif /* __CONFIG_H */
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 11 +++++++++++ include/configs/galileo.h | 7 +++++++ 2 files changed, 18 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/quark.c | 11 +++++++++++ include/configs/galileo.h | 7 +++++++ 2 files changed, 18 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
Add some instructions about building U-Boot for Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
doc/README.x86 | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86 index c699b79..fb87682 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -18,8 +18,8 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link on other x86 boards since coreboot deals with most of the low-level details.
U-Boot also supports booting directly from x86 reset vector without coreboot, -aka raw support or bare support. Currently Link, Intel Crown Bay and Intel -Minnowboard Max support running U-Boot 'bare metal'. +aka raw support or bare support. Currently Link, Intel Crown Bay, Intel +Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'.
As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit Linux kernel as part of a FIT image. It also supports a compressed zImage. @@ -110,7 +110,6 @@ Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all
- Intel Minnowboard Max instructions:
This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. @@ -136,6 +135,24 @@ Now you can build U-Boot and obtain u-boot.rom $ make minnowmax_defconfig $ make all
+Intel Galileo instructions: + +Only one binary blob is needed for Remote Management Unit (RMU) within Intel +Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is +needed by the Quark SoC itself. + +You can get the binary blob from Quark Board Support Package from Intel website: + +* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin + +Rename the file and put it to the board directory by: + + $ cp RMU.bin board/intel/galileo/rmu.bin + +Now you can build U-Boot and obtain u-boot.rom + +$ make galileo_defconfig +$ make all
Test with coreboot ------------------ @@ -203,7 +220,6 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
Development Flow ---------------- - These notes are for those who want to port U-Boot to a new x86 platform.
Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Add some instructions about building U-Boot for Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
doc/README.x86 | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 4 February 2015 at 20:26, Simon Glass sjg@chromium.org wrote:
On 4 February 2015 at 01:26, Bin Meng bmeng.cn@gmail.com wrote:
Add some instructions about building U-Boot for Intel Galileo board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
doc/README.x86 | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!
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