[U-Boot] [PATCH] libfdt: use CONFIG_IS_ENABLED for OF_LIBFDT
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com --- lib/fdtdec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 81f47ef2c7f4..269226e0ef15 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -112,7 +112,7 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, return FDT_ADDR_T_NONE; }
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_LIBFDT) +#if CONFIG_IS_ENABLED(OF_LIBFDT) if (translate) addr = fdt_translate_address(blob, node, prop_addr); else
2017-02-13 16:34 GMT+09:00 Vignesh R vigneshr@ti.com:
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Masahiro Yamada yamada.masahiro@socionext.com
On Monday 13 February 2017 01:04 PM, Vignesh R wrote:
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
Hi,
On 13 February 2017 at 01:08, Lokesh Vutla lokeshvutla@ti.com wrote:
On Monday 13 February 2017 01:04 PM, Vignesh R wrote:
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
Unfortunately this breaks boards which use SPL and OF_CONTROL:
06: dtoc: make ScanTree recurse into subnodes aarch64: + xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zcu102 xilinx_zynqmp_zc1751_xm015_dc1 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zc1751_xm016_dc2 xilinx_zynqmp_ep xilinx_zynqmp_zcu102_revB arm: + socfpga_de0_nano_soc uniphier_pro4 uniphier_ld4_sld8 zynq_zc770_xm010 zynq_zc770_xm012 zynq_zc706 evb-rk3288 socfpga_arria5 zynq_zybo rock2 socfpga_socrates uniphier_sld3 zynq_microzed socfpga_sr1500 tinker-rk3288 zynq_zed socfpga_de1_soc firefly-rk3288 sama5d2_xplained_spiflash topic_miami sama5d2_xplained_mmc socfpga_sockit zynq_zc702 socfpga_is1 zynq_picozed fennec-rk3288 zynq_zc770_xm011 zynq_zc770_xm013 popmetal-rk3288 socfpga_mcvevk topic_miamiplus socfpga_cyclone5 socfpga_vining_fpga uniphier_pxs2_ld6b microblaze: + microblaze-generic x86: + qemu-x86_64 chromebook_link64 +lib/built-in.o: In function `fdtdec_get_addr_size_fixed': +build/../lib/fdtdec.c:117: undefined reference to `fdt_translate_address' +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +build/../lib/fdtdec.
You can move the position of fdt_support.o in common/Makefile to fix this.
It also bloats SPL on many boards which currently don't need address translation. For example firefly-rk3288 goes from ~20KB to ~26KB.
Can you add an option to enable address translation in SPL perhaps? Then it will be disabled by default on existing boards.
Regards, Simon
On Fri, Mar 17, 2017 at 12:46:17PM -0600, Simon Glass wrote:
Hi,
On 13 February 2017 at 01:08, Lokesh Vutla lokeshvutla@ti.com wrote:
On Monday 13 February 2017 01:04 PM, Vignesh R wrote:
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
Unfortunately this breaks boards which use SPL and OF_CONTROL:
06: dtoc: make ScanTree recurse into subnodes aarch64: + xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zcu102 xilinx_zynqmp_zc1751_xm015_dc1 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zc1751_xm016_dc2 xilinx_zynqmp_ep xilinx_zynqmp_zcu102_revB arm: + socfpga_de0_nano_soc uniphier_pro4 uniphier_ld4_sld8 zynq_zc770_xm010 zynq_zc770_xm012 zynq_zc706 evb-rk3288 socfpga_arria5 zynq_zybo rock2 socfpga_socrates uniphier_sld3 zynq_microzed socfpga_sr1500 tinker-rk3288 zynq_zed socfpga_de1_soc firefly-rk3288 sama5d2_xplained_spiflash topic_miami sama5d2_xplained_mmc socfpga_sockit zynq_zc702 socfpga_is1 zynq_picozed fennec-rk3288 zynq_zc770_xm011 zynq_zc770_xm013 popmetal-rk3288 socfpga_mcvevk topic_miamiplus socfpga_cyclone5 socfpga_vining_fpga uniphier_pxs2_ld6b microblaze: + microblaze-generic x86: + qemu-x86_64 chromebook_link64 +lib/built-in.o: In function `fdtdec_get_addr_size_fixed': +build/../lib/fdtdec.c:117: undefined reference to `fdt_translate_address' +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +build/../lib/fdtdec.
You can move the position of fdt_support.o in common/Makefile to fix this.
It also bloats SPL on many boards which currently don't need address translation. For example firefly-rk3288 goes from ~20KB to ~26KB.
Can you add an option to enable address translation in SPL perhaps? Then it will be disabled by default on existing boards.
Does that include when we use gcc-6.x and are able to discard all of the unused strings (which is I assume what's bloating things) ? At some point we will need to say that SoC $X/$Y/$Z only work with gcc-6.x and later due to size issues. Not that we're strictly at that point yet, and may indeed want to fix this by moving functions around to allow for the older toolchains to be able to discard the strings.
On Saturday 18 March 2017 12:16 AM, Simon Glass wrote:
Hi,
On 13 February 2017 at 01:08, Lokesh Vutla lokeshvutla@ti.com wrote:
On Monday 13 February 2017 01:04 PM, Vignesh R wrote:
Use CONFIG_IS_ENABLED() macro to check whether OF_LIBFDT is enabled, so that code block is compiled irrespective of SPL or U-Boot build depending on CONFIG_SPL_OF_LIBFDT(for SPL) or CONFIG_OF_LIBFDT(for U-Boot).
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
Unfortunately this breaks boards which use SPL and OF_CONTROL:
06: dtoc: make ScanTree recurse into subnodes aarch64: + xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zcu102 xilinx_zynqmp_zc1751_xm015_dc1 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zc1751_xm016_dc2 xilinx_zynqmp_ep xilinx_zynqmp_zcu102_revB arm: + socfpga_de0_nano_soc uniphier_pro4 uniphier_ld4_sld8 zynq_zc770_xm010 zynq_zc770_xm012 zynq_zc706 evb-rk3288 socfpga_arria5 zynq_zybo rock2 socfpga_socrates uniphier_sld3 zynq_microzed socfpga_sr1500 tinker-rk3288 zynq_zed socfpga_de1_soc firefly-rk3288 sama5d2_xplained_spiflash topic_miami sama5d2_xplained_mmc socfpga_sockit zynq_zc702 socfpga_is1 zynq_picozed fennec-rk3288 zynq_zc770_xm011 zynq_zc770_xm013 popmetal-rk3288 socfpga_mcvevk topic_miamiplus socfpga_cyclone5 socfpga_vining_fpga uniphier_pxs2_ld6b microblaze: + microblaze-generic x86: + qemu-x86_64 chromebook_link64 +lib/built-in.o: In function `fdtdec_get_addr_size_fixed': +build/../lib/fdtdec.c:117: undefined reference to `fdt_translate_address' +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +build/../lib/fdtdec.
You can move the position of fdt_support.o in common/Makefile to fix this.
It also bloats SPL on many boards which currently don't need address translation. For example firefly-rk3288 goes from ~20KB to ~26KB.
Can you add an option to enable address translation in SPL perhaps?
Yes, there is OF_TRANSLATE. I have posted v2 with the changes: https://patchwork.ozlabs.org/patch/740789/
participants (5)
-
Lokesh Vutla -
Masahiro Yamada -
Simon Glass -
Tom Rini -
Vignesh R