[U-Boot] U-Boot 2012.10 - pxa270 CPU Unknown / no turbo
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, inactive) [ 0.000000] Memory clock: 104.00MHz (/2) [ 0.000000] System bus clock: 104.00MHz
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 207.66 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 0000000000000000
With an old uboot from a third party vendor its working fine and the boot time is about half with the latest stable u-boot.
U-Boot 2010.06-dirty CPU speed: 520000kHz; RCSR 00000001
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, active) [ 0.000000] Memory clock: 208.00MHz (/2) [ 0.000000] System bus clock: 208.00MHz
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 519.37 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 00003600602d1400
Uboot-2012.10 was compiled with stock files and no modification.
Kind regards Andreas
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, inactive) [ 0.000000] Memory clock: 104.00MHz (/2) [ 0.000000] System bus clock: 104.00MHz
Looks like you need to enable the "Turbo" bit, patch is welcome. See arch/arm/cpu/pxa/start.S and arch/arm/cpu/pxa/pxa2xx.c
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 207.66 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 0000000000000000
With an old uboot from a third party vendor its working fine and the boot time is about half with the latest stable u-boot.
U-Boot 2010.06-dirty CPU speed: 520000kHz; RCSR 00000001
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, active) [ 0.000000] Memory clock: 208.00MHz (/2) [ 0.000000] System bus clock: 208.00MHz
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 519.37 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 00003600602d1400
Uboot-2012.10 was compiled with stock files and no modification.
Kind regards Andreas
Best regards, Marek Vasut
Dear Marek Vasut,
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
Yes, its a PXA270 M. There is a spec. update pdf from Marvel. http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec... - Table 2-3.
They changed the Stepping from A0...C5 to "PXA270M -- A1" A colleague would support me to change this becouse i have no cloue about writing C Files. So we would like ask you first if the right CPU Name should be shown in the summary screen which would be a rewrite of your function or only the right stepping with the old CPU Name would be enough ? (Damn it - hope you understand my Denglish)
first lines of dmesg: [ 0.000000] CPU: XScale-PXA270 [69054118] revision 8 (ARMv5TE), cr=0000397f [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Toradex Colibri PXA270 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] Run Mode clock: 208.00MHz (*16) [ 0.000000] Turbo Mode clock: 520.00MHz (*2.5, inactive) [ 0.000000] Memory clock: 104.00MHz (/2) [ 0.000000] System bus clock: 104.00MHz
Looks like you need to enable the "Turbo" bit, patch is welcome. See arch/arm/cpu/pxa/start.S and arch/arm/cpu/pxa/pxa2xx.c
Thank you for the files where we can look up. We will try.
$ cat /proc/cpuinfo Processor : XScale-PXA270 rev 8 (v5l) BogoMIPS : 207.66 Features : swp half thumb fastmult edsp iwmmxt CPU implementer : 0x69 CPU architecture: 5TE CPU variant : 0x0 CPU part : 0x411 CPU revision : 8
Hardware : Toradex Colibri PXA270 Revision : 0000 Serial : 0000000000000000
[...] Kind regards Andreas
Best regards, Marek Vasut
Kind regards Andreas
Dear Andreas Puls,
Dear Marek Vasut,
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
Yes, its a PXA270 M. There is a spec. update pdf from Marvel. http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spe c_update.pdf - Table 2-3.
They changed the Stepping from A0...C5 to "PXA270M -- A1" A colleague would support me to change this becouse i have no cloue about writing C Files. So we would like ask you first if the right CPU Name should be shown in the summary screen which would be a rewrite of your function or only the right stepping with the old CPU Name would be enough ? (Damn it - hope you understand my Denglish)
Can the CPUs be distinguished in some deterministic way? If so, rewrite it, no problem.
[...]
Best regards, Marek Vasut
Dear Marek Vasut,
Dear Andreas Puls,
Dear Marek Vasut,
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
Yes, its a PXA270 M. There is a spec. update pdf from Marvel.
http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spe
c_update.pdf - Table 2-3.
They changed the Stepping from A0...C5 to "PXA270M -- A1" A colleague would support me to change this becouse i have no cloue
about
writing C Files. So we would like ask you first if the right CPU Name should be shown in the summary screen which would be a rewrite of your function or only the right stepping with the old CPU Name would be
enough
? (Damn it - hope you understand my Denglish)
Can the CPUs be distinguished in some deterministic way? If so, rewrite it, no problem.
Both CPU types have the same basic CPU ID, only the 4 stepping bits (the 4 LSBs of the CPU ID) are different. So basically the existing functions could be extended just to handle the new stepping code.
However, the naming scheme of the new CPU type according to the data sheet is quite different than the older steppings.
Older PXA270 versions have the following CPU ID, wher the last hex digit (the 4 LSBs) is the stepping code, e.g.:
CPU ID: 0x69054111, stepping code 1 --> PXA270 -- A1
The Marvell Spec Update Manual shows the new Stepping and CPU ID as follows:
CPU ID: 0x69054118, stepping code 8 --> PXA270M -- A1
So for stepping code 8 the revision name A1 is the same as for stepping code 1, but the CPU base name has changed from PXA270 to PXA270M for the new type.
So just extending the existing stepping decoding function would lead to confusion since the existing code would print
PXA270 rev. A1
for bothe the oldest and the newest CPU type, where something like
PXA270M rev. A1
would be correct for stepping code 8. I'm not sure which would be the best way to handle this situation and change the code accordingly.
Best regards, Marek Vasut
Kind regards Andreas
Dear Andreas Puls,
Dear Marek Vasut,
Dear Andreas Puls,
Dear Marek Vasut,
Dear Andreas Puls,
Hi together,
i've got another problem with latest stable U-Boot-2012.10 and a Toradex Colibri PXA270 V2.4
Uboot dosen't regonized the CPU Revision u-boot summary screen:
U-Boot 2012.10 (Nov 12 2012 - 14:22:12) CPU: Marvell PXA27x rev. Unknown
See arch/arm/cpu/pxa/cpuinfo.c , patch is welcome ... they probably rolled out some new CPU version.
Yes, its a PXA270 M. There is a spec. update pdf from Marvel.
http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_s pe
c_update.pdf - Table 2-3.
They changed the Stepping from A0...C5 to "PXA270M -- A1" A colleague would support me to change this becouse i have no cloue
about
writing C Files. So we would like ask you first if the right CPU Name should be shown in the summary screen which would be a rewrite of your function or only the right stepping with the old CPU Name would be
enough
? (Damn it - hope you understand my Denglish)
Can the CPUs be distinguished in some deterministic way? If so, rewrite it, no problem.
Both CPU types have the same basic CPU ID, only the 4 stepping bits (the 4 LSBs of the CPU ID) are different. So basically the existing functions could be extended just to handle the new stepping code.
However, the naming scheme of the new CPU type according to the data sheet is quite different than the older steppings.
Older PXA270 versions have the following CPU ID, wher the last hex digit (the 4 LSBs) is the stepping code, e.g.:
CPU ID: 0x69054111, stepping code 1 --> PXA270 -- A1
The Marvell Spec Update Manual shows the new Stepping and CPU ID as follows:
CPU ID: 0x69054118, stepping code 8 --> PXA270M -- A1
So for stepping code 8 the revision name A1 is the same as for stepping code 1, but the CPU base name has changed from PXA270 to PXA270M for the new type.
So just extending the existing stepping decoding function would lead to confusion since the existing code would print
PXA270 rev. A1
for bothe the oldest and the newest CPU type, where something like
PXA270M rev. A1
would be correct for stepping code 8. I'm not sure which would be the best way to handle this situation and change the code accordingly.
Try something, submit a patch, then we'll discuss it further above some code. Let's stop theoreticizing now.
Best regards, Marek Vasut
participants (2)
-
Andreas Puls -
Marek Vasut