[U-Boot] [PATCH V8 0/9] EXYNOS5: Enable DWMMC, add FDT support for DWMMC and
This patch set enables and initialises DWMMC for Exynos5250 on SMDK5250. Adds driver changes required for DWMMC. Adds FDT support for DWMMC. Adds EMMC boot support for SMDK5250.
This patch set is based on: "EXYNOS: mmc: support DesignWare Controller for Samsung-SoC", which is merged in u-boot-mmc. "Exynos: clock: support get_mmc_clk for exynos". "Add DT based ethernet driver for SMDK5250". "SMDK5250: Add FDT support" present at the following link http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/149991
Changes since V1: 1)Corrected in response to review comments. 2)Created separate board files for FDT and non-FDT versions. 3)Added binding file for DWMMC device node. 4)Removed the propname 'index' from device node. 5)Prefixed the vendor name 'samsung' before propname in device node. 6)Ensured to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 7)EMMC clock setting has been moved from spl_boot.c to clock_init.c.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10). 2)In the file exynos_dw_mmc.c, replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 3)In the file exynos_dw_mmc.c, computation of FSYS block clock divisor (pre-ratio) value is added. 4)Removed the new function exynos5_mmc_set_clk_div() from clock.c.
Changes since V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1). 2)Replaced the function call 'exynos_dwmmc_init(0, 8);' with the function exynos_dwmmc_add_port() in smdk5250.c. 3)The function get_irom_func(int index) has been added to avoid type casting at many places. 4)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed).
Changes since V5: 1)Added the 'removable' flag to mmc device node. 2)Changed the mmc clock value from 50MHz to 52MHz in the function exynos_dwmci_add_port() present in file drivers/mmc/exynos_dw_mmc.c. 3)Enabled CONFIG_LCD only for non-FDT operation. 4)Removed the function call i2c_init() present inside the function board_i2c_init().
Changes since V6: 1)Re-based to the patch "SMDK5250: Add PMIC voltage settings".
Changes since V7: 1)Re-based to the patch "Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk". 2)In file dw_mmc.c, updated the function dwmci_setup_bus() to return 0 if (freq == 0).This is to avoid the run time exception "raise:Signal # 8 caught". 3)In the files drivers/mmc/mmc.c and common/cmd_mmc.c, the piece of code involved in EMMC open/close and resize of EMMC boot partition has been made conditional and is enabled only if the macro CONFIG_SUPPORT_EMMC_BOOT is defined. 4)The macros FSYS1_MMC0_DIV_MASK and FSYS1_MMC0_DIV_VAL are made local to file clock_init.c.
Amar (9): FDT: Add compatible string for DWMMC EXYNOS5: FDT: Add DWMMC device node data DWMMC: Initialise dwmci and resolve EMMC read write issues EXYNOS5: DWMMC: Added FDT support for DWMMC EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results. SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT MMC: APIs to support resize of EMMC boot partition SMDK5250: Enable EMMC booting COMMON: MMC: Command to support EMMC booting and to resize EMMC boot partition
arch/arm/cpu/armv7/exynos/clock.c | 4 +- arch/arm/dts/exynos5250.dtsi | 33 +++ arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +- board/samsung/dts/exynos5250-smdk5250.dts | 24 ++ board/samsung/smdk5250/Makefile | 4 + board/samsung/smdk5250/clock_init.c | 18 ++ board/samsung/smdk5250/clock_init.h | 5 + board/samsung/smdk5250/exynos5-dt.c | 423 ++++++++++++++++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 223 ++++------------ board/samsung/smdk5250/spl_boot.c | 52 +++- common/cmd_mmc.c | 110 +++++++- doc/device-tree-bindings/exynos/dwmmc.txt | 54 ++++ drivers/mmc/dw_mmc.c | 28 +- drivers/mmc/exynos_dw_mmc.c | 127 ++++++++- drivers/mmc/mmc.c | 134 ++++++++++ drivers/video/exynos_fb.c | 4 +- include/configs/exynos5250-dt.h | 8 + include/dwmmc.h | 3 + include/fdtdec.h | 1 + include/mmc.h | 26 ++ lib/fdtdec.c | 1 + 21 files changed, 1087 insertions(+), 206 deletions(-) create mode 100644 board/samsung/smdk5250/exynos5-dt.c create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt
Add required compatible information for DWMMC driver.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Jaehoon Chung jh80.chung@samsung.com --- Changes since V1: No change.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: No change.
Changes since V5: No change.
Changes since V6: No change.
Changes since V7: No change.
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index a83b160..5ab3d59 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -89,6 +89,7 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ + COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0f34bdc..c187133 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -64,6 +64,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), + COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Jaehoon Chung jh80.chung@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since V1: 1)Added binding file for DWMMC device node at the location "doc/device-tree-bindings/exynos/dwmmc.txt". 2)Removed the propname 'index' from device node. 3)Prefixed the vendor name 'samsung' before propname in device node.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Updated the doc/device-tree-bindings/exynos/dwmmc.txt with more information regarding the property 'samsung,timing'. 2)Replaced the name 'dwmmc' with 'mmc'.
Changes since V5: 1)Added the 'removable' flag to mmc device node.
Changes since V6: No change.
Changes since V7: No change.
arch/arm/dts/exynos5250.dtsi | 33 +++++++++++++++++++ board/samsung/dts/exynos5250-smdk5250.dts | 24 ++++++++++++++ doc/device-tree-bindings/exynos/dwmmc.txt | 54 +++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index df4b231..cee4fe8 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -169,4 +169,37 @@ #address-cells = <1>; #size-cells = <1>; }; + + mmc@12200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + }; + + mmc@12210000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + }; + + mmc@12220000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + }; + + mmc@12230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + }; + }; diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index 8da973b..93375a6 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -30,6 +30,10 @@ spi2 = "/spi@12d40000"; spi3 = "/spi@131a0000"; spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + mmc3 = "/mmc@12230000"; };
sromc@12250000 { @@ -119,4 +123,24 @@ samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; }; diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt new file mode 100644 index 0000000..566da3b --- /dev/null +++ b/doc/device-tree-bindings/exynos/dwmmc.txt @@ -0,0 +1,54 @@ +* Exynos 5250 DWC_mobile_storage + +The Exynos 5250 provides DWC_mobile_storage interface which supports +. Embedded Multimedia Cards (EMMC-version 4.5) +. Secure Digital memory (SD mem-version 2.0) +. Secure Digital I/O (SDIO-version 3.0) +. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1) + +The Exynos 5250 DWC_mobile_storage provides four channels. +SOC specific and Board specific properties are channel specific. + +Required SoC Specific Properties: + +- compatible: should be + - samsung,exynos5250-dwmmc: for exynos5250 platforms + +- reg: physical base address of the controller and length of memory mapped + region. + +- interrupts: The interrupt number to the cpu. + +Required Board Specific Properties: + +- #address-cells: should be 1. +- #size-cells: should be 0. +- samsung,bus-width: The width of the bus used to interface the devices + supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO). + . Typically the bus width is 4 or 8. +- samsung,timing: The timing values to be written into the + Drv/sample clock selection register of corresponding channel. + . It is comprised of 3 values corresponding to the 3 fileds + 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register. + . SelClk_sample: Select sample clock among 8 shifted clocks. + . SelClk_drv: Select drv clock among 8 shifted clocks. + . DIVRATIO: Clock Divide ratio select. + . The above 3 values are used by the clock phase shifter. + +Example: + +mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <1>; +} +In the above example, + . The bus width is 8 + . Timing is comprised of 3 values as explained below + 1 - SelClk_sample + 3 - SelClk_drv + 3 - DIVRATIO + . The 'removable' flag indicates whether the the particilar device + cannot be removed (always present) or it is a removable device. + 1 - Indicates that the device is removable. + 0 - Indicates that the device cannot be removed.
This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues.
Signed-off-by: Amar amarendra.xt@samsung.com --- Changes since V1: 1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).
Changes since V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).
Changes since V5: 1)Updated in response to review comments.
Changes since V6: No change.
Changes since V7: 1)Updated the function dwmci_setup_bus() to return 0 if (freq == 0). This is to avoid the run time exception "raise:Signal # 8 caught".
drivers/mmc/dw_mmc.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4070d4e..963a515 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int timeout = 100000; u32 retry = 10000; u32 mask, ctrl; + ulong start = get_timer(0);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { - if (timeout == 0) { + if (get_timer(start) > timeout) { printf("Timeout on data busy\n"); return TIMEOUT; } - timeout--; }
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); @@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) dwmci_prepare_data(host, data);
- dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
if (data) @@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) int timeout = 10000; unsigned long sclk;
- if (freq == host->clock) + if ((freq == host->clock) || (freq == 0)) return 0; - /* * If host->mmc_clk didn't define, * then assume that host->bus_hz is source clock value. @@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc) static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv; - u32 fifo_size, fifoth_val; + u32 fifo_size, fifoth_val, ier;
dwmci_writel(host, DWMCI_PWREN, 1);
@@ -323,6 +321,14 @@ static int dwmci_init(struct mmc *mmc) return -1; }
+ /* Enumerate at 400KHz */ + dwmci_setup_bus(host, mmc->f_min); + + /* Set auto stop command */ + ier = dwmci_readl(host, DWMCI_CTRL); + ier |= DWMCI_CTRL_SEND_AS_CCSD; + dwmci_writel(host, DWMCI_CTRL, ier); + dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0);
@@ -332,11 +338,13 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_BMOD, 1);
fifo_size = dwmci_readl(host, DWMCI_FIFOTH); - if (host->fifoth_val) + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + if (host->fifoth_val) { fifoth_val = host->fifoth_val; - else - fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | - TX_WMARK(fifo_size/2); + } else { + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); + } dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
dwmci_writel(host, DWMCI_CLKENA, 0);
Hi Amar,
I'm not sure that need to enable the auto-stop command feature. why do you enable this feature? Is there any benefit? Is it related with read/write issue?
Best Regards, Jaehoon Chung
On 04/03/2013 11:08 PM, Amar wrote:
This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).
Changes since V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).
Changes since V5: 1)Updated in response to review comments.
Changes since V6: No change.
Changes since V7: 1)Updated the function dwmci_setup_bus() to return 0 if (freq == 0). This is to avoid the run time exception "raise:Signal # 8 caught".
drivers/mmc/dw_mmc.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4070d4e..963a515 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int timeout = 100000; u32 retry = 10000; u32 mask, ctrl;
ulong start = get_timer(0);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (timeout == 0) {
if (get_timer(start) > timeout) { printf("Timeout on data busy\n"); return TIMEOUT;
timeout--;}
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) dwmci_prepare_data(host, data);
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
if (data)
@@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) int timeout = 10000; unsigned long sclk;
- if (freq == host->clock)
- if ((freq == host->clock) || (freq == 0)) return 0;
- /*
- If host->mmc_clk didn't define,
- then assume that host->bus_hz is source clock value.
@@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc) static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
- u32 fifo_size, fifoth_val;
u32 fifo_size, fifoth_val, ier;
dwmci_writel(host, DWMCI_PWREN, 1);
@@ -323,6 +321,14 @@ static int dwmci_init(struct mmc *mmc) return -1; }
- /* Enumerate at 400KHz */
- dwmci_setup_bus(host, mmc->f_min);
- /* Set auto stop command */
- ier = dwmci_readl(host, DWMCI_CTRL);
- ier |= DWMCI_CTRL_SEND_AS_CCSD;
- dwmci_writel(host, DWMCI_CTRL, ier);
- dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0);
@@ -332,11 +338,13 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_BMOD, 1);
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
- if (host->fifoth_val)
- fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
- if (host->fifoth_val) { fifoth_val = host->fifoth_val;
- else
fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |TX_WMARK(fifo_size/2);
} else {
fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |TX_WMARK(fifo_size / 2);} dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
dwmci_writel(host, DWMCI_CLKENA, 0);
Hi Jaehoon,
Auto-stop command is not related to read/write issue. Today, I commented the 'auto-stop command' enable code and tested, SD/EMMC read write and EMMC boot work fine. Hence enabling Auto-stop command is not required. I shall update the same in next patchset.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:19, Jaehoon Chung jh80.chung@samsung.com wrote:
Hi Amar,
I'm not sure that need to enable the auto-stop command feature. why do you enable this feature? Is there any benefit? Is it related with read/write issue?
Best Regards, Jaehoon Chung
On 04/03/2013 11:08 PM, Amar wrote:
This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header
file.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10).
Changes since V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1).
Changes since V5: 1)Updated in response to review comments.
Changes since V6: No change.
Changes since V7: 1)Updated the function dwmci_setup_bus() to return 0 if (freq ==
0).
This is to avoid the run time exception "raise:Signal # 8 caught".drivers/mmc/dw_mmc.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4070d4e..963a515 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct
mmc_cmd *cmd,
unsigned int timeout = 100000; u32 retry = 10000; u32 mask, ctrl;
ulong start = get_timer(0); while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (timeout == 0) {
if (get_timer(start) > timeout) { printf("Timeout on data busy\n"); return TIMEOUT; }
timeout--; } dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct
mmc_cmd *cmd,
if (data) dwmci_prepare_data(host, data);
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); if (data)@@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host,
u32 freq)
int timeout = 10000; unsigned long sclk;
if (freq == host->clock)
if ((freq == host->clock) || (freq == 0)) return 0;
/* * If host->mmc_clk didn't define, * then assume that host->bus_hz is source clock value.@@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc) static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 fifo_size, fifoth_val;
u32 fifo_size, fifoth_val, ier; dwmci_writel(host, DWMCI_PWREN, 1);@@ -323,6 +321,14 @@ static int dwmci_init(struct mmc *mmc) return -1; }
/* Enumerate at 400KHz */dwmci_setup_bus(host, mmc->f_min);/* Set auto stop command */ier = dwmci_readl(host, DWMCI_CTRL);ier |= DWMCI_CTRL_SEND_AS_CCSD;dwmci_writel(host, DWMCI_CTRL, ier);dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0);@@ -332,11 +338,13 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_BMOD, 1);
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
if (host->fifoth_val)
fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;if (host->fifoth_val) { fifoth_val = host->fifoth_val;
elsefifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |TX_WMARK(fifo_size/2);
} else {fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |TX_WMARK(fifo_size / 2);} dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); dwmci_writel(host, DWMCI_CLKENA, 0);
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This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.
Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int bus_width)" with int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will use exynos_dwmmc_add_port() for every channel enabled in device node. 2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within the function.
Changes since V5: 1)Updated in response to review comments and changed the mmc clock value from 50MHz to 52MHz.
Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127 ++++++++++++++++++++++++++++--- include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index); - -static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return exynos_dwmci_init(base, bus_width, index); -} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
+/* + * Function used as callback function to initialise the + * CLKSEL register for every mmc channel. + */ static void exynos_dwmci_clksel(struct dwmci_host *host) { - u32 val; - val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | - DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); +}
- dwmci_writel(host, DWMCI_CLKSEL, val); +unsigned int exynos_dwmci_get_clk(int dev_index) +{ + return get_mmc_clk(dev_index); }
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { struct dwmci_host *host = NULL; + unsigned int div; + unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; } + /* request mmc clock vlaue of 52MHz. */ + freq = 52000000; + sclk = get_mmc_clk(index); + div = DIV_ROUND_UP(sclk, freq); + /* set the clock divisor for mmc */ + set_mmc_clk(index, div);
- host->name = EXYNOS_NAME; + host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width; + + if (clksel) { + host->clksel_val = clksel; + } else { + if (0 == index) + host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; + if (2 == index) + host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; + } + host->clksel = exynos_dwmci_clksel; host->dev_index = index; + host->mmc_clk = exynos_dwmci_get_clk; + /* Add the mmc channel to be registered with mmc core */ + if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { + debug("dwmmc%d registration failed\n", index); + return -1; + } + return 0; +} + +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{ + int index, bus_width; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, dev_id, flag, count, i; + u32 clksel_val, base, timing[3]; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, + DWMMC_MAX_CH_NUM); + + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue;
- add_dwmci(host, 52000000, 400000); + /* Extract device id for each mmc channel */ + dev_id = pinmux_decode_periph_id(blob, node);
+ /* Get the bus width from the device node */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width <= 0) { + debug("DWMMC: Can't get bus-width\n"); + return -1; + } + if (8 == bus_width) + flag = PINMUX_FLAG_8BIT_MODE; + else + flag = PINMUX_FLAG_NONE; + + /* config pinmux for each mmc channel */ + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("DWMMC not configured\n"); + return err; + } + + index = dev_id - PERIPH_ID_SDMMC0; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -1; + } + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", + timing, 3); + if (err) { + debug("Can't get sdr-timings for divider\n"); + return -1; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + /* Initialise each mmc channel */ + err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); + if (err) + debug("dwmmc Channel-%d init failed\n", index); + } return 0; } - +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth; + u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.
Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int bus_width)" with int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will use exynos_dwmmc_add_port() for every channel enabled in device node. 2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within the function.
Changes since V5: 1)Updated in response to review comments and changed the mmc clock value from 50MHz to 52MHz.
Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127 ++++++++++++++++++++++++++++--- include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{
- unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return exynos_dwmci_init(base, bus_width, index);
-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
- u32 val;
- val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
- dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
- dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index) +{
- return get_mmc_clk(dev_index);
}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in 'index'.
- bus_width - operating bus width of mmc channel specified in 'index'.
- clksel - value to be written into CLKSEL register in case of FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { struct dwmci_host *host = NULL;
- unsigned int div;
- unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }
- /* request mmc clock vlaue of 52MHz. */
- freq = 52000000;
- sclk = get_mmc_clk(index);
- div = DIV_ROUND_UP(sclk, freq);
- /* set the clock divisor for mmc */
- set_mmc_clk(index, div);
- host->name = EXYNOS_NAME;
- host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;
- if (clksel) {
host->clksel_val = clksel;- } else {
if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;- }
- host->clksel = exynos_dwmci_clksel; host->dev_index = index;
- host->mmc_clk = exynos_dwmci_get_clk;
- /* Add the mmc channel to be registered with mmc core */
- if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
debug("dwmmc%d registration failed\n", index);return -1;- }
- return 0;
+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
- int index, bus_width;
- int node_list[DWMMC_MAX_CH_NUM];
- int err = 0, dev_id, flag, count, i;
- u32 clksel_val, base, timing[3];
- count = fdtdec_find_aliases_for_id(blob, "mmc",
COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,DWMMC_MAX_CH_NUM);- for (i = 0; i < count; i++) {
int node = node_list[i];if (node <= 0)continue;
- add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node, "samsung,timing",timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;
}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
- u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
Hi Jaehoon,
Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:23, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.
Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) willuse
exynos_dwmmc_add_port() for every channel enabled indevice node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' withinthe function.
Changes since V5: 1)Updated in response to review comments and changed the mmc clock
value
from 50MHz to 52MHz.Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127
++++++++++++++++++++++++++++---
include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);return exynos_dwmci_init(base, bus_width, index);-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.
The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port. But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
u32 val;val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);+}
dwmci_writel(host, DWMCI_CLKSEL, val);+unsigned int exynos_dwmci_get_clk(int dev_index) +{
return get_mmc_clk(dev_index);}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in 'index'.
- bus_width - operating bus width of mmc channel specified in
'index'.
- clksel - value to be written into CLKSEL register in case of FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ struct dwmci_host *host = NULL;
unsigned int div;unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }/* request mmc clock vlaue of 52MHz. */freq = 52000000;sclk = get_mmc_clk(index);div = DIV_ROUND_UP(sclk, freq);/* set the clock divisor for mmc */set_mmc_clk(index, div);
host->name = EXYNOS_NAME;
host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;if (clksel) {host->clksel_val = clksel;} else {if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;}host->clksel = exynos_dwmci_clksel; host->dev_index = index;host->mmc_clk = exynos_dwmci_get_clk;/* Add the mmc channel to be registered with mmc core */if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {debug("dwmmc%d registration failed\n", index);return -1;}return 0;+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
int index, bus_width;int node_list[DWMMC_MAX_CH_NUM];int err = 0, dev_id, flag, count, i;u32 clksel_val, base, timing[3];count = fdtdec_find_aliases_for_id(blob, "mmc",COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,DWMMC_MAX_CH_NUM);for (i = 0; i < count; i++) {int node = node_list[i];if (node <= 0)continue;
add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node,"samsung,bus-width", 0);
if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node, "samsung,timing",timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width,clksel_val);
if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
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On 04/10/2013 03:13 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:23, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added.
Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) willuse
exynos_dwmmc_add_port() for every channel enabled indevice node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' withinthe function.
Changes since V5: 1)Updated in response to review comments and changed the mmc clock
value
from 50MHz to 52MHz.Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127
++++++++++++++++++++++++++++---
include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);return exynos_dwmci_init(base, bus_width, index);-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.
The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port. But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.
No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4. Then we need to consider how get the clksel value according to SoC.
Best Regards, Jaehoon Chung
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
u32 val;val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);+}
dwmci_writel(host, DWMCI_CLKSEL, val);+unsigned int exynos_dwmci_get_clk(int dev_index) +{
return get_mmc_clk(dev_index);}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in 'index'.
- bus_width - operating bus width of mmc channel specified in
'index'.
- clksel - value to be written into CLKSEL register in case of FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ struct dwmci_host *host = NULL;
unsigned int div;unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }/* request mmc clock vlaue of 52MHz. */freq = 52000000;sclk = get_mmc_clk(index);div = DIV_ROUND_UP(sclk, freq);/* set the clock divisor for mmc */set_mmc_clk(index, div);
host->name = EXYNOS_NAME;
host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;if (clksel) {host->clksel_val = clksel;} else {if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;}host->clksel = exynos_dwmci_clksel; host->dev_index = index;host->mmc_clk = exynos_dwmci_get_clk;/* Add the mmc channel to be registered with mmc core */if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {debug("dwmmc%d registration failed\n", index);return -1;}return 0;+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
int index, bus_width;int node_list[DWMMC_MAX_CH_NUM];int err = 0, dev_id, flag, count, i;u32 clksel_val, base, timing[3];count = fdtdec_find_aliases_for_id(blob, "mmc",COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,DWMMC_MAX_CH_NUM);for (i = 0; i < count; i++) {int node = node_list[i];if (node <= 0)continue;
add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node,"samsung,bus-width", 0);
if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node, "samsung,timing",timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width,clksel_val);
if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
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Hi Jaehoon,
Please find my response below.
Thanks & Regards Amarendra Reddy
On 12 April 2013 16:50, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/10/2013 03:13 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:23, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the
purpose.
2)Computation of FSYS block clock divisor (pre-ratio) is added.Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) willuse
exynos_dwmmc_add_port() for every channel enabled indevice node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' withinthe function.
Changes since V5: 1)Updated in response to review comments and changed the mmc
clock
value
from 50MHz to 52MHz.Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127
++++++++++++++++++++++++++++---
include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);return exynos_dwmci_init(base, bus_width, index);-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.
The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port. But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.
No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4. Then we need to consider how get the clksel value according to SoC.
Best Regards, Jaehoon Chung
OK. Then I shall add the macro for supporting exynos4 also as shown below #define EXYNOS4_DWMMC_MMC0_CLKSEL_VAL 0x00000000 (reset value) #define EXYNOS5_DWMMC_MMC0_CLKSEL_VAL 0x03030001 #define EXYNOS5_DWMMC_MMC2_CLKSEL_VAL 0x03020001
In Exynos4, Mobile Storage Host has only one channel.
The the below function will be updated as below int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { ...... ......
if (clksel) { host->clksel_val = clksel; } else { if (0 == index) { if(cpu_is_exynos5()) host->clksel_val = EXYNOS5_DWMMC_MMC0_CLKSEL_VAL; else host->clksel_val = EXYNOS4_DWMMC_MMC0_CLKSEL_VAL; /* Exynos4 MSH has only one channel */
}
if (2 == index) host->clksel_val = EXYNOS5_DWMMC_MMC2_CLKSEL_VAL; } ........ ........ }
Is it OK. Please comment on the above.
Thanks & Regards Amarendra Reddy
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
u32 val;val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DIV_RATIO(0);
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);+}
dwmci_writel(host, DWMCI_CLKSEL, val);+unsigned int exynos_dwmci_get_clk(int dev_index) +{
return get_mmc_clk(dev_index);}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in
'index'.
- bus_width - operating bus width of mmc channel specified in
'index'.
- clksel - value to be written into CLKSEL register in case of FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ struct dwmci_host *host = NULL;
unsigned int div;unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }/* request mmc clock vlaue of 52MHz. */freq = 52000000;sclk = get_mmc_clk(index);div = DIV_ROUND_UP(sclk, freq);/* set the clock divisor for mmc */set_mmc_clk(index, div);
host->name = EXYNOS_NAME;
host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;if (clksel) {host->clksel_val = clksel;} else {if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;}host->clksel = exynos_dwmci_clksel; host->dev_index = index;host->mmc_clk = exynos_dwmci_get_clk;/* Add the mmc channel to be registered with mmc core */if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {debug("dwmmc%d registration failed\n", index);return -1;}return 0;+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
int index, bus_width;int node_list[DWMMC_MAX_CH_NUM];int err = 0, dev_id, flag, count, i;u32 clksel_val, base, timing[3];count = fdtdec_find_aliases_for_id(blob, "mmc",COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,DWMMC_MAX_CH_NUM);for (i = 0; i < count; i++) {int node = node_list[i];if (node <= 0)continue;
add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node,"samsung,bus-width", 0);
if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node, "samsung,timing",timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width,clksel_val);
if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
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On 04/16/2013 05:44 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my response below.
Thanks & Regards Amarendra Reddy
On 12 April 2013 16:50, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/10/2013 03:13 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:23, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the
purpose.
2)Computation of FSYS block clock divisor (pre-ratio) is added.Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) willuse
exynos_dwmmc_add_port() for every channel enabled indevice node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' withinthe function.
Changes since V5: 1)Updated in response to review comments and changed the mmc
clock
value
from 50MHz to 52MHz.Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127
++++++++++++++++++++++++++++---
include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);return exynos_dwmci_init(base, bus_width, index);-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.
The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port. But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5 series and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.
No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4. Then we need to consider how get the clksel value according to SoC.
Best Regards, Jaehoon Chung
OK. Then I shall add the macro for supporting exynos4 also as shown below #define EXYNOS4_DWMMC_MMC0_CLKSEL_VAL 0x00000000 (reset value) #define EXYNOS5_DWMMC_MMC0_CLKSEL_VAL 0x03030001 #define EXYNOS5_DWMMC_MMC2_CLKSEL_VAL 0x03020001
In Exynos4, Mobile Storage Host has only one channel.
The the below function will be updated as below int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { ...... ......
if (clksel) { host->clksel_val = clksel; } else { if (0 == index) { if(cpu_is_exynos5()) host->clksel_val =EXYNOS5_DWMMC_MMC0_CLKSEL_VAL; else host->clksel_val = EXYNOS4_DWMMC_MMC0_CLKSEL_VAL; /* Exynos4 MSH has only one channel */
} if (2 == index) host->clksel_val = EXYNOS5_DWMMC_MMC2_CLKSEL_VAL; }........ ........ }
Is it OK. Please comment on the above.
Well...if you want to set the CLKSEL,i will modify for exynos4 in future. How about this? (I think you're only working for the exynos5)
Best Regards, Jaehoon Chung
Thanks & Regards Amarendra Reddy
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
u32 val;val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DIV_RATIO(0);
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);+}
dwmci_writel(host, DWMCI_CLKSEL, val);+unsigned int exynos_dwmci_get_clk(int dev_index) +{
return get_mmc_clk(dev_index);}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in
'index'.
- bus_width - operating bus width of mmc channel specified in
'index'.
- clksel - value to be written into CLKSEL register in case of FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ struct dwmci_host *host = NULL;
unsigned int div;unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }/* request mmc clock vlaue of 52MHz. */freq = 52000000;sclk = get_mmc_clk(index);div = DIV_ROUND_UP(sclk, freq);/* set the clock divisor for mmc */set_mmc_clk(index, div);
host->name = EXYNOS_NAME;
host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;if (clksel) {host->clksel_val = clksel;} else {if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;}host->clksel = exynos_dwmci_clksel; host->dev_index = index;host->mmc_clk = exynos_dwmci_get_clk;/* Add the mmc channel to be registered with mmc core */if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {debug("dwmmc%d registration failed\n", index);return -1;}return 0;+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
int index, bus_width;int node_list[DWMMC_MAX_CH_NUM];int err = 0, dev_id, flag, count, i;u32 clksel_val, base, timing[3];count = fdtdec_find_aliases_for_id(blob, "mmc",COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,DWMMC_MAX_CH_NUM);for (i = 0; i < count; i++) {int node = node_list[i];if (node <= 0)continue;
add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node,"samsung,bus-width", 0);
if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node, "samsung,timing",timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width,clksel_val);
if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
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Hi Jaehoon,
Please find my response below
Thanks & Regards Amarendra
On 23 April 2013 09:27, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/16/2013 05:44 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my response below.
Thanks & Regards Amarendra Reddy
On 12 April 2013 16:50, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/10/2013 03:13 PM, Amarendra Reddy wrote:
Hi Jaehoon,
Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:23, Jaehoon Chung jh80.chung@samsung.com wrote:
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT.
Changes since V2: 1)Updation of commit message and resubmition of proper patch
set.
Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the
purpose.
2)Computation of FSYS block clock divisor (pre-ratio) is added.Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int
bus_width)" with
int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDTboards.
ii)In FDT case, exynos_dwmmc_init(const void *blob)will
use
exynos_dwmmc_add_port() for every channel enabled indevice node.
2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val'within
the function.
Changes since V5: 1)Updated in response to review comments and changed the mmc
clock
value
from 50MHz to 52MHz.Changes since V6: No change.
Changes since V7: No change.
arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127
++++++++++++++++++++++++++++---
include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-static inline unsigned int exynos_dwmmc_init(int index, int
bus_width)
-{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);return exynos_dwmci_init(base, bus_width, index);-} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c
b/drivers/mmc/exynos_dw_mmc.c
index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */
#include <common.h> -#include <malloc.h> #include <dwmmc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> +#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
I known that CLKSEL's value is SoC specific. All exynos series are working fine? I didn't think so.
Best Regards, Jaehoon Chung
The above values of CLKSEL work fine for Exynos5 (5250 & 5410) and is tested.
The above CLKSEL values donot hold good for Exynos4 series. Exynos4 has "Mobile Storage Host" with only one port. But this file 'drivers/mmc/exynos_dw_mmc.c' is specific to Exynos5
series
and gets compiled only when CONFIG_EXYNOS_DWMMC is defined.
No, driver/mmc/exynos_dw_mmc.c isn't specific to Exynos5 series. We can use this controller at the exynos4. Then we need to consider how get the clksel value according to SoC.
Best Regards, Jaehoon Chung
OK. Then I shall add the macro for supporting exynos4 also as shown below #define EXYNOS4_DWMMC_MMC0_CLKSEL_VAL 0x00000000 (reset value) #define EXYNOS5_DWMMC_MMC0_CLKSEL_VAL 0x03030001 #define EXYNOS5_DWMMC_MMC2_CLKSEL_VAL 0x03020001
In Exynos4, Mobile Storage Host has only one channel.
The the below function will be updated as below int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ ...... ......
if (clksel) { host->clksel_val = clksel; } else { if (0 == index) { if(cpu_is_exynos5()) host->clksel_val =EXYNOS5_DWMMC_MMC0_CLKSEL_VAL; else host->clksel_val = EXYNOS4_DWMMC_MMC0_CLKSEL_VAL; /* Exynos4 MSH has only one channel
*/
} if (2 == index) host->clksel_val = EXYNOS5_DWMMC_MMC2_CLKSEL_VAL; }........ ........ }
Is it OK. Please comment on the above.
Well...if you want to set the CLKSEL,i will modify for exynos4 in future. How about this? (I think you're only working for the exynos5)
Ok fine, that will be really good. Hence right now I will not set CLKSEL
for exynos4 in the file 'drivers/mmc/exynos_dw_mmc.c'.
Best Regards,
Jaehoon Chung
Thanks & Regards Amarendra Reddy
+/*
- Function used as callback function to initialise the
- CLKSEL register for every mmc channel.
- */
static void exynos_dwmci_clksel(struct dwmci_host *host) {
u32 val;val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) |DWMCI_SET_DIV_RATIO(0);
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);+}
dwmci_writel(host, DWMCI_CLKSEL, val);+unsigned int exynos_dwmci_get_clk(int dev_index) +{
return get_mmc_clk(dev_index);}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/*
- This function adds the mmc channel to be registered with mmc
core.
- index - mmc channel number.
- regbase - register base address of mmc channel specified in
'index'.
- bus_width - operating bus width of mmc channel specified in
'index'.
- clksel - value to be written into CLKSEL register in case of
FDT.
NULL in case od non-FDT.- */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32
clksel)
{ struct dwmci_host *host = NULL;
unsigned int div;unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; }/* request mmc clock vlaue of 52MHz. */freq = 52000000;sclk = get_mmc_clk(index);div = DIV_ROUND_UP(sclk, freq);/* set the clock divisor for mmc */set_mmc_clk(index, div);
host->name = EXYNOS_NAME;
host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width;if (clksel) {host->clksel_val = clksel;} else {if (0 == index)host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;if (2 == index)host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;}host->clksel = exynos_dwmci_clksel; host->dev_index = index;host->mmc_clk = exynos_dwmci_get_clk;/* Add the mmc channel to be registered with mmc core */if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {debug("dwmmc%d registration failed\n", index);return -1;}return 0;+}
+#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{
int index, bus_width;int node_list[DWMMC_MAX_CH_NUM];int err = 0, dev_id, flag, count, i;u32 clksel_val, base, timing[3];count = fdtdec_find_aliases_for_id(blob, "mmc",COMPAT_SAMSUNG_EXYNOS5_DWMMC,node_list,
DWMMC_MAX_CH_NUM);for (i = 0; i < count; i++) {int node = node_list[i];if (node <= 0)continue;
add_dwmci(host, 52000000, 400000);
/* Extract device id for each mmc channel */dev_id = pinmux_decode_periph_id(blob, node);/* Get the bus width from the device node */bus_width = fdtdec_get_int(blob, node,"samsung,bus-width", 0);
if (bus_width <= 0) {debug("DWMMC: Can't get bus-width\n");return -1;}if (8 == bus_width)flag = PINMUX_FLAG_8BIT_MODE;elseflag = PINMUX_FLAG_NONE;/* config pinmux for each mmc channel */err = exynos_pinmux_config(dev_id, flag);if (err) {debug("DWMMC not configured\n");return err;}index = dev_id - PERIPH_ID_SDMMC0;/* Get the base address from the device node */base = fdtdec_get_addr(blob, node, "reg");if (!base) {debug("DWMMC: Can't get base address\n");return -1;}/* Extract the timing info from the node */err = fdtdec_get_int_array(blob, node,"samsung,timing",
timing, 3);if (err) {debug("Can't get sdr-timings for divider\n");return -1;}clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |DWMCI_SET_DRV_CLK(timing[1]) |DWMCI_SET_DIV_RATIO(timing[2]));/* Initialise each mmc channel */err = exynos_dwmci_add_port(index, base, bus_width,clksel_val);
if (err)debug("dwmmc Channel-%d init failed\n", index);} return 0;}
+#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth;
u32 clksel_val; u32 fifoth_val; struct mmc *mmc;
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This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk().
Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock.
Changes since V4: 1)Updated the subject line to reflect the changes present in this patch. 2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which were present in this patch, have been moved out of this patch.
Changes since V5: No change.
Changes since V6: No change.
Changes since V7: No change.
arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 223660a..cf3247a 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -613,7 +613,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0;
sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -662,7 +662,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0;
sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf;
Acked-by: Jaehoon Chung jh80.chung@samsung.com
On 04/03/2013 11:08 PM, Amar wrote:
This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk().
Signed-off-by: Amar amarendra.xt@samsung.com Acked-by: Simon Glass sjg@chromium.org
Changes since V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: 1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock.
Changes since V4: 1)Updated the subject line to reflect the changes present in this patch. 2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which were present in this patch, have been moved out of this patch.
Changes since V5: No change.
Changes since V6: No change.
Changes since V7: No change.
arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 223660a..cf3247a 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -613,7 +613,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio;
- int shift;
int shift = 0;
sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf;
@@ -662,7 +662,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio;
- int shift;
int shift = 0;
sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf;
This patch enables and initialises DWMMC for SMDK5250. Supports both FDT and non-FDT. This patch creates a new file 'exynos5-dt.c' meant for FDT support. exynos5-dt.c: This file shall contain all code which supports FDT. Any addition of FDT support for any module needs to be added in this file. smdk5250.c: This file shall contain the code which supports non-FDT. version. Any addition of non-FDT support for any module needs to be added in this file. May be, the file smdk5250.c can be removed in near future when non-FDT is not required.
The Makefile is updated to compile only one of the files exynos5-dt.c / smdk5250.c based on FDT configuration.
NOTE: Please note that all additions corresponding to FDT need to be added into the file exynos5-dt.c. At same time if non-FDT support is required then add the corresponding updations into smdk5250.c.
Signed-off-by: Amar amarendra.xt@samsung.com --- Changes since V1: 1)A new file 'exynos5-dt.c' is created meant for FDT support 2)Makefile is updated to compile only one of the files exynos5-dt.c / smdk5250.c based on FDT configuration
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Replaced the function call 'exynos_dwmmc_init(0, 8);' with the function exynos_dwmmc_add_port() in smdk5250.c. 2)dram_init() is updated to use for loop to compute the ram size. 3)dram_init_banksize() is updated to use for loop to initialise the dram bank size. 4)board_uart_init() is updated to use for loop to initialise UARTS. 5)In non-FDT case NULL is passed as parameter to board_i2c_init().
Changes since V5: 1)Enabled CONFIG_LCD only for non-FDT operation.
Changes since V6: 1)Re-based.
Changes since V7: 1)Re-based. 2)Because of creation of new file 'exynos5-dt.c' meant for FDT support, the exynos_fb.c had to be updated to support non-FDT and FDT for LCD. If exynos_fb.c is not updated as per this patch the compilation fails. 3)Added the macro CONFIG_SUPPORT_EMMC_BOOT in exynos5250-dt.h.
board/samsung/smdk5250/Makefile | 4 + board/samsung/smdk5250/exynos5-dt.c | 423 ++++++++++++++++++++++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 223 +++++-------------- drivers/video/exynos_fb.c | 4 +- include/configs/exynos5250-dt.h | 8 + 5 files changed, 493 insertions(+), 169 deletions(-) create mode 100644 board/samsung/smdk5250/exynos5-dt.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 47c6a5a..ecca9f3 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -32,8 +32,12 @@ COBJS += tzpc_init.o COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD +ifdef CONFIG_OF_CONTROL +COBJS += exynos5-dt.o +else COBJS += smdk5250.o endif +endif
ifdef CONFIG_SPL_BUILD COBJS += spl_boot.o diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c new file mode 100644 index 0000000..78ef424 --- /dev/null +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <errno.h> +#include <i2c.h> +#include <netdev.h> +#include <spi.h> +#include <asm/arch/cpu.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/sromc.h> +#include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <tmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined CONFIG_EXYNOS_TMU +/* + * Boot Time Thermal Analysis for SoC temperature threshold breach + */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + /* Status TRIPPED ans WARNING means corresponding threshold breach */ + case TMU_STATUS_TRIPPED: + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + /* + * TMU_STATUS_INIT means something is wrong with temperature sensing + * and TMU status was changed back from NORMAL to INIT. + */ + case TMU_STATUS_INIT: + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + +#ifdef CONFIG_USB_EHCI_EXYNOS +int board_usb_vbus_init(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable VBUS power switch */ + s5p_gpio_direction_output(&gpio1->x2, 6, 1); + + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} +#endif + +#ifdef CONFIG_SOUND_MAX98095 +static void board_enable_audio_codec(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable MAX98095 Codec */ + s5p_gpio_direction_output(&gpio1->x1, 7, 1); + s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + +#ifdef CONFIG_EXYNOS_SPI + spi_init(); +#endif +#ifdef CONFIG_USB_EHCI_EXYNOS + board_usb_vbus_init(); +#endif +#ifdef CONFIG_SOUND_MAX98095 + board_enable_audio_codec(); +#endif + return 0; +} + +int dram_init(void) +{ + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } + return 0; +} + +#if defined(CONFIG_POWER) +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +int power_init_board(void) +{ + struct pmic *p; + + set_ps_hold_ctrl(); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif + +void dram_init_banksize(void) +{ + int i; + u32 addr, size; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; + } +} + +static int decode_sromc(const void *blob, struct fdt_sromc *config) +{ + int err; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); + if (node < 0) { + debug("Could not find SROMC node\n"); + return node; + } + + config->bank = fdtdec_get_int(blob, node, "bank", 0); + config->width = fdtdec_get_int(blob, node, "width", 2); + + err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, + FDT_SROM_TIMING_COUNT); + if (err < 0) { + debug("Could not decode SROMC configuration Error: %s\n", + fdt_strerror(err)); + return -FDT_ERR_NOTFOUND; + } + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + u32 smc_bw_conf, smc_bc_conf; + struct fdt_sromc config; + fdt_addr_t base_addr; + int node; + + node = decode_sromc(gd->fdt_blob, &config); + if (node < 0) { + debug("%s: Could not find sromc configuration\n", __func__); + return 0; + } + node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); + if (node < 0) { + debug("%s: Could not find lan9215 configuration\n", __func__); + return 0; + } + + /* We now have a node, so any problems from now on are errors */ + base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) { + debug("%s: Could not find lan9215 address\n", __func__); + return -1; + } + + /* Ethernet needs data bus width of 16 bits */ + if (config.width != 2) { + debug("%s: Unsupported bus width %d\n", __func__, + config.width); + return -1; + } + smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) + | SROMC_BYTE_ENABLE(config.bank); + + smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | + SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | + SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | + SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | + SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | + SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | + SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); + + /* Select and configure the SROMC bank */ + exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); + s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); + return smc911x_initialize(0, base_addr); +#endif + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (board_name == NULL) + printf("\nUnknown Board\n"); + else + printf("\nBoard: %s\n", board_name); + + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int ret; + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); + if (ret) + debug("dwmmc init failed\n"); + + return ret; +} +#endif + +static int board_uart_init(void) +{ + int err, uart_id, ret = 0; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + ret |= err; + } + } + return ret; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + err = board_uart_init(); + if (err) { + debug("UART init failed\n"); + return err; + } +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_i2c_init(gd->fdt_blob); +#endif + return err; +} +#endif + +#ifdef CONFIG_LCD +void exynos_cfg_lcd_gpio(void) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); + + /* For Backlight */ + s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->b2, 0, 1); + + /* LCD power on */ + s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->x1, 5, 1); + + /* Set Hotplug detect for DP */ + s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); +} + +void exynos_set_dp_phy(unsigned int onoff) +{ + set_dp_phy_ctrl(onoff); +} +#endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 8b09e1d..276fd41 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -29,6 +29,7 @@ #include <netdev.h> #include <spi.h> #include <asm/arch/cpu.h> +#include <asm/arch/dwmmc.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> @@ -37,39 +38,9 @@ #include <asm/arch/dp_info.h> #include <power/pmic.h> #include <power/max77686_pmic.h> -#include <tmu.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined CONFIG_EXYNOS_TMU -/* - * Boot Time Thermal Analysis for SoC temperature threshold breach - */ -static void boot_temp_check(void) -{ - int temp; - - switch (tmu_monitor(&temp)) { - /* Status TRIPPED ans WARNING means corresponding threshold breach */ - case TMU_STATUS_TRIPPED: - puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); - set_ps_hold_ctrl(); - hang(); - break; - case TMU_STATUS_WARNING: - puts("EXYNOS_TMU: WARNING! Temperature very high\n"); - break; - /* - * TMU_STATUS_INIT means something is wrong with temperature sensing - * and TMU status was changed back from NORMAL to INIT. - */ - case TMU_STATUS_INIT: - default: - debug("EXYNOS_TMU: Unknown TMU state\n"); - } -} -#endif - #ifdef CONFIG_USB_EHCI_EXYNOS int board_usb_vbus_init(void) { @@ -102,14 +73,6 @@ int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-#if defined CONFIG_EXYNOS_TMU - if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { - debug("%s: Failed to init TMU\n", __func__); - return -1; - } - boot_temp_check(); -#endif - #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif @@ -124,14 +87,13 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE) - + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE) - + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE) - + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE) - + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE); + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } return 0; }
@@ -254,57 +216,15 @@ int power_init_board(void)
void dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, - PHYS_SDRAM_4_SIZE); - gd->bd->bi_dram[4].start = PHYS_SDRAM_5; - gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5, - PHYS_SDRAM_5_SIZE); - gd->bd->bi_dram[5].start = PHYS_SDRAM_6; - gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6, - PHYS_SDRAM_6_SIZE); - gd->bd->bi_dram[6].start = PHYS_SDRAM_7; - gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7, - PHYS_SDRAM_7_SIZE); - gd->bd->bi_dram[7].start = PHYS_SDRAM_8; - gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8, - PHYS_SDRAM_8_SIZE); -} - -#ifdef CONFIG_OF_CONTROL -static int decode_sromc(const void *blob, struct fdt_sromc *config) -{ - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } - - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); - - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration\n"); - return -FDT_ERR_NOTFOUND; + int i; + u32 addr, size; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; } - - return 0; } -#endif
int board_eth_init(bd_t *bis) { @@ -313,27 +233,6 @@ int board_eth_init(bd_t *bis) struct fdt_sromc config; fdt_addr_t base_addr;
-#ifdef CONFIG_OF_CONTROL - int node; - - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); - if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; - } - - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } -#else /* Non-FDT configuration - bank number and timing parameters*/ config.bank = CONFIG_ENV_SROM_BANK; config.width = 2; @@ -346,7 +245,6 @@ int board_eth_init(bd_t *bis) config.timing[FDT_SROM_TACP] = 0x09; config.timing[FDT_SROM_PMC] = 0x01; base_addr = CONFIG_SMC911X_BASE; -#endif
/* Ethernet needs data bus width of 16 bits */ if (config.width != 2) { @@ -376,17 +274,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { -#ifdef CONFIG_OF_CONTROL - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); -#else printf("\nBoard: SMDK5250\n"); -#endif return 0; } #endif @@ -394,48 +282,54 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int err; + int err, ret = 0, index, bus_width; + u32 base;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) { + if (err) debug("SDMMC0 not configured\n"); - return err; - } - - err = s5p_mmc_init(0, 8); - return err; + ret |= err; + + /*EMMC: dwmmc Channel-0 with 8 bit bus width */ + index = 0; + base = samsung_get_base_mmc() + (0x10000 * index); + bus_width = 8; + err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); + if (err) + debug("dwmmc Channel-0 init failed\n"); + ret |= err; + + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) + debug("SDMMC2 not configured\n"); + ret |= err; + + /*SD: dwmmc Channel-2 with 4 bit bus width */ + index = 2; + base = samsung_get_base_mmc() + (0x10000 * index); + bus_width = 4; + err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); + if (err) + debug("dwmmc Channel-2 init failed\n"); + ret |= err; + + return ret; } #endif
static int board_uart_init(void) { - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; + int err, uart_id, ret = 0; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + ret |= err; + } } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - - return 0; + return ret; }
#ifdef CONFIG_BOARD_EARLY_INIT_F @@ -448,7 +342,7 @@ int board_early_init_f(void) return err; } #ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); + board_i2c_init(NULL); #endif return err; } @@ -477,7 +371,6 @@ void exynos_set_dp_phy(unsigned int onoff) set_dp_phy_ctrl(onoff); }
-#ifndef CONFIG_OF_CONTROL vidinfo_t panel_info = { .vl_freq = 60, .vl_col = 2560, @@ -543,13 +436,9 @@ static struct exynos_dp_platform_data dp_platform_data = { .edp_dev_info = &edp_info, };
-#endif void init_panel_info(vidinfo_t *vid) { -#ifndef CONFIG_OF_CONTROL - vid->rgb_mode = MODE_RGB_P, - + vid->rgb_mode = MODE_RGB_P; exynos_set_dp_platform_data(&dp_platform_data); -#endif } #endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index dfe329f..d3bb7f4 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -331,10 +331,10 @@ void lcd_ctrl_init(void *lcdbase) #ifdef CONFIG_OF_CONTROL if (exynos_fimd_parse_dt(gd->fdt_blob)) debug("Can't get proper panel info\n"); -#endif +#else /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); - +#endif panel_width = panel_info.vl_width; panel_height = panel_info.vl_height;
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 496a194..e026362 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -100,6 +100,10 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_SUPPORT_EMMC_BOOT +
#define CONFIG_BOARD_EARLY_INIT_F
@@ -220,6 +224,10 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS +
#define CONFIG_IRAM_STACK 0x02050000
This patch adds APIs to access(open / close) and to resize boot partiton of EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com --- Changes since V1: New patch.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Replaced the functions mmc_boot_open() & mmc_boot_close() with a single function mmc_boot_part_access().
Changes since V5: 1)Updated in response to review comments.
Changes since V6: 1)Added spaces around << operator, in response to review comments.
Changes since V7: 1)In the file drivers/mmc/mmc.c, the piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the macro CONFIG_SUPPORT_EMMC_BOOT is defined.
drivers/mmc/mmc.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/mmc.h | 26 +++++++++++ 2 files changed, 160 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d732581..a6a04e6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1352,3 +1352,137 @@ int mmc_initialize(bd_t *bis)
return 0; } + +#ifdef CONFIG_SUPPORT_EMMC_BOOT +/* + * This function changes the size of boot partition and the size of rpmb + * partition present on EMMC devices. + * + * Input Parameters: + * struct *mmc: pointer for the mmc device strcuture + * bootsize: size of boot partition + * rpmbsize: size of rpmb partition + * + * Returns 0 on success. + */ + +int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, + unsigned long rpmbsize) +{ + int err; + struct mmc_cmd cmd; + + /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = MMC_CMD62_ARG1; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error1 = %d\n", err); + return err; + } + + /* Boot partition changing mode */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = MMC_CMD62_ARG2; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error2 = %d\n", err); + return err; + } + /* boot partition size is multiple of 128KB */ + bootsize = (bootsize * 1024) / 128; + + /* Arg: boot partition size */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = bootsize; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error3 = %d\n", err); + return err; + } + /* RPMB partition size is multiple of 128KB */ + rpmbsize = (rpmbsize * 1024) / 128; + /* Arg: RPMB partition size */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = rpmbsize; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error4 = %d\n", err); + return err; + } + return 0; +} + +/* + * This function shall form and send the commands to open / close the + * boot partition specified by user. + * + * Input Parameters: + * ack: 0x0 - No boot acknowledge sent (default) + * 0x1 - Boot acknowledge sent during boot operation + * part_num: User selects boot data that will be sent to master + * 0x0 - Device not boot enabled (default) + * 0x1 - Boot partition 1 enabled for boot + * 0x2 - Boot partition 2 enabled for boot + * access: User selects partitions to access + * 0x0 : No access to boot partition (default) + * 0x1 : R/W boot partition 1 + * 0x2 : R/W boot partition 2 + * 0x3 : R/W Replay Protected Memory Block (RPMB) + * + * Returns 0 on success. + */ +int mmc_boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32 access) +{ + int err; + struct mmc_cmd cmd; + + /* Boot ack enable, boot partition enable , boot partition access */ + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + + cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (EXT_CSD_PART_CONF << 16) | + ((EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)) << 8); + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + if (access) { + debug("mmc boot partition#%d open fail:Error1 = %d\n", + part_num, err); + } else { + debug("mmc boot partition#%d close fail:Error = %d\n", + part_num, err); + } + return err; + } + + if (access) { + /* 4bit transfer mode at booting time. */ + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + + cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (EXT_CSD_BOOT_BUS_WIDTH << 16) | + ((1 << 0) << 8); + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc boot partition#%d open fail:Error2 = %d\n", + part_num, err); + return err; + } + } + return 0; +} +#endif diff --git a/include/mmc.h b/include/mmc.h index de6d497..ab93576 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -86,6 +86,11 @@ #define MMC_CMD_APP_CMD 55 #define MMC_CMD_SPI_READ_OCR 58 #define MMC_CMD_SPI_CRC_ON_OFF 59 +#define MMC_CMD_RES_MAN 62 + +#define MMC_CMD62_ARG1 0xefac62ec +#define MMC_CMD62_ARG2 0xcbaea7 +
#define SD_CMD_SEND_RELATIVE_ADDR 3 #define SD_CMD_SWITCH_FUNC 6 @@ -153,6 +158,7 @@ */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_BOOT_BUS_WIDTH 177 #define EXT_CSD_PART_CONF 179 /* R/W */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ @@ -177,6 +183,16 @@ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
+#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) +#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) +#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) +#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) + +#define EXT_CSD_BOOT_ACK(x) (x << 6) +#define EXT_CSD_BOOT_PART_NUM(x) (x << 3) +#define EXT_CSD_PARTITION_ACCESS(x) (x << 0) + + #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5)
@@ -201,6 +217,11 @@ #define PART_ACCESS_MASK (0x7) #define PART_SUPPORT (0x1)
+/* The number of MMC physical partitions. These consist of: + * boot partitions (2), general purpose partitions (4) in MMC v4.4. + */ +#define MMC_NUM_BOOT_PARTITION 2 + struct mmc_cid { unsigned long psn; unsigned short oid; @@ -277,6 +298,11 @@ int mmc_switch_part(int dev_num, unsigned int part_num); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); void spl_mmc_load(void) __noreturn; +/* Function to change the size of boot partition and rpmb partitions */ +int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, + unsigned long rpmbsize); +/* Function to send commands to open/close the specified boot partition */ +int mmc_boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32 access);
#ifdef CONFIG_GENERIC_MMC #define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
This patch adds support for EMMC booting on SMDK5250.
Signed-off-by: Amar amarendra.xt@samsung.com --- Changes since V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)The function get_irom_func(int index) has been added to avoid type casting at many places. 2)The changes to file arch/arm/include/asm/arch-exynos/clk.h are included in this patch file.
Changes since V5: No change.
Changes since V6: No change.
Changes since V7: 1)The macros FSYS1_MMC0_DIV_MASK and FSYS1_MMC0_DIV_VAL are made local to file clock_init.c.
board/samsung/smdk5250/clock_init.c | 18 +++++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index 5b9e82f..b288e66 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,10 +28,14 @@ #include <asm/arch/clk.h> #include <asm/arch/clock.h> #include <asm/arch/spl.h> +#include <asm/arch/dwmmc.h>
#include "clock_init.h" #include "setup.h"
+#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = { @@ -664,3 +668,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..fa2c0b2 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,15 +23,42 @@ #include<common.h> #include<config.h>
+#include <asm/arch-exynos/dmc.h> +#include <asm/arch/clock.h> +#include <asm/arch/clk.h> + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ };
- typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); +void *get_irom_func(int index) +{ + return (void *)*(u32 *)irom_ptr_table[index]; +}
/* * Copy U-boot from mmc to RAM: @@ -40,23 +67,36 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = get_irom_func(SPI_INDEX); spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = get_irom_func(MMC_INDEX); copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX); + end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX); + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + break; + default: break; }
This patch adds commands to access(open/close) and resize boot partitions on EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com --- Changes since V1: 1)Combined the common piece of code between 'open' and 'close' operations.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Added a new funtion boot_part_access() to combine the common parts of 'mmc open' and 'mmc close' functionalities. 2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed).
Changes since V5: 1)Updated minor nits in response to review comments.
Changes since V6: No change.
Changes since V7: 1)The piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the macro CONFIG_SUPPORT_EMMC_BOOT is defined.
common/cmd_mmc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..c5f60a2 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -147,6 +147,36 @@ U_BOOT_CMD( "- display info of the current MMC device" );
+#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32 access) +{ + int err; + err = mmc_boot_part_access(mmc, ack, part_num, access); + + if ((err == 0) && (access != 0)) { + printf("\t\t\t!!!Notice!!!\n"); + + printf("!You must close EMMC boot Partition"); + printf("after all images are written\n"); + + printf("!EMMC boot partition has continuity"); + printf("at image writing time.\n"); + + printf("!So, do not close the boot partition"); + printf("before all images are written.\n"); + return 0; + } else if ((err == 0) && (access == 0)) + return 0; + else if ((err != 0) && (access != 0)) { + printf("EMMC boot partition-%d OPEN Failed.\n", part_num); + return 1; + } else { + printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); + return 1; + } +} +#endif + static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) curr_device, mmc->part_num);
return 0; - } +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if ((strcmp(argv[1], "open") == 0) || + (strcmp(argv[1], "close") == 0)) { + int dev; + struct mmc *mmc; + u32 ack, part_num, access = 0; + + if (argc == 4) { + dev = simple_strtoul(argv[2], NULL, 10); + part_num = simple_strtoul(argv[3], NULL, 10); + } else { + return CMD_RET_USAGE; + }
+ mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + printf("SD device cannot be opened/closed\n"); + return 1; + } + + if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { + printf("Invalid boot partition number:\n"); + printf("Boot partition number cannot be <= 0\n"); + printf("EMMC44 supports only 2 boot partitions\n"); + return 1; + } + + if (strcmp(argv[1], "open") == 0) + access = part_num; /* enable R/W access to boot part*/ + if (strcmp(argv[1], "close") == 0) + access = 0; /* No access to boot partition */ + + /* acknowledge to be sent during boot operation */ + ack = 1; + return boot_part_access(mmc, ack, part_num, access); + + } else if (strcmp(argv[1], "bootpart") == 0) { + int dev; + dev = simple_strtoul(argv[2], NULL, 10); + + u32 bootsize = simple_strtoul(argv[3], NULL, 10); + u32 rpmbsize = simple_strtoul(argv[4], NULL, 10); + struct mmc *mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + printf("It is not a EMMC device\n"); + return 1; + } + + if (0 == mmc_boot_partition_size_change(mmc, + bootsize, rpmbsize)) { + printf("EMMC boot partition Size %d MB\n", bootsize); + printf("EMMC RPMB partition Size %d MB\n", rpmbsize); + return 0; + } else { + printf("EMMC boot partition Size change Failed.\n"); + return 1; + } +#endif /* CONFIG_SUPPORT_EMMC_BOOT */ + } state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ; @@ -324,5 +421,14 @@ U_BOOT_CMD( "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n" - "mmc list - lists available devices"); + "mmc list - lists available devices\n" +#ifdef CONFIG_SUPPORT_EMMC_BOOT + "mmc open <dev> <boot_partition>\n" + " - Enable boot_part for booting and enable R/W access of boot_part\n" + "mmc close <dev> <boot_partition>\n" + " - Enable boot_part for booting and disable access to boot_part\n" + "mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n" + " - change sizes of boot and RPMB partions of specified device\n" #endif + ); +#endif /* !CONFIG_GENERIC_MMC */
Hi Amar,
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds commands to access(open/close) and resize boot partitions on EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Combined the common piece of code between 'open' and 'close' operations.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Added a new funtion boot_part_access() to combine the common parts of 'mmc open' and 'mmc close' functionalities. 2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed).
Changes since V5: 1)Updated minor nits in response to review comments.
Changes since V6: No change.
Changes since V7: 1)The piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the macro CONFIG_SUPPORT_EMMC_BOOT is defined.
common/cmd_mmc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..c5f60a2 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -147,6 +147,36 @@ U_BOOT_CMD( "- display info of the current MMC device" );
+#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32 access)
Why do you use u32? I know that just used 8bit.
+{
- int err;
- err = mmc_boot_part_access(mmc, ack, part_num, access);
- if ((err == 0) && (access != 0)) {
printf("\t\t\t!!!Notice!!!\n");printf("!You must close EMMC boot Partition");printf("after all images are written\n");printf("!EMMC boot partition has continuity");printf("at image writing time.\n");printf("!So, do not close the boot partition");printf("before all images are written.\n");return 0;- } else if ((err == 0) && (access == 0))
return 0;- else if ((err != 0) && (access != 0)) {
printf("EMMC boot partition-%d OPEN Failed.\n", part_num);return 1;- } else {
printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);return 1;- }
+} +#endif
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) curr_device, mmc->part_num);
return 0;
- }
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
} else if ((strcmp(argv[1], "open") == 0) ||
(strcmp(argv[1], "close") == 0)) {int dev;struct mmc *mmc;u32 ack, part_num, access = 0;if (argc == 4) {dev = simple_strtoul(argv[2], NULL, 10);part_num = simple_strtoul(argv[3], NULL, 10);} else {return CMD_RET_USAGE;}mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("SD device cannot be opened/closed\n");return 1;}if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {printf("Invalid boot partition number:\n");printf("Boot partition number cannot be <= 0\n");printf("EMMC44 supports only 2 boot partitions\n");
What means? EMMC44 supports only 2 boot partitions?
return 1;}if (strcmp(argv[1], "open") == 0)access = part_num; /* enable R/W access to boot part*/if (strcmp(argv[1], "close") == 0)
else if?
access = 0; /* No access to boot partition *//* acknowledge to be sent during boot operation */ack = 1;
ack is always set to 1? then Can't initialize ack value as 1. Otherwise, boot_part_access(mmc, 1, part_num, access)?
Best Regards, Jaehoon Chung
return boot_part_access(mmc, ack, part_num, access);- } else if (strcmp(argv[1], "bootpart") == 0) {
int dev;dev = simple_strtoul(argv[2], NULL, 10);u32 bootsize = simple_strtoul(argv[3], NULL, 10);u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);struct mmc *mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("It is not a EMMC device\n");return 1;}if (0 == mmc_boot_partition_size_change(mmc,bootsize, rpmbsize)) {printf("EMMC boot partition Size %d MB\n", bootsize);printf("EMMC RPMB partition Size %d MB\n", rpmbsize);return 0;} else {printf("EMMC boot partition Size change Failed.\n");return 1;}+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
- } state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ;
@@ -324,5 +421,14 @@ U_BOOT_CMD( "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n"
- "mmc list - lists available devices");
- "mmc list - lists available devices\n"
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
- "mmc open <dev> <boot_partition>\n"
- " - Enable boot_part for booting and enable R/W access of boot_part\n"
- "mmc close <dev> <boot_partition>\n"
- " - Enable boot_part for booting and disable access to boot_part\n"
- "mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
- " - change sizes of boot and RPMB partions of specified device\n"
#endif
- );
+#endif /* !CONFIG_GENERIC_MMC */
Hi Jaehoon,
Please find the responses below
Thanks & Regards Amarendra Reddy
On 5 April 2013 11:51, Jaehoon Chung jh80.chung@samsung.com wrote:
Hi Amar,
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds commands to access(open/close) and resize boot
partitions on EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Combined the common piece of code between 'open' and 'close' operations.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Added a new funtion boot_part_access() to combine the common
parts of
'mmc open' and 'mmc close' functionalities. 2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doingso user
can specify which boot partition to be accessed (opened / closed).Changes since V5: 1)Updated minor nits in response to review comments.
Changes since V6: No change.
Changes since V7: 1)The piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the
macro
CONFIG_SUPPORT_EMMC_BOOT is defined.common/cmd_mmc.c | 110
++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 108 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..c5f60a2 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -147,6 +147,36 @@ U_BOOT_CMD( "- display info of the current MMC device" );
+#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32
access) Why do you use u32? I know that just used 8bit.
Yes, just 8bit would suffice. I will update it.
+{
int err;err = mmc_boot_part_access(mmc, ack, part_num, access);if ((err == 0) && (access != 0)) {printf("\t\t\t!!!Notice!!!\n");printf("!You must close EMMC boot Partition");printf("after all images are written\n");printf("!EMMC boot partition has continuity");printf("at image writing time.\n");printf("!So, do not close the boot partition");printf("before all images are written.\n");return 0;} else if ((err == 0) && (access == 0))return 0;else if ((err != 0) && (access != 0)) {printf("EMMC boot partition-%d OPEN Failed.\n", part_num);return 1;} else {printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);return 1;}+} +#endif
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
{ enum mmc_state state; @@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
curr_device, mmc->part_num); return 0;
}+#ifdef CONFIG_SUPPORT_EMMC_BOOT
} else if ((strcmp(argv[1], "open") == 0) ||(strcmp(argv[1], "close") == 0)) {int dev;struct mmc *mmc;u32 ack, part_num, access = 0;if (argc == 4) {dev = simple_strtoul(argv[2], NULL, 10);part_num = simple_strtoul(argv[3], NULL, 10);} else {return CMD_RET_USAGE;}mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("SD device cannot be opened/closed\n");return 1;}if ((part_num <= 0) || (part_num >MMC_NUM_BOOT_PARTITION)) {
printf("Invalid boot partition number:\n");printf("Boot partition number cannot be <= 0\n");printf("EMMC44 supports only 2 boot partitions\n");What means? EMMC44 supports only 2 boot partitions?
As per the eMMC 4.4 specification, eMMC 4.4 has 1 RPMB partition, 2 Boot partitions and 4 General Purpose partitions. As there are only 2 Boot partitions, we restrict the user not to use an invalid partition number.
return 1;
}if (strcmp(argv[1], "open") == 0)access = part_num; /* enable R/W access to bootpart*/
if (strcmp(argv[1], "close") == 0)else if?
Even 'else if' is fine, but I wanted to explicitly check the string in both cases.
access = 0; /* No access to boot partition *//* acknowledge to be sent during boot operation */ack = 1;ack is always set to 1? then Can't initialize ack value as 1. Otherwise, boot_part_access(mmc, 1, part_num, access)?
As per JEDEC Standard 'ack' can be 0 / 1.
Right now we are always using ack=1. Is it OK to use "boot_part_access(mmc, 1, part_num, access)" with a hardcoded value '1' in the function call ?
Best Regards,
Jaehoon Chung
return boot_part_access(mmc, ack, part_num, access);} else if (strcmp(argv[1], "bootpart") == 0) {int dev;dev = simple_strtoul(argv[2], NULL, 10);u32 bootsize = simple_strtoul(argv[3], NULL, 10);u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);struct mmc *mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("It is not a EMMC device\n");return 1;}if (0 == mmc_boot_partition_size_change(mmc,bootsize,rpmbsize)) {
printf("EMMC boot partition Size %d MB\n",bootsize);
printf("EMMC RPMB partition Size %d MB\n",rpmbsize);
return 0;} else {printf("EMMC boot partition Size changeFailed.\n");
return 1;}+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
} state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ;@@ -324,5 +421,14 @@ U_BOOT_CMD( "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device
[partition]\n"
"mmc list - lists available devices");
"mmc list - lists available devices\n"+#ifdef CONFIG_SUPPORT_EMMC_BOOT
"mmc open <dev> <boot_partition>\n"" - Enable boot_part for booting and enable R/W access ofboot_part\n"
"mmc close <dev> <boot_partition>\n"" - Enable boot_part for booting and disable access to boot_part\n""mmc bootpart <device num> <boot part size MB> <RPMB part sizeMB>\n"
" - change sizes of boot and RPMB partions of specified device\n"#endif
);+#endif /* !CONFIG_GENERIC_MMC */
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Dear Amarendra,
On 05/04/13 16:39, Amarendra Reddy wrote:
Hi Jaehoon,
Please find the responses below
Thanks & Regards Amarendra Reddy
On 5 April 2013 11:51, Jaehoon Chung jh80.chung@samsung.com wrote:
Hi Amar,
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds commands to access(open/close) and resize boot
partitions on EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Combined the common piece of code between 'open' and 'close' operations.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Added a new funtion boot_part_access() to combine the common
parts of
'mmc open' and 'mmc close' functionalities. 2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doingso user
can specify which boot partition to be accessed (opened / closed).Changes since V5: 1)Updated minor nits in response to review comments.
Changes since V6: No change.
Changes since V7: 1)The piece of code involved in open/close and resize of EMMC boot partition has been made conditional and is enabled only if the
macro
CONFIG_SUPPORT_EMMC_BOOT is defined.common/cmd_mmc.c | 110
++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 108 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..c5f60a2 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -147,6 +147,36 @@ U_BOOT_CMD( "- display info of the current MMC device" );
+#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int boot_part_access(struct mmc *mmc, u32 ack, u32 part_num, u32
access) Why do you use u32? I know that just used 8bit.
Yes, just 8bit would suffice. I will update it.
+{
int err;err = mmc_boot_part_access(mmc, ack, part_num, access);if ((err == 0) && (access != 0)) {printf("\t\t\t!!!Notice!!!\n");printf("!You must close EMMC boot Partition");printf("after all images are written\n");printf("!EMMC boot partition has continuity");printf("at image writing time.\n");printf("!So, do not close the boot partition");printf("before all images are written.\n");return 0;} else if ((err == 0) && (access == 0))return 0;else if ((err != 0) && (access != 0)) {printf("EMMC boot partition-%d OPEN Failed.\n", part_num);return 1;} else {printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);return 1;}+} +#endif
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
{ enum mmc_state state; @@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
curr_device, mmc->part_num); return 0;
}+#ifdef CONFIG_SUPPORT_EMMC_BOOT
} else if ((strcmp(argv[1], "open") == 0) ||(strcmp(argv[1], "close") == 0)) {int dev;struct mmc *mmc;u32 ack, part_num, access = 0;if (argc == 4) {dev = simple_strtoul(argv[2], NULL, 10);part_num = simple_strtoul(argv[3], NULL, 10);} else {return CMD_RET_USAGE;}mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("SD device cannot be opened/closed\n");return 1;}if ((part_num <= 0) || (part_num >MMC_NUM_BOOT_PARTITION)) {
printf("Invalid boot partition number:\n");printf("Boot partition number cannot be <= 0\n");printf("EMMC44 supports only 2 boot partitions\n");What means? EMMC44 supports only 2 boot partitions?
As per the eMMC 4.4 specification, eMMC 4.4 has 1 RPMB partition, 2 Boot partitions and 4 General Purpose partitions. As there are only 2 Boot partitions, we restrict the user not to use an invalid partition number.
return 1;
}if (strcmp(argv[1], "open") == 0)access = part_num; /* enable R/W access to bootpart*/
if (strcmp(argv[1], "close") == 0)else if?
Even 'else if' is fine, but I wanted to explicitly check the string in both cases.
Why? I think, It doesn't make sense.
access = 0; /* No access to boot partition *//* acknowledge to be sent during boot operation */ack = 1;ack is always set to 1? then Can't initialize ack value as 1. Otherwise, boot_part_access(mmc, 1, part_num, access)?
As per JEDEC Standard 'ack' can be 0 / 1.
Right now we are always using ack=1. Is it OK to use "boot_part_access(mmc, 1, part_num, access)" with a hardcoded value '1' in the function call ?
Yes, It's a constant.
Best Regards,
Jaehoon Chung
return boot_part_access(mmc, ack, part_num, access);} else if (strcmp(argv[1], "bootpart") == 0) {int dev;dev = simple_strtoul(argv[2], NULL, 10);u32 bootsize = simple_strtoul(argv[3], NULL, 10);u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);struct mmc *mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("It is not a EMMC device\n");return 1;}if (0 == mmc_boot_partition_size_change(mmc,bootsize,rpmbsize)) {
printf("EMMC boot partition Size %d MB\n",bootsize);
printf("EMMC RPMB partition Size %d MB\n",rpmbsize);
return 0;} else {printf("EMMC boot partition Size changeFailed.\n");
return 1;}+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
} state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ;@@ -324,5 +421,14 @@ U_BOOT_CMD( "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device
[partition]\n"
"mmc list - lists available devices");
"mmc list - lists available devices\n"+#ifdef CONFIG_SUPPORT_EMMC_BOOT
"mmc open <dev> <boot_partition>\n"" - Enable boot_part for booting and enable R/W access ofboot_part\n"
"mmc close <dev> <boot_partition>\n"" - Enable boot_part for booting and disable access to boot_part\n""mmc bootpart <device num> <boot part size MB> <RPMB part sizeMB>\n"
" - change sizes of boot and RPMB partions of specified device\n"#endif
);+#endif /* !CONFIG_GENERIC_MMC */
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang.
Dear Minkyu,
Thankyou for the review comments. Please find my responses below.
Thanks & Regards Amarendra Reddy
On 9 April 2013 16:25, Minkyu Kang mk7.kang@samsung.com wrote:
Dear Amarendra,
On 05/04/13 16:39, Amarendra Reddy wrote:
Hi Jaehoon,
Please find the responses below
Thanks & Regards Amarendra Reddy
On 5 April 2013 11:51, Jaehoon Chung jh80.chung@samsung.com wrote:
Hi Amar,
On 04/03/2013 11:08 PM, Amar wrote:
This patch adds commands to access(open/close) and resize boot
partitions on EMMC.
Signed-off-by: Amar amarendra.xt@samsung.com
Changes since V1: 1)Combined the common piece of code between 'open' and 'close' operations.
Changes since V2: 1)Updation of commit message and resubmition of proper patch set.
Changes since V3: No change.
Changes since V4: 1)Added a new funtion boot_part_access() to combine the common
parts of
'mmc open' and 'mmc close' functionalities. 2)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doingso user
can specify which boot partition to be accessed (opened /closed).
Changes since V5: 1)Updated minor nits in response to review comments.
Changes since V6: No change.
Changes since V7: 1)The piece of code involved in open/close and resize of EMMC
boot
partition has been made conditional and is enabled only if themacro
CONFIG_SUPPORT_EMMC_BOOT is defined.common/cmd_mmc.c | 110
++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 108 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..c5f60a2 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -147,6 +147,36 @@ U_BOOT_CMD( "- display info of the current MMC device" );
+#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int boot_part_access(struct mmc *mmc, u32 ack, u32 part_num,
u32
access) Why do you use u32? I know that just used 8bit.
Yes, just 8bit would suffice. I will update it.
+{
int err;err = mmc_boot_part_access(mmc, ack, part_num, access);if ((err == 0) && (access != 0)) {printf("\t\t\t!!!Notice!!!\n");printf("!You must close EMMC boot Partition");printf("after all images are written\n");printf("!EMMC boot partition has continuity");printf("at image writing time.\n");printf("!So, do not close the boot partition");printf("before all images are written.\n");return 0;} else if ((err == 0) && (access == 0))return 0;else if ((err != 0) && (access != 0)) {printf("EMMC boot partition-%d OPEN Failed.\n",part_num);
return 1;} else {printf("EMMC boot partition-%d CLOSE Failed.\n",part_num);
return 1;}+} +#endif
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *
const
argv[])
{ enum mmc_state state; @@ -248,8 +278,75 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
curr_device, mmc->part_num); return 0;
}+#ifdef CONFIG_SUPPORT_EMMC_BOOT
} else if ((strcmp(argv[1], "open") == 0) ||(strcmp(argv[1], "close") == 0)) {int dev;struct mmc *mmc;u32 ack, part_num, access = 0;if (argc == 4) {dev = simple_strtoul(argv[2], NULL, 10);part_num = simple_strtoul(argv[3], NULL, 10);} else {return CMD_RET_USAGE;}mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("SD device cannot be opened/closed\n");return 1;}if ((part_num <= 0) || (part_num >MMC_NUM_BOOT_PARTITION)) {
printf("Invalid boot partition number:\n");printf("Boot partition number cannot be <= 0\n");printf("EMMC44 supports only 2 bootpartitions\n");
What means? EMMC44 supports only 2 boot partitions?
As per the eMMC 4.4 specification, eMMC 4.4 has 1 RPMB partition, 2 Boot partitions and 4 General Purpose partitions. As there are only 2 Boot partitions, we restrict the user not to use an invalid partition number.
return 1;
}if (strcmp(argv[1], "open") == 0)access = part_num; /* enable R/W access to bootpart*/
if (strcmp(argv[1], "close") == 0)else if?
Even 'else if' is fine, but I wanted to explicitly check the string in
both
cases.
Why? I think, It doesn't make sense. OK. I will replace the above with 'else if'.
access = 0; /* No access to boot partition *//* acknowledge to be sent during boot operation */ack = 1;ack is always set to 1? then Can't initialize ack value as 1. Otherwise, boot_part_access(mmc, 1, part_num, access)?
As per JEDEC Standard 'ack' can be 0 / 1.
Right now we are always using ack=1. Is it OK to use "boot_part_access(mmc, 1, part_num, access)" with a hardcoded value '1' in the function call ?
Yes, It's a constant.
I meant from uboot coding standard point of view. Ok. I shall use 'boot_part_access(mmc, 1, part_num, access)' in next patchset.
Best Regards,
Jaehoon Chung
return boot_part_access(mmc, ack, part_num, access);} else if (strcmp(argv[1], "bootpart") == 0) {int dev;dev = simple_strtoul(argv[2], NULL, 10);u32 bootsize = simple_strtoul(argv[3], NULL, 10);u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);struct mmc *mmc = find_mmc_device(dev);if (!mmc) {printf("no mmc device at slot %x\n", dev);return 1;}if (IS_SD(mmc)) {printf("It is not a EMMC device\n");return 1;}if (0 == mmc_boot_partition_size_change(mmc,bootsize,rpmbsize)) {
printf("EMMC boot partition Size %d MB\n",bootsize);
printf("EMMC RPMB partition Size %d MB\n",rpmbsize);
return 0;} else {printf("EMMC boot partition Size changeFailed.\n");
return 1;}+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
} state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ;@@ -324,5 +421,14 @@ U_BOOT_CMD( "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device
[partition]\n"
"mmc list - lists available devices");
"mmc list - lists available devices\n"+#ifdef CONFIG_SUPPORT_EMMC_BOOT
"mmc open <dev> <boot_partition>\n"" - Enable boot_part for booting and enable R/W access ofboot_part\n"
"mmc close <dev> <boot_partition>\n"" - Enable boot_part for booting and disable access toboot_part\n"
"mmc bootpart <device num> <boot part size MB> <RPMB part sizeMB>\n"
" - change sizes of boot and RPMB partions of specified device\n"#endif
);+#endif /* !CONFIG_GENERIC_MMC */
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang.
participants (4)
-
Amar -
Amarendra Reddy -
Jaehoon Chung -
Minkyu Kang